2 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/sdram.h>
11 /* Board-specific header. */
12 #include <qts/sdram_config.h>
14 static const struct socfpga_sdram_config sdram_config
= {
16 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE
<<
17 SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB
) |
18 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL
<<
19 SDR_CTRLGRP_CTRLCFG_MEMBL_LSB
) |
20 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER
<<
21 SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB
) |
22 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN
<<
23 SDR_CTRLGRP_CTRLCFG_ECCEN_LSB
) |
24 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN
<<
25 SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB
) |
26 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN
<<
27 SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB
) |
28 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT
<<
29 SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB
) |
30 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN
<<
31 SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB
) |
32 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS
<<
33 SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB
),
35 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL
<<
36 SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB
) |
37 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL
<<
38 SDR_CTRLGRP_DRAMTIMING1_TAL_LSB
) |
39 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL
<<
40 SDR_CTRLGRP_DRAMTIMING1_TCL_LSB
) |
41 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD
<<
42 SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB
) |
43 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW
<<
44 SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB
) |
45 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC
<<
46 SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB
),
48 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI
<<
49 SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB
) |
50 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD
<<
51 SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB
) |
52 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP
<<
53 SDR_CTRLGRP_DRAMTIMING2_TRP_LSB
) |
54 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR
<<
55 SDR_CTRLGRP_DRAMTIMING2_TWR_LSB
) |
56 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR
<<
57 SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB
),
59 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
<<
60 SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB
) |
61 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS
<<
62 SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB
) |
63 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC
<<
64 SDR_CTRLGRP_DRAMTIMING3_TRC_LSB
) |
65 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD
<<
66 SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB
) |
67 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD
<<
68 SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB
),
70 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
<<
71 SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB
) |
72 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT
<<
73 SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB
),
75 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES
<<
76 SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB
) |
77 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES
<<
78 SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB
),
80 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ
<<
81 SDR_CTRLGRP_DRAMODT_READ_LSB
) |
82 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE
<<
83 SDR_CTRLGRP_DRAMODT_WRITE_LSB
),
85 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS
<<
86 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB
) |
87 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS
<<
88 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB
) |
89 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS
<<
90 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB
) |
91 ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS
- 1) <<
92 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB
),
94 (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH
<<
95 SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB
),
97 (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH
<<
98 SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB
),
100 (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN
<<
101 SDR_CTRLGRP_DRAMINTR_INTREN_LSB
),
103 (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK
<<
104 SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB
),
106 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL
<<
107 SDR_CTRLGRP_STATICCFG_MEMBL_LSB
) |
108 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA
<<
109 SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB
),
111 (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH
<<
112 SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB
),
114 (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH
<<
115 SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB
),
117 (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP
<<
118 SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB
),
120 (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP
<<
121 SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB
),
123 (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP
<<
124 SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB
),
126 (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP
<<
127 SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB
),
129 (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR
<<
130 SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB
),
132 (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN
<<
133 SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB
),
134 .fpgaport_rst
= CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST
,
136 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
<<
137 SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB
) |
138 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC
<<
139 SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB
),
141 (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY
<<
142 SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB
),
144 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0
<<
145 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB
),
147 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32
<<
148 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB
) |
149 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0
<<
150 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB
),
152 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14
<<
153 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB
),
155 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46
<<
156 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB
),
158 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0
<<
159 SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB
),
161 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32
<<
162 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB
) |
163 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0
<<
164 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB
),
166 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4
<<
167 SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB
),
169 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36
<<
170 SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB
),
172 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0
<<
173 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB
),
175 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32
<<
176 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB
),
178 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64
<<
179 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB
),
180 .phy_ctrl0
= CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0
,
183 static const struct socfpga_sdram_rw_mgr_config rw_mgr_config
= {
184 .activate_0_and_1
= RW_MGR_ACTIVATE_0_AND_1
,
185 .activate_0_and_1_wait1
= RW_MGR_ACTIVATE_0_AND_1_WAIT1
,
186 .activate_0_and_1_wait2
= RW_MGR_ACTIVATE_0_AND_1_WAIT2
,
187 .activate_1
= RW_MGR_ACTIVATE_1
,
188 .clear_dqs_enable
= RW_MGR_CLEAR_DQS_ENABLE
,
189 .guaranteed_read
= RW_MGR_GUARANTEED_READ
,
190 .guaranteed_read_cont
= RW_MGR_GUARANTEED_READ_CONT
,
191 .guaranteed_write
= RW_MGR_GUARANTEED_WRITE
,
192 .guaranteed_write_wait0
= RW_MGR_GUARANTEED_WRITE_WAIT0
,
193 .guaranteed_write_wait1
= RW_MGR_GUARANTEED_WRITE_WAIT1
,
194 .guaranteed_write_wait2
= RW_MGR_GUARANTEED_WRITE_WAIT2
,
195 .guaranteed_write_wait3
= RW_MGR_GUARANTEED_WRITE_WAIT3
,
197 .idle_loop1
= RW_MGR_IDLE_LOOP1
,
198 .idle_loop2
= RW_MGR_IDLE_LOOP2
,
199 .init_reset_0_cke_0
= RW_MGR_INIT_RESET_0_CKE_0
,
200 .init_reset_1_cke_0
= RW_MGR_INIT_RESET_1_CKE_0
,
201 .lfsr_wr_rd_bank_0
= RW_MGR_LFSR_WR_RD_BANK_0
,
202 .lfsr_wr_rd_bank_0_data
= RW_MGR_LFSR_WR_RD_BANK_0_DATA
,
203 .lfsr_wr_rd_bank_0_dqs
= RW_MGR_LFSR_WR_RD_BANK_0_DQS
,
204 .lfsr_wr_rd_bank_0_nop
= RW_MGR_LFSR_WR_RD_BANK_0_NOP
,
205 .lfsr_wr_rd_bank_0_wait
= RW_MGR_LFSR_WR_RD_BANK_0_WAIT
,
206 .lfsr_wr_rd_bank_0_wl_1
= RW_MGR_LFSR_WR_RD_BANK_0_WL_1
,
207 .lfsr_wr_rd_dm_bank_0
= RW_MGR_LFSR_WR_RD_DM_BANK_0
,
208 .lfsr_wr_rd_dm_bank_0_data
= RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA
,
209 .lfsr_wr_rd_dm_bank_0_dqs
= RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS
,
210 .lfsr_wr_rd_dm_bank_0_nop
= RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP
,
211 .lfsr_wr_rd_dm_bank_0_wait
= RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT
,
212 .lfsr_wr_rd_dm_bank_0_wl_1
= RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1
,
213 .mrs0_dll_reset
= RW_MGR_MRS0_DLL_RESET
,
214 .mrs0_dll_reset_mirr
= RW_MGR_MRS0_DLL_RESET_MIRR
,
215 .mrs0_user
= RW_MGR_MRS0_USER
,
216 .mrs0_user_mirr
= RW_MGR_MRS0_USER_MIRR
,
218 .mrs1_mirr
= RW_MGR_MRS1_MIRR
,
220 .mrs2_mirr
= RW_MGR_MRS2_MIRR
,
222 .mrs3_mirr
= RW_MGR_MRS3_MIRR
,
223 .precharge_all
= RW_MGR_PRECHARGE_ALL
,
224 .read_b2b
= RW_MGR_READ_B2B
,
225 .read_b2b_wait1
= RW_MGR_READ_B2B_WAIT1
,
226 .read_b2b_wait2
= RW_MGR_READ_B2B_WAIT2
,
227 .refresh_all
= RW_MGR_REFRESH_ALL
,
228 .rreturn
= RW_MGR_RETURN
,
229 .sgle_read
= RW_MGR_SGLE_READ
,
232 .true_mem_data_mask_width
= RW_MGR_TRUE_MEM_DATA_MASK_WIDTH
,
233 .mem_address_mirroring
= RW_MGR_MEM_ADDRESS_MIRRORING
,
234 .mem_data_mask_width
= RW_MGR_MEM_DATA_MASK_WIDTH
,
235 .mem_data_width
= RW_MGR_MEM_DATA_WIDTH
,
236 .mem_dq_per_read_dqs
= RW_MGR_MEM_DQ_PER_READ_DQS
,
237 .mem_dq_per_write_dqs
= RW_MGR_MEM_DQ_PER_WRITE_DQS
,
238 .mem_if_read_dqs_width
= RW_MGR_MEM_IF_READ_DQS_WIDTH
,
239 .mem_if_write_dqs_width
= RW_MGR_MEM_IF_WRITE_DQS_WIDTH
,
240 .mem_number_of_cs_per_dimm
= RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM
,
241 .mem_number_of_ranks
= RW_MGR_MEM_NUMBER_OF_RANKS
,
242 .mem_virtual_groups_per_read_dqs
=
243 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
,
244 .mem_virtual_groups_per_write_dqs
=
245 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS
,
248 struct socfpga_sdram_io_config io_config
= {
249 .delay_per_dchain_tap
= IO_DELAY_PER_DCHAIN_TAP
,
250 .delay_per_dqs_en_dchain_tap
= IO_DELAY_PER_DQS_EN_DCHAIN_TAP
,
251 .delay_per_opa_tap
= IO_DELAY_PER_OPA_TAP
,
252 .dll_chain_length
= IO_DLL_CHAIN_LENGTH
,
253 .dqdqs_out_phase_max
= IO_DQDQS_OUT_PHASE_MAX
,
254 .dqs_en_delay_max
= IO_DQS_EN_DELAY_MAX
,
255 .dqs_en_delay_offset
= IO_DQS_EN_DELAY_OFFSET
,
256 .dqs_en_phase_max
= IO_DQS_EN_PHASE_MAX
,
257 .dqs_in_delay_max
= IO_DQS_IN_DELAY_MAX
,
258 .dqs_in_reserve
= IO_DQS_IN_RESERVE
,
259 .dqs_out_reserve
= IO_DQS_OUT_RESERVE
,
260 .io_in_delay_max
= IO_IO_IN_DELAY_MAX
,
261 .io_out1_delay_max
= IO_IO_OUT1_DELAY_MAX
,
262 .io_out2_delay_max
= IO_IO_OUT2_DELAY_MAX
,
263 .shift_dqs_en_when_shift_dqs
= IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
,
266 struct socfpga_sdram_misc_config misc_config
= {
267 .afi_rate_ratio
= AFI_RATE_RATIO
,
268 .calib_lfifo_offset
= CALIB_LFIFO_OFFSET
,
269 .calib_vfifo_offset
= CALIB_VFIFO_OFFSET
,
270 .enable_super_quick_calibration
= ENABLE_SUPER_QUICK_CALIBRATION
,
271 .max_latency_count_width
= MAX_LATENCY_COUNT_WIDTH
,
272 .read_valid_fifo_size
= READ_VALID_FIFO_SIZE
,
273 .reg_file_init_seq_signature
= REG_FILE_INIT_SEQ_SIGNATURE
,
274 .tinit_cntr0_val
= TINIT_CNTR0_VAL
,
275 .tinit_cntr1_val
= TINIT_CNTR1_VAL
,
276 .tinit_cntr2_val
= TINIT_CNTR2_VAL
,
277 .treset_cntr0_val
= TRESET_CNTR0_VAL
,
278 .treset_cntr1_val
= TRESET_CNTR1_VAL
,
279 .treset_cntr2_val
= TRESET_CNTR2_VAL
,
282 const struct socfpga_sdram_config
*socfpga_get_sdram_config(void)
284 return &sdram_config
;
287 void socfpga_get_seq_ac_init(const u32
**init
, unsigned int *nelem
)
290 *nelem
= ARRAY_SIZE(ac_rom_init
);
293 void socfpga_get_seq_inst_init(const u32
**init
, unsigned int *nelem
)
295 *init
= inst_rom_init
;
296 *nelem
= ARRAY_SIZE(inst_rom_init
);
299 const struct socfpga_sdram_rw_mgr_config
*socfpga_get_sdram_rwmgr_config(void)
301 return &rw_mgr_config
;
304 const struct socfpga_sdram_io_config
*socfpga_get_sdram_io_config(void)
309 const struct socfpga_sdram_misc_config
*socfpga_get_sdram_misc_config(void)