arch/arm/mach-sunxi/Kconfig

   1 if ARCH_SUNXI
   2
   3 config SPL_LDSCRIPT
   4         default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
   5
   6 config IDENT_STRING
   7         default " Allwinner Technology"
   8
   9 config SUNXI_HIGH_SRAM
  10         bool
  11         default n
  12         ---help---
  13         Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
  14         with the first SRAM region being located at address 0.
  15         Some newer SoCs map the boot ROM at address 0 instead and move the
  16         SRAM to 64KB, just behind the mask ROM.
  17         Chips using the latter setup are supposed to select this option to
  18         adjust the addresses accordingly.
  19
  20 # Note only one of these may be selected at a time! But hidden choices are
  21 # not supported by Kconfig
  22 config SUNXI_GEN_SUN4I
  23         bool
  24         ---help---
  25         Select this for sunxi SoCs which have resets and clocks set up
  26         as the original A10 (mach-sun4i).
  27
  28 config SUNXI_GEN_SUN6I
  29         bool
  30         ---help---
  31         Select this for sunxi SoCs which have sun6i like periphery, like
  32         separate ahb reset control registers, custom pmic bus, new style
  33         watchdog, etc.
  34
  35 config SUNXI_DRAM_DW
  36         bool
  37         ---help---
  38         Select this for sunxi SoCs which uses a DRAM controller like the
  39         DesignWare controller used in H3, mainly SoCs after H3, which do
  40         not have official open-source DRAM initialization code, but can
  41         use modified H3 DRAM initialization code.
  42
  43 if SUNXI_DRAM_DW
  44 config SUNXI_DRAM_DW_16BIT
  45         bool
  46         ---help---
  47         Select this for sunxi SoCs with DesignWare DRAM controller and
  48         have only 16-bit memory buswidth.
  49
  50 config SUNXI_DRAM_DW_32BIT
  51         bool
  52         ---help---
  53         Select this for sunxi SoCs with DesignWare DRAM controller with
  54         32-bit memory buswidth.
  55 endif
  56
  57 config MACH_SUNXI_H3_H5
  58         bool
  59         select DM_I2C
  60         select SUNXI_DE2
  61         select SUNXI_DRAM_DW
  62         select SUNXI_DRAM_DW_32BIT
  63         select SUNXI_GEN_SUN6I
  64         select SUPPORT_SPL
  65         imply ENV_IS_IN_MMC
  66
  67 choice
  68         prompt "Sunxi SoC Variant"
  69         optional
  70
  71 config MACH_SUN4I
  72         bool "sun4i (Allwinner A10)"
  73         select CPU_V7
  74         select ARM_CORTEX_CPU_IS_UP
  75         select SUNXI_GEN_SUN4I
  76         select SUPPORT_SPL
  77         imply ENV_IS_IN_MMC
  78
  79 config MACH_SUN5I
  80         bool "sun5i (Allwinner A13)"
  81         select CPU_V7
  82         select ARM_CORTEX_CPU_IS_UP
  83         select SUNXI_GEN_SUN4I
  84         select SUPPORT_SPL
  85
  86 config MACH_SUN6I
  87         bool "sun6i (Allwinner A31)"
  88         select CPU_V7
  89         select CPU_V7_HAS_NONSEC
  90         select CPU_V7_HAS_VIRT
  91         select ARCH_SUPPORT_PSCI
  92         select SUNXI_GEN_SUN6I
  93         select SUPPORT_SPL
  94         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
  95         imply ENV_IS_IN_MMC
  96
  97 config MACH_SUN7I
  98         bool "sun7i (Allwinner A20)"
  99         select CPU_V7
 100         select CPU_V7_HAS_NONSEC
 101         select CPU_V7_HAS_VIRT
 102         select ARCH_SUPPORT_PSCI
 103         select SUNXI_GEN_SUN4I
 104         select SUPPORT_SPL
 105         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 106         imply ENV_IS_IN_MMC
 107
 108 config MACH_SUN8I_A23
 109         bool "sun8i (Allwinner A23)"
 110         select CPU_V7
 111         select CPU_V7_HAS_NONSEC
 112         select CPU_V7_HAS_VIRT
 113         select ARCH_SUPPORT_PSCI
 114         select SUNXI_GEN_SUN6I
 115         select SUPPORT_SPL
 116         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 117         imply ENV_IS_IN_MMC
 118
 119 config MACH_SUN8I_A33
 120         bool "sun8i (Allwinner A33)"
 121         select CPU_V7
 122         select CPU_V7_HAS_NONSEC
 123         select CPU_V7_HAS_VIRT
 124         select ARCH_SUPPORT_PSCI
 125         select SUNXI_GEN_SUN6I
 126         select SUPPORT_SPL
 127         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 128
 129 config MACH_SUN8I_A83T
 130         bool "sun8i (Allwinner A83T)"
 131         select CPU_V7
 132         select SUNXI_GEN_SUN6I
 133         select SUPPORT_SPL
 134
 135 config MACH_SUN8I_H3
 136         bool "sun8i (Allwinner H3)"
 137         select CPU_V7
 138         select CPU_V7_HAS_NONSEC
 139         select CPU_V7_HAS_VIRT
 140         select ARCH_SUPPORT_PSCI
 141         select MACH_SUNXI_H3_H5
 142         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 143         imply ENV_IS_IN_MMC
 144
 145 config MACH_SUN8I_R40
 146         bool "sun8i (Allwinner R40)"
 147         select CPU_V7
 148         select CPU_V7_HAS_NONSEC
 149         select CPU_V7_HAS_VIRT
 150         select ARCH_SUPPORT_PSCI
 151         select SUNXI_GEN_SUN6I
 152         select SUPPORT_SPL
 153         select SUNXI_DRAM_DW
 154         select SUNXI_DRAM_DW_32BIT
 155
 156 config MACH_SUN8I_V3S
 157         bool "sun8i (Allwinner V3s)"
 158         select CPU_V7
 159         select CPU_V7_HAS_NONSEC
 160         select CPU_V7_HAS_VIRT
 161         select ARCH_SUPPORT_PSCI
 162         select SUNXI_GEN_SUN6I
 163         select SUNXI_DRAM_DW
 164         select SUNXI_DRAM_DW_16BIT
 165         select SUPPORT_SPL
 166         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 167
 168 config MACH_SUN9I
 169         bool "sun9i (Allwinner A80)"
 170         select CPU_V7
 171         select SUNXI_HIGH_SRAM
 172         select SUNXI_GEN_SUN6I
 173         select SUPPORT_SPL
 174
 175 config MACH_SUN50I
 176         bool "sun50i (Allwinner A64)"
 177         select ARM64
 178         select DM_I2C
 179         select SUNXI_DE2
 180         select SUNXI_GEN_SUN6I
 181         select SUNXI_HIGH_SRAM
 182         select SUPPORT_SPL
 183         select SUNXI_DRAM_DW
 184         select SUNXI_DRAM_DW_32BIT
 185         select FIT
 186         select SPL_LOAD_FIT
 187
 188 config MACH_SUN50I_H5
 189         bool "sun50i (Allwinner H5)"
 190         select ARM64
 191         select MACH_SUNXI_H3_H5
 192         select SUNXI_HIGH_SRAM
 193         select FIT
 194         select SPL_LOAD_FIT
 195
 196 endchoice
 197
 198 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
 199 config MACH_SUN8I
 200         bool
 201         default y if MACH_SUN8I_A23
 202         default y if MACH_SUN8I_A33
 203         default y if MACH_SUN8I_A83T
 204         default y if MACH_SUNXI_H3_H5
 205         default y if MACH_SUN8I_R40
 206         default y if MACH_SUN8I_V3S
 207
 208 config RESERVE_ALLWINNER_BOOT0_HEADER
 209         bool "reserve space for Allwinner boot0 header"
 210         select ENABLE_ARM_SOC_BOOT0_HOOK
 211         ---help---
 212         Prepend a 1536 byte (empty) header to the U-Boot image file, to be
 213         filled with magic values post build. The Allwinner provided boot0
 214         blob relies on this information to load and execute U-Boot.
 215         Only needed on 64-bit Allwinner boards so far when using boot0.
 216
 217 config ARM_BOOT_HOOK_RMR
 218         bool
 219         depends on ARM64
 220         default y
 221         select ENABLE_ARM_SOC_BOOT0_HOOK
 222         ---help---
 223         Insert some ARM32 code at the very beginning of the U-Boot binary
 224         which uses an RMR register write to bring the core into AArch64 mode.
 225         The very first instruction acts as a switch, since it's carefully
 226         chosen to be a NOP in one mode and a branch in the other, so the
 227         code would only be executed if not already in AArch64.
 228         This allows both the SPL and the U-Boot proper to be entered in
 229         either mode and switch to AArch64 if needed.
 230
 231 if SUNXI_DRAM_DW
 232 config SUNXI_DRAM_DDR3
 233         bool
 234
 235 config SUNXI_DRAM_DDR2
 236         bool
 237
 238 config SUNXI_DRAM_LPDDR3
 239         bool
 240
 241 choice
 242         prompt "DRAM Type and Timing"
 243         default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
 244         default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
 245
 246 config SUNXI_DRAM_DDR3_1333
 247         bool "DDR3 1333"
 248         select SUNXI_DRAM_DDR3
 249         depends on !MACH_SUN8I_V3S
 250         ---help---
 251         This option is the original only supported memory type, which suits
 252         many H3/H5/A64 boards available now.
 253
 254 config SUNXI_DRAM_LPDDR3_STOCK
 255         bool "LPDDR3 with Allwinner stock configuration"
 256         select SUNXI_DRAM_LPDDR3
 257         ---help---
 258         This option is the LPDDR3 timing used by the stock boot0 by
 259         Allwinner.
 260
 261 config SUNXI_DRAM_DDR2_V3S
 262         bool "DDR2 found in V3s chip"
 263         select SUNXI_DRAM_DDR2
 264         depends on MACH_SUN8I_V3S
 265         ---help---
 266         This option is only for the DDR2 memory chip which is co-packaged in
 267         Allwinner V3s SoC.
 268
 269 endchoice
 270 endif
 271
 272 config DRAM_TYPE
 273         int "sunxi dram type"
 274         depends on MACH_SUN8I_A83T
 275         default 3
 276         ---help---
 277         Set the dram type, 3: DDR3, 7: LPDDR3
 278
 279 config DRAM_CLK
 280         int "sunxi dram clock speed"
 281         default 792 if MACH_SUN9I
 282         default 648 if MACH_SUN8I_R40
 283         default 312 if MACH_SUN6I || MACH_SUN8I
 284         default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
 285                        MACH_SUN8I_V3S
 286         default 672 if MACH_SUN50I
 287         ---help---
 288         Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
 289         must be a multiple of 24. For the sun9i (A80), the tested values
 290         (for DDR3-1600) are 312 to 792.
 291
 292 if MACH_SUN5I || MACH_SUN7I
 293 config DRAM_MBUS_CLK
 294         int "sunxi mbus clock speed"
 295         default 300
 296         ---help---
 297         Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
 298
 299 endif
 300
 301 config DRAM_ZQ
 302         int "sunxi dram zq value"
 303         default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
 304         default 127 if MACH_SUN7I
 305         default 14779 if MACH_SUN8I_V3S
 306         default 3881979 if MACH_SUN8I_R40
 307         default 4145117 if MACH_SUN9I
 308         default 3881915 if MACH_SUN50I
 309         ---help---
 310         Set the dram zq value.
 311
 312 config DRAM_ODT_EN
 313         bool "sunxi dram odt enable"
 314         default n if !MACH_SUN8I_A23
 315         default y if MACH_SUN8I_A23
 316         default y if MACH_SUN8I_R40
 317         default y if MACH_SUN50I
 318         ---help---
 319         Select this to enable dram odt (on die termination).
 320
 321 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 322 config DRAM_EMR1
 323         int "sunxi dram emr1 value"
 324         default 0 if MACH_SUN4I
 325         default 4 if MACH_SUN5I || MACH_SUN7I
 326         ---help---
 327         Set the dram controller emr1 value.
 328
 329 config DRAM_TPR3
 330         hex "sunxi dram tpr3 value"
 331         default 0
 332         ---help---
 333         Set the dram controller tpr3 parameter. This parameter configures
 334         the delay on the command lane and also phase shifts, which are
 335         applied for sampling incoming read data. The default value 0
 336         means that no phase/delay adjustments are necessary. Properly
 337         configuring this parameter increases reliability at high DRAM
 338         clock speeds.
 339
 340 config DRAM_DQS_GATING_DELAY
 341         hex "sunxi dram dqs_gating_delay value"
 342         default 0
 343         ---help---
 344         Set the dram controller dqs_gating_delay parmeter. Each byte
 345         encodes the DQS gating delay for each byte lane. The delay
 346         granularity is 1/4 cycle. For example, the value 0x05060606
 347         means that the delay is 5 quarter-cycles for one lane (1.25
 348         cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
 349         The default value 0 means autodetection. The results of hardware
 350         autodetection are not very reliable and depend on the chip
 351         temperature (sometimes producing different results on cold start
 352         and warm reboot). But the accuracy of hardware autodetection
 353         is usually good enough, unless running at really high DRAM
 354         clocks speeds (up to 600MHz). If unsure, keep as 0.
 355
 356 choice
 357         prompt "sunxi dram timings"
 358         default DRAM_TIMINGS_VENDOR_MAGIC
 359         ---help---
 360         Select the timings of the DDR3 chips.
 361
 362 config DRAM_TIMINGS_VENDOR_MAGIC
 363         bool "Magic vendor timings from Android"
 364         ---help---
 365         The same DRAM timings as in the Allwinner boot0 bootloader.
 366
 367 config DRAM_TIMINGS_DDR3_1066F_1333H
 368         bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
 369         ---help---
 370         Use the timings of the standard JEDEC DDR3-1066F speed bin for
 371         DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
 372         for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
 373         used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
 374         or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
 375         that down binning to DDR3-1066F is supported (because DDR3-1066F
 376         uses a bit faster timings than DDR3-1333H).
 377
 378 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
 379         bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
 380         ---help---
 381         Use the timings of the slowest possible JEDEC speed bin for the
 382         selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
 383         DDR3-800E, DDR3-1066G or DDR3-1333J.
 384
 385 endchoice
 386
 387 endif
 388
 389 if MACH_SUN8I_A23
 390 config DRAM_ODT_CORRECTION
 391         int "sunxi dram odt correction value"
 392         default 0
 393         ---help---
 394         Set the dram odt correction value (range -255 - 255). In allwinner
 395         fex files, this option is found in bits 8-15 of the u32 odt_en variable
 396         in the [dram] section. When bit 31 of the odt_en variable is set
 397         then the correction is negative. Usually the value for this is 0.
 398 endif
 399
 400 config SYS_CLK_FREQ
 401         default 1008000000 if MACH_SUN4I
 402         default 1008000000 if MACH_SUN5I
 403         default 1008000000 if MACH_SUN6I
 404         default 912000000 if MACH_SUN7I
 405         default 1008000000 if MACH_SUN8I
 406         default 1008000000 if MACH_SUN9I
 407         default 816000000 if MACH_SUN50I
 408
 409 config SYS_CONFIG_NAME
 410         default "sun4i" if MACH_SUN4I
 411         default "sun5i" if MACH_SUN5I
 412         default "sun6i" if MACH_SUN6I
 413         default "sun7i" if MACH_SUN7I
 414         default "sun8i" if MACH_SUN8I
 415         default "sun9i" if MACH_SUN9I
 416         default "sun50i" if MACH_SUN50I
 417
 418 config SYS_BOARD
 419         default "sunxi"
 420
 421 config SYS_SOC
 422         default "sunxi"
 423
 424 config UART0_PORT_F
 425         bool "UART0 on MicroSD breakout board"
 426         default n
 427         ---help---
 428         Repurpose the SD card slot for getting access to the UART0 serial
 429         console. Primarily useful only for low level u-boot debugging on
 430         tablets, where normal UART0 is difficult to access and requires
 431         device disassembly and/or soldering. As the SD card can't be used
 432         at the same time, the system can be only booted in the FEL mode.
 433         Only enable this if you really know what you are doing.
 434
 435 config OLD_SUNXI_KERNEL_COMPAT
 436         bool "Enable workarounds for booting old kernels"
 437         default n
 438         ---help---
 439         Set this to enable various workarounds for old kernels, this results in
 440         sub-optimal settings for newer kernels, only enable if needed.
 441
 442 config MACPWR
 443         string "MAC power pin"
 444         default ""
 445         help
 446           Set the pin used to power the MAC. This takes a string in the format
 447           understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 448
 449 config MMC0_CD_PIN
 450         string "Card detect pin for mmc0"
 451         default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
 452         default ""
 453         ---help---
 454         Set the card detect pin for mmc0, leave empty to not use cd. This
 455         takes a string in the format understood by sunxi_name_to_gpio, e.g.
 456         PH1 for pin 1 of port H.
 457
 458 config MMC1_CD_PIN
 459         string "Card detect pin for mmc1"
 460         default ""
 461         ---help---
 462         See MMC0_CD_PIN help text.
 463
 464 config MMC2_CD_PIN
 465         string "Card detect pin for mmc2"
 466         default ""
 467         ---help---
 468         See MMC0_CD_PIN help text.
 469
 470 config MMC3_CD_PIN
 471         string "Card detect pin for mmc3"
 472         default ""
 473         ---help---
 474         See MMC0_CD_PIN help text.
 475
 476 config MMC1_PINS
 477         string "Pins for mmc1"
 478         default ""
 479         ---help---
 480         Set the pins used for mmc1, when applicable. This takes a string in the
 481         format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
 482
 483 config MMC2_PINS
 484         string "Pins for mmc2"
 485         default ""
 486         ---help---
 487         See MMC1_PINS help text.
 488
 489 config MMC3_PINS
 490         string "Pins for mmc3"
 491         default ""
 492         ---help---
 493         See MMC1_PINS help text.
 494
 495 config MMC_SUNXI_SLOT_EXTRA
 496         int "mmc extra slot number"
 497         default -1
 498         ---help---
 499         sunxi builds always enable mmc0, some boards also have a second sdcard
 500         slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
 501         support for this.
 502
 503 config INITIAL_USB_SCAN_DELAY
 504         int "delay initial usb scan by x ms to allow builtin devices to init"
 505         default 0
 506         ---help---
 507         Some boards have on board usb devices which need longer than the
 508         USB spec's 1 second to connect from board powerup. Set this config
 509         option to a non 0 value to add an extra delay before the first usb
 510         bus scan.
 511
 512 config USB0_VBUS_PIN
 513         string "Vbus enable pin for usb0 (otg)"
 514         default ""
 515         ---help---
 516         Set the Vbus enable pin for usb0 (otg). This takes a string in the
 517         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 518
 519 config USB0_VBUS_DET
 520         string "Vbus detect pin for usb0 (otg)"
 521         default ""
 522         ---help---
 523         Set the Vbus detect pin for usb0 (otg). This takes a string in the
 524         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 525
 526 config USB0_ID_DET
 527         string "ID detect pin for usb0 (otg)"
 528         default ""
 529         ---help---
 530         Set the ID detect pin for usb0 (otg). This takes a string in the
 531         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 532
 533 config USB1_VBUS_PIN
 534         string "Vbus enable pin for usb1 (ehci0)"
 535         default "PH6" if MACH_SUN4I || MACH_SUN7I
 536         default "PH27" if MACH_SUN6I
 537         ---help---
 538         Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
 539         a string in the format understood by sunxi_name_to_gpio, e.g.
 540         PH1 for pin 1 of port H.
 541
 542 config USB2_VBUS_PIN
 543         string "Vbus enable pin for usb2 (ehci1)"
 544         default "PH3" if MACH_SUN4I || MACH_SUN7I
 545         default "PH24" if MACH_SUN6I
 546         ---help---
 547         See USB1_VBUS_PIN help text.
 548
 549 config USB3_VBUS_PIN
 550         string "Vbus enable pin for usb3 (ehci2)"
 551         default ""
 552         ---help---
 553         See USB1_VBUS_PIN help text.
 554
 555 config I2C0_ENABLE
 556         bool "Enable I2C/TWI controller 0"
 557         default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
 558         default n if MACH_SUN6I || MACH_SUN8I
 559         select CMD_I2C
 560         ---help---
 561         This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
 562         its clock and setting up the bus. This is especially useful on devices
 563         with slaves connected to the bus or with pins exposed through e.g. an
 564         expansion port/header.
 565
 566 config I2C1_ENABLE
 567         bool "Enable I2C/TWI controller 1"
 568         default n
 569         select CMD_I2C
 570         ---help---
 571         See I2C0_ENABLE help text.
 572
 573 config I2C2_ENABLE
 574         bool "Enable I2C/TWI controller 2"
 575         default n
 576         select CMD_I2C
 577         ---help---
 578         See I2C0_ENABLE help text.
 579
 580 if MACH_SUN6I || MACH_SUN7I
 581 config I2C3_ENABLE
 582         bool "Enable I2C/TWI controller 3"
 583         default n
 584         select CMD_I2C
 585         ---help---
 586         See I2C0_ENABLE help text.
 587 endif
 588
 589 if SUNXI_GEN_SUN6I
 590 config R_I2C_ENABLE
 591         bool "Enable the PRCM I2C/TWI controller"
 592         # This is used for the pmic on H3
 593         default y if SY8106A_POWER
 594         select CMD_I2C
 595         ---help---
 596         Set this to y to enable the I2C controller which is part of the PRCM.
 597 endif
 598
 599 if MACH_SUN7I
 600 config I2C4_ENABLE
 601         bool "Enable I2C/TWI controller 4"
 602         default n
 603         select CMD_I2C
 604         ---help---
 605         See I2C0_ENABLE help text.
 606 endif
 607
 608 config AXP_GPIO
 609         bool "Enable support for gpio-s on axp PMICs"
 610         default n
 611         ---help---
 612         Say Y here to enable support for the gpio pins of the axp PMIC ICs.
 613
 614 config VIDEO
 615         bool "Enable graphical uboot console on HDMI, LCD or VGA"
 616         depends on !MACH_SUN8I_A83T
 617         depends on !MACH_SUNXI_H3_H5
 618         depends on !MACH_SUN8I_R40
 619         depends on !MACH_SUN8I_V3S
 620         depends on !MACH_SUN9I
 621         depends on !MACH_SUN50I
 622         default y
 623         ---help---
 624         Say Y here to add support for using a cfb console on the HDMI, LCD
 625         or VGA output found on most sunxi devices. See doc/README.video for
 626         info on how to select the video output and mode.
 627
 628 config VIDEO_HDMI
 629         bool "HDMI output support"
 630         depends on VIDEO && !MACH_SUN8I
 631         default y
 632         ---help---
 633         Say Y here to add support for outputting video over HDMI.
 634
 635 config VIDEO_VGA
 636         bool "VGA output support"
 637         depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
 638         default n
 639         ---help---
 640         Say Y here to add support for outputting video over VGA.
 641
 642 config VIDEO_VGA_VIA_LCD
 643         bool "VGA via LCD controller support"
 644         depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
 645         default n
 646         ---help---
 647         Say Y here to add support for external DACs connected to the parallel
 648         LCD interface driving a VGA connector, such as found on the
 649         Olimex A13 boards.
 650
 651 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
 652         bool "Force sync active high for VGA via LCD controller support"
 653         depends on VIDEO_VGA_VIA_LCD
 654         default n
 655         ---help---
 656         Say Y here if you've a board which uses opendrain drivers for the vga
 657         hsync and vsync signals. Opendrain drivers cannot generate steep enough
 658         positive edges for a stable video output, so on boards with opendrain
 659         drivers the sync signals must always be active high.
 660
 661 config VIDEO_VGA_EXTERNAL_DAC_EN
 662         string "LCD panel power enable pin"
 663         depends on VIDEO_VGA_VIA_LCD
 664         default ""
 665         ---help---
 666         Set the enable pin for the external VGA DAC. This takes a string in the
 667         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 668
 669 config VIDEO_COMPOSITE
 670         bool "Composite video output support"
 671         depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
 672         default n
 673         ---help---
 674         Say Y here to add support for outputting composite video.
 675
 676 config VIDEO_LCD_MODE
 677         string "LCD panel timing details"
 678         depends on VIDEO
 679         default ""
 680         ---help---
 681         LCD panel timing details string, leave empty if there is no LCD panel.
 682         This is in drivers/video/videomodes.c: video_get_params() format, e.g.
 683         x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
 684         Also see: http://linux-sunxi.org/LCD
 685
 686 config VIDEO_LCD_DCLK_PHASE
 687         int "LCD panel display clock phase"
 688         depends on VIDEO
 689         default 1
 690         ---help---
 691         Select LCD panel display clock phase shift, range 0-3.
 692
 693 config VIDEO_LCD_POWER
 694         string "LCD panel power enable pin"
 695         depends on VIDEO
 696         default ""
 697         ---help---
 698         Set the power enable pin for the LCD panel. This takes a string in the
 699         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 700
 701 config VIDEO_LCD_RESET
 702         string "LCD panel reset pin"
 703         depends on VIDEO
 704         default ""
 705         ---help---
 706         Set the reset pin for the LCD panel. This takes a string in the format
 707         understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 708
 709 config VIDEO_LCD_BL_EN
 710         string "LCD panel backlight enable pin"
 711         depends on VIDEO
 712         default ""
 713         ---help---
 714         Set the backlight enable pin for the LCD panel. This takes a string in the
 715         the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
 716         port H.
 717
 718 config VIDEO_LCD_BL_PWM
 719         string "LCD panel backlight pwm pin"
 720         depends on VIDEO
 721         default ""
 722         ---help---
 723         Set the backlight pwm pin for the LCD panel. This takes a string in the
 724         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 725
 726 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
 727         bool "LCD panel backlight pwm is inverted"
 728         depends on VIDEO
 729         default y
 730         ---help---
 731         Set this if the backlight pwm output is active low.
 732
 733 config VIDEO_LCD_PANEL_I2C
 734         bool "LCD panel needs to be configured via i2c"
 735         depends on VIDEO
 736         default n
 737         select CMD_I2C
 738         ---help---
 739         Say y here if the LCD panel needs to be configured via i2c. This
 740         will add a bitbang i2c controller using gpios to talk to the LCD.
 741
 742 config VIDEO_LCD_PANEL_I2C_SDA
 743         string "LCD panel i2c interface SDA pin"
 744         depends on VIDEO_LCD_PANEL_I2C
 745         default "PG12"
 746         ---help---
 747         Set the SDA pin for the LCD i2c interface. This takes a string in the
 748         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 749
 750 config VIDEO_LCD_PANEL_I2C_SCL
 751         string "LCD panel i2c interface SCL pin"
 752         depends on VIDEO_LCD_PANEL_I2C
 753         default "PG10"
 754         ---help---
 755         Set the SCL pin for the LCD i2c interface. This takes a string in the
 756         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 757
 758
 759 # Note only one of these may be selected at a time! But hidden choices are
 760 # not supported by Kconfig
 761 config VIDEO_LCD_IF_PARALLEL
 762         bool
 763
 764 config VIDEO_LCD_IF_LVDS
 765         bool
 766
 767 config SUNXI_DE2
 768         bool
 769         default n
 770
 771 config VIDEO_DE2
 772         bool "Display Engine 2 video driver"
 773         depends on SUNXI_DE2
 774         select DM_VIDEO
 775         select DISPLAY
 776         default y
 777         ---help---
 778         Say y here if you want to build DE2 video driver which is present on
 779         newer SoCs. Currently only HDMI output is supported.
 780
 781
 782 choice
 783         prompt "LCD panel support"
 784         depends on VIDEO
 785         ---help---
 786         Select which type of LCD panel to support.
 787
 788 config VIDEO_LCD_PANEL_PARALLEL
 789         bool "Generic parallel interface LCD panel"
 790         select VIDEO_LCD_IF_PARALLEL
 791
 792 config VIDEO_LCD_PANEL_LVDS
 793         bool "Generic lvds interface LCD panel"
 794         select VIDEO_LCD_IF_LVDS
 795
 796 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
 797         bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
 798         select VIDEO_LCD_SSD2828
 799         select VIDEO_LCD_IF_PARALLEL
 800         ---help---
 801         7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
 802
 803 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
 804         bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
 805         select VIDEO_LCD_ANX9804
 806         select VIDEO_LCD_IF_PARALLEL
 807         select VIDEO_LCD_PANEL_I2C
 808         ---help---
 809         Select this for eDP LCD panels with 4 lanes running at 1.62G,
 810         connected via an ANX9804 bridge chip.
 811
 812 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
 813         bool "Hitachi tx18d42vm LCD panel"
 814         select VIDEO_LCD_HITACHI_TX18D42VM
 815         select VIDEO_LCD_IF_LVDS
 816         ---help---
 817         7.85" 1024x768 Hitachi tx18d42vm LCD panel support
 818
 819 config VIDEO_LCD_TL059WV5C0
 820         bool "tl059wv5c0 LCD panel"
 821         select VIDEO_LCD_PANEL_I2C
 822         select VIDEO_LCD_IF_PARALLEL
 823         ---help---
 824         6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
 825         Aigo M60/M608/M606 tablets.
 826
 827 endchoice
 828
 829 config SATAPWR
 830         string "SATA power pin"
 831         default ""
 832         help
 833           Set the pins used to power the SATA. This takes a string in the
 834           format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
 835           port H.
 836
 837 config GMAC_TX_DELAY
 838         int "GMAC Transmit Clock Delay Chain"
 839         default 0
 840         ---help---
 841         Set the GMAC Transmit Clock Delay Chain value.
 842
 843 config SPL_STACK_R_ADDR
 844         default 0x4fe00000 if MACH_SUN4I
 845         default 0x4fe00000 if MACH_SUN5I
 846         default 0x4fe00000 if MACH_SUN6I
 847         default 0x4fe00000 if MACH_SUN7I
 848         default 0x4fe00000 if MACH_SUN8I
 849         default 0x2fe00000 if MACH_SUN9I
 850         default 0x4fe00000 if MACH_SUN50I
 851
 852 endif