arch/arm/mach-sunxi/clock_sun6i.c

   1 /*
   2  * sun6i specific clock code
   3  *
   4  * (C) Copyright 2007-2012
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * Tom Cubie <tangliang@allwinnertech.com>
   7  *
   8  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/prcm.h>
  17 #include <asm/arch/sys_proto.h>
  18
  19 #ifdef CONFIG_SPL_BUILD
  20 void clock_init_safe(void)
  21 {
  22         struct sunxi_ccm_reg * const ccm =
  23                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  24
  25 #if !defined(CONFIG_MACH_SUN8I_H3) && !defined(CONFIG_MACH_SUN50I)
  26         struct sunxi_prcm_reg * const prcm =
  27                 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
  28
  29         /* Set PLL ldo voltage without this PLL6 does not work properly */
  30         clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
  31                         PRCM_PLL_CTRL_LDO_KEY);
  32         clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
  33                 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
  34                 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
  35         clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
  36 #endif
  37
  38         clock_set_pll1(408000000);
  39
  40         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  41         while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
  42                 ;
  43
  44         writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
  45
  46         writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
  47         if (IS_ENABLED(CONFIG_MACH_SUN6I))
  48                 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
  49 }
  50 #endif
  51
  52 void clock_init_sec(void)
  53 {
  54 #ifdef CONFIG_MACH_SUN8I_H3
  55         struct sunxi_ccm_reg * const ccm =
  56                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  57
  58         setbits_le32(&ccm->ccu_sec_switch,
  59                      CCM_SEC_SWITCH_MBUS_NONSEC |
  60                      CCM_SEC_SWITCH_BUS_NONSEC |
  61                      CCM_SEC_SWITCH_PLL_NONSEC);
  62 #endif
  63 }
  64
  65 void clock_init_uart(void)
  66 {
  67 #if CONFIG_CONS_INDEX < 5
  68         struct sunxi_ccm_reg *const ccm =
  69                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  70
  71         /* uart clock source is apb2 */
  72         writel(APB2_CLK_SRC_OSC24M|
  73                APB2_CLK_RATE_N_1|
  74                APB2_CLK_RATE_M(1),
  75                &ccm->apb2_div);
  76
  77         /* open the clock for uart */
  78         setbits_le32(&ccm->apb2_gate,
  79                      CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
  80                                        CONFIG_CONS_INDEX - 1));
  81
  82         /* deassert uart reset */
  83         setbits_le32(&ccm->apb2_reset_cfg,
  84                      1 << (APB2_RESET_UART_SHIFT +
  85                            CONFIG_CONS_INDEX - 1));
  86 #else
  87         /* enable R_PIO and R_UART clocks, and de-assert resets */
  88         prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
  89 #endif
  90 }
  91
  92 #ifdef CONFIG_SPL_BUILD
  93 void clock_set_pll1(unsigned int clk)
  94 {
  95         struct sunxi_ccm_reg * const ccm =
  96                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  97         const int p = 0;
  98         int k = 1;
  99         int m = 1;
 100
 101         if (clk > 1152000000) {
 102                 k = 2;
 103         } else if (clk > 768000000) {
 104                 k = 3;
 105                 m = 2;
 106         }
 107
 108         /* Switch to 24MHz clock while changing PLL1 */
 109         writel(AXI_DIV_3 << AXI_DIV_SHIFT |
 110                ATB_DIV_2 << ATB_DIV_SHIFT |
 111                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 112                &ccm->cpu_axi_cfg);
 113
 114         /*
 115          * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m   (p is ignored)
 116          * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
 117          */
 118         writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
 119                CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
 120                CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
 121         sdelay(200);
 122
 123         /* Switch CPU to PLL1 */
 124         writel(AXI_DIV_3 << AXI_DIV_SHIFT |
 125                ATB_DIV_2 << ATB_DIV_SHIFT |
 126                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 127                &ccm->cpu_axi_cfg);
 128 }
 129 #endif
 130
 131 void clock_set_pll3(unsigned int clk)
 132 {
 133         struct sunxi_ccm_reg * const ccm =
 134                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 135         const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
 136
 137         if (clk == 0) {
 138                 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
 139                 return;
 140         }
 141
 142         /* PLL3 rate = 24000000 * n / m */
 143         writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
 144                CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
 145                &ccm->pll3_cfg);
 146 }
 147
 148 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 149 {
 150         struct sunxi_ccm_reg * const ccm =
 151                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 152         const int max_n = 32;
 153         int k = 1, m = 2;
 154
 155 #ifdef CONFIG_MACH_SUN8I_H3
 156         clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |
 157                         CCM_PLL5_TUN_INIT_FREQ_MASK,
 158                         CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16));
 159 #endif
 160
 161         if (sigma_delta_enable)
 162                 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
 163
 164         /* PLL5 rate = 24000000 * n * k / m */
 165         if (clk > 24000000 * k * max_n / m) {
 166                 m = 1;
 167                 if (clk > 24000000 * k * max_n / m)
 168                         k = 2;
 169         }
 170         writel(CCM_PLL5_CTRL_EN |
 171                (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
 172                CCM_PLL5_CTRL_UPD |
 173                CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
 174                CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
 175
 176         udelay(5500);
 177 }
 178
 179 #ifdef CONFIG_MACH_SUN6I
 180 void clock_set_mipi_pll(unsigned int clk)
 181 {
 182         struct sunxi_ccm_reg * const ccm =
 183                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 184         unsigned int k, m, n, value, diff;
 185         unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
 186         unsigned int src = clock_get_pll3();
 187
 188         /* All calculations are in KHz to avoid overflows */
 189         clk /= 1000;
 190         src /= 1000;
 191
 192         /* Pick the closest lower clock */
 193         for (k = 1; k <= 4; k++) {
 194                 for (m = 1; m <= 16; m++) {
 195                         for (n = 1; n <= 16; n++) {
 196                                 value = src * n * k / m;
 197                                 if (value > clk)
 198                                         continue;
 199
 200                                 diff = clk - value;
 201                                 if (diff < best_diff) {
 202                                         best_diff = diff;
 203                                         best_k = k;
 204                                         best_m = m;
 205                                         best_n = n;
 206                                 }
 207                                 if (diff == 0)
 208                                         goto done;
 209                         }
 210                 }
 211         }
 212
 213 done:
 214         writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
 215                CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
 216                CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
 217 }
 218 #endif
 219
 220 #if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN50I)
 221 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
 222 {
 223         struct sunxi_ccm_reg * const ccm =
 224                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 225
 226         if (sigma_delta_enable)
 227                 writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0);
 228
 229         writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
 230                (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
 231                CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
 232
 233         while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
 234                 ;
 235 }
 236 #endif
 237
 238 unsigned int clock_get_pll3(void)
 239 {
 240         struct sunxi_ccm_reg *const ccm =
 241                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 242         uint32_t rval = readl(&ccm->pll3_cfg);
 243         int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
 244         int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
 245
 246         /* Multiply by 1000 after dividing by m to avoid integer overflows */
 247         return (24000 * n / m) * 1000;
 248 }
 249
 250 unsigned int clock_get_pll6(void)
 251 {
 252         struct sunxi_ccm_reg *const ccm =
 253                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 254         uint32_t rval = readl(&ccm->pll6_cfg);
 255         int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
 256         int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
 257         return 24000000 * n * k / 2;
 258 }
 259
 260 unsigned int clock_get_mipi_pll(void)
 261 {
 262         struct sunxi_ccm_reg *const ccm =
 263                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 264         uint32_t rval = readl(&ccm->mipi_pll_cfg);
 265         unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
 266         unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
 267         unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
 268         unsigned int src = clock_get_pll3();
 269
 270         /* Multiply by 1000 after dividing by m to avoid integer overflows */
 271         return ((src / 1000) * n * k / m) * 1000;
 272 }
 273
 274 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
 275 {
 276         int pll = clock_get_pll6() * 2;
 277         int div = 1;
 278
 279         while ((pll / div) > hz)
 280                 div++;
 281
 282         writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
 283                clk_cfg);
 284 }