arch/arm/mach-sunxi/cpu_info.c

   1 /*
   2  * (C) Copyright 2007-2011
   3  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   4  * Tom Cubie <tangliang@allwinnertech.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/cpu.h>
  12 #include <asm/arch/clock.h>
  13 #include <axp_pmic.h>
  14 #include <errno.h>
  15
  16 #ifdef CONFIG_MACH_SUN6I
  17 int sunxi_get_ss_bonding_id(void)
  18 {
  19         struct sunxi_ccm_reg * const ccm =
  20                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  21         static int bonding_id = -1;
  22
  23         if (bonding_id != -1)
  24                 return bonding_id;
  25
  26         /* Enable Security System */
  27         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
  28         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
  29
  30         bonding_id = readl(SUNXI_SS_BASE);
  31         bonding_id = (bonding_id >> 16) & 0x7;
  32
  33         /* Disable Security System again */
  34         clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
  35         clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
  36
  37         return bonding_id;
  38 }
  39 #endif
  40
  41 #ifdef CONFIG_MACH_SUN8I
  42 uint sunxi_get_sram_id(void)
  43 {
  44         uint id;
  45
  46         /* Unlock sram info reg, read it, relock */
  47         setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
  48         id = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
  49         clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
  50
  51         return id;
  52 }
  53 #endif
  54
  55 #ifdef CONFIG_DISPLAY_CPUINFO
  56 int print_cpuinfo(void)
  57 {
  58 #ifdef CONFIG_MACH_SUN4I
  59         puts("CPU:   Allwinner A10 (SUN4I)\n");
  60 #elif defined CONFIG_MACH_SUN5I
  61         u32 val = readl(SUNXI_SID_BASE + 0x08);
  62         switch ((val >> 12) & 0xf) {
  63         case 0: puts("CPU:   Allwinner A12 (SUN5I)\n"); break;
  64         case 3: puts("CPU:   Allwinner A13 (SUN5I)\n"); break;
  65         case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
  66         default: puts("CPU:   Allwinner A1X (SUN5I)\n");
  67         }
  68 #elif defined CONFIG_MACH_SUN6I
  69         switch (sunxi_get_ss_bonding_id()) {
  70         case SUNXI_SS_BOND_ID_A31:
  71                 puts("CPU:   Allwinner A31 (SUN6I)\n");
  72                 break;
  73         case SUNXI_SS_BOND_ID_A31S:
  74                 puts("CPU:   Allwinner A31s (SUN6I)\n");
  75                 break;
  76         default:
  77                 printf("CPU:   Allwinner A31? (SUN6I, id: %d)\n",
  78                        sunxi_get_ss_bonding_id());
  79         }
  80 #elif defined CONFIG_MACH_SUN7I
  81         puts("CPU:   Allwinner A20 (SUN7I)\n");
  82 #elif defined CONFIG_MACH_SUN8I_A23
  83         printf("CPU:   Allwinner A23 (SUN8I %04x)\n", sunxi_get_sram_id());
  84 #elif defined CONFIG_MACH_SUN8I_A33
  85         printf("CPU:   Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id());
  86 #elif defined CONFIG_MACH_SUN8I_A83T
  87         printf("CPU:   Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
  88 #elif defined CONFIG_MACH_SUN8I_H3
  89         printf("CPU:   Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
  90 #elif defined CONFIG_MACH_SUN9I
  91         puts("CPU:   Allwinner A80 (SUN9I)\n");
  92 #elif defined CONFIG_MACH_SUN50I
  93         puts("CPU:   Allwinner A64 (SUN50I)\n");
  94 #elif defined CONFIG_MACH_SUN50I_H5
  95         puts("CPU:   Allwinner H5 (SUN50I)\n");
  96 #else
  97 #warning Please update cpu_info.c with correct CPU information
  98         puts("CPU:   SUNXI Family\n");
  99 #endif
 100         return 0;
 101 }
 102 #endif
 103
 104 #ifdef CONFIG_MACH_SUN8I_H3
 105
 106 #define SIDC_PRCTL 0x40
 107 #define SIDC_RDKEY 0x60
 108
 109 #define SIDC_OP_LOCK 0xAC
 110
 111 uint32_t sun8i_efuse_read(uint32_t offset)
 112 {
 113         uint32_t reg_val;
 114
 115         reg_val = readl(SUNXI_SIDC_BASE + SIDC_PRCTL);
 116         reg_val &= ~(((0x1ff) << 16) | 0x3);
 117         reg_val |= (offset << 16);
 118         writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
 119
 120         reg_val &= ~(((0xff) << 8) | 0x3);
 121         reg_val |= (SIDC_OP_LOCK << 8) | 0x2;
 122         writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
 123
 124         while (readl(SUNXI_SIDC_BASE + SIDC_PRCTL) & 0x2);
 125
 126         reg_val &= ~(((0x1ff) << 16) | ((0xff) << 8) | 0x3);
 127         writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
 128
 129         reg_val = readl(SUNXI_SIDC_BASE + SIDC_RDKEY);
 130         return reg_val;
 131 }
 132 #endif
 133
 134 int sunxi_get_sid(unsigned int *sid)
 135 {
 136 #ifdef CONFIG_AXP221_POWER
 137         return axp_get_sid(sid);
 138 #elif defined CONFIG_MACH_SUN8I_H3
 139         /*
 140          * H3 SID controller has a bug, which makes the initial value of
 141          * SUNXI_SID_BASE at boot wrong.
 142          * Read the value directly from SID controller, in order to get
 143          * the correct value, and also refresh the wrong value at
 144          * SUNXI_SID_BASE.
 145          */
 146         int i;
 147
 148         for (i = 0; i< 4; i++)
 149                 sid[i] = sun8i_efuse_read(i * 4);
 150
 151         return 0;
 152 #elif defined SUNXI_SID_BASE
 153         int i;
 154
 155         for (i = 0; i< 4; i++)
 156                 sid[i] = readl((ulong)SUNXI_SID_BASE + 4 * i);
 157
 158         return 0;
 159 #else
 160         return -ENODEV;
 161 #endif
 162 }