1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
10 #include <asm/arch/spl.h>
13 #include <linux/bitops.h>
14 #include <linux/delay.h>
15 #include <linux/libfdt.h>
17 #ifdef CONFIG_SPL_OS_BOOT
18 #error CONFIG_SPL_OS_BOOT is not supported yet
22 * This is a very simple U-Boot image loading implementation, trying to
23 * replicate what the boot ROM is doing when loading the SPL. Because we
24 * know the exact pins where the SPI Flash is connected and also know
25 * that the Read Data Bytes (03h) command is supported, the hardware
26 * configuration is very simple and we don't need the extra flexibility
27 * of the SPI framework. Moreover, we rely on the default settings of
28 * the SPI controler hardware registers and only adjust what needs to
29 * be changed. This is good for the code size and this implementation
30 * adds less than 400 bytes to the SPL.
32 * There are two variants of the SPI controller in Allwinner SoCs:
33 * A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
34 * Both of them are supported.
36 * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
37 * supported at the moment.
40 /*****************************************************************************/
41 /* SUN4I variant of the SPI controller */
42 /*****************************************************************************/
44 #define SUN4I_SPI0_CCTL 0x1C
45 #define SUN4I_SPI0_CTL 0x08
46 #define SUN4I_SPI0_RX 0x00
47 #define SUN4I_SPI0_TX 0x04
48 #define SUN4I_SPI0_FIFO_STA 0x28
49 #define SUN4I_SPI0_BC 0x20
50 #define SUN4I_SPI0_TC 0x24
52 #define SUN4I_CTL_ENABLE BIT(0)
53 #define SUN4I_CTL_MASTER BIT(1)
54 #define SUN4I_CTL_TF_RST BIT(8)
55 #define SUN4I_CTL_RF_RST BIT(9)
56 #define SUN4I_CTL_XCH BIT(10)
58 /*****************************************************************************/
59 /* SUN6I variant of the SPI controller */
60 /*****************************************************************************/
62 #define SUN6I_SPI0_CCTL 0x24
63 #define SUN6I_SPI0_GCR 0x04
64 #define SUN6I_SPI0_TCR 0x08
65 #define SUN6I_SPI0_FIFO_STA 0x1C
66 #define SUN6I_SPI0_MBC 0x30
67 #define SUN6I_SPI0_MTC 0x34
68 #define SUN6I_SPI0_BCC 0x38
69 #define SUN6I_SPI0_TXD 0x200
70 #define SUN6I_SPI0_RXD 0x300
72 #define SUN6I_CTL_ENABLE BIT(0)
73 #define SUN6I_CTL_MASTER BIT(1)
74 #define SUN6I_CTL_SRST BIT(31)
75 #define SUN6I_TCR_XCH BIT(31)
77 /*****************************************************************************/
79 #define CCM_AHB_GATING0 (0x01C20000 + 0x60)
80 #define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c)
81 #ifdef CONFIG_MACH_SUN50I_H6
82 #define CCM_SPI0_CLK (0x03001000 + 0x940)
84 #define CCM_SPI0_CLK (0x01C20000 + 0xA0)
86 #define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0)
88 #define AHB_RESET_SPI0_SHIFT 20
89 #define AHB_GATE_OFFSET_SPI0 20
91 #define SPI0_CLK_DIV_BY_2 0x1000
92 #define SPI0_CLK_DIV_BY_4 0x1001
93 #define SPI0_CLK_DIV_BY_32 0x100f
95 /*****************************************************************************/
98 * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
99 * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
100 * The H6 uses PC0, PC2, PC3, PC5.
102 static void spi0_pinmux_setup(unsigned int pin_function
)
104 /* All chips use PC0 and PC2. */
105 sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function
);
106 sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function
);
108 /* All chips except H6 use PC1, and only H6 uses PC5. */
109 if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6
))
110 sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function
);
112 sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function
);
114 /* Older generations use PC23 for CS, newer ones use PC3. */
115 if (IS_ENABLED(CONFIG_MACH_SUN4I
) || IS_ENABLED(CONFIG_MACH_SUN7I
) ||
116 IS_ENABLED(CONFIG_MACH_SUN8I_R40
))
117 sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function
);
119 sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function
);
122 static bool is_sun6i_gen_spi(void)
124 return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I
) ||
125 IS_ENABLED(CONFIG_MACH_SUN50I_H6
);
128 static uintptr_t spi0_base_address(void)
130 if (IS_ENABLED(CONFIG_MACH_SUN8I_R40
))
133 if (IS_ENABLED(CONFIG_MACH_SUN50I_H6
))
136 if (!is_sun6i_gen_spi() ||
137 IS_ENABLED(CONFIG_MACH_SUNIV
))
144 * Setup 6 MHz from OSC24M (because the BROM is doing the same).
146 static void spi0_enable_clock(void)
148 uintptr_t base
= spi0_base_address();
150 /* Deassert SPI0 reset on SUN6I */
151 if (IS_ENABLED(CONFIG_MACH_SUN50I_H6
))
152 setbits_le32(CCM_H6_SPI_BGR_REG
, (1U << 16) | 0x1);
153 else if (is_sun6i_gen_spi())
154 setbits_le32(SUN6I_BUS_SOFT_RST_REG0
,
155 (1 << AHB_RESET_SPI0_SHIFT
));
157 /* Open the SPI0 gate */
158 if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6
))
159 setbits_le32(CCM_AHB_GATING0
, (1 << AHB_GATE_OFFSET_SPI0
));
161 if (IS_ENABLED(CONFIG_MACH_SUNIV
)) {
162 /* Divide by 32, clock source is AHB clock 200MHz */
163 writel(SPI0_CLK_DIV_BY_32
, base
+ SUN6I_SPI0_CCTL
);
166 writel(SPI0_CLK_DIV_BY_4
, base
+ (is_sun6i_gen_spi() ?
167 SUN6I_SPI0_CCTL
: SUN4I_SPI0_CCTL
));
168 /* 24MHz from OSC24M */
169 writel((1 << 31), CCM_SPI0_CLK
);
172 if (is_sun6i_gen_spi()) {
173 /* Enable SPI in the master mode and do a soft reset */
174 setbits_le32(base
+ SUN6I_SPI0_GCR
, SUN6I_CTL_MASTER
|
175 SUN6I_CTL_ENABLE
| SUN6I_CTL_SRST
);
176 /* Wait for completion */
177 while (readl(base
+ SUN6I_SPI0_GCR
) & SUN6I_CTL_SRST
)
180 /* Enable SPI in the master mode and reset FIFO */
181 setbits_le32(base
+ SUN4I_SPI0_CTL
, SUN4I_CTL_MASTER
|
188 static void spi0_disable_clock(void)
190 uintptr_t base
= spi0_base_address();
192 /* Disable the SPI0 controller */
193 if (is_sun6i_gen_spi())
194 clrbits_le32(base
+ SUN6I_SPI0_GCR
, SUN6I_CTL_MASTER
|
197 clrbits_le32(base
+ SUN4I_SPI0_CTL
, SUN4I_CTL_MASTER
|
200 /* Disable the SPI0 clock */
201 if (!IS_ENABLED(CONFIG_MACH_SUNIV
))
202 writel(0, CCM_SPI0_CLK
);
204 /* Close the SPI0 gate */
205 if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6
))
206 clrbits_le32(CCM_AHB_GATING0
, (1 << AHB_GATE_OFFSET_SPI0
));
208 /* Assert SPI0 reset on SUN6I */
209 if (IS_ENABLED(CONFIG_MACH_SUN50I_H6
))
210 clrbits_le32(CCM_H6_SPI_BGR_REG
, (1U << 16) | 0x1);
211 else if (is_sun6i_gen_spi())
212 clrbits_le32(SUN6I_BUS_SOFT_RST_REG0
,
213 (1 << AHB_RESET_SPI0_SHIFT
));
216 static void spi0_init(void)
218 unsigned int pin_function
= SUNXI_GPC_SPI0
;
220 if (IS_ENABLED(CONFIG_MACH_SUN50I
) ||
221 IS_ENABLED(CONFIG_MACH_SUN50I_H6
))
222 pin_function
= SUN50I_GPC_SPI0
;
223 else if (IS_ENABLED(CONFIG_MACH_SUNIV
))
224 pin_function
= SUNIV_GPC_SPI0
;
226 spi0_pinmux_setup(pin_function
);
230 static void spi0_deinit(void)
232 /* New SoCs can disable pins, older could only set them as input */
233 unsigned int pin_function
= SUNXI_GPIO_INPUT
;
235 if (is_sun6i_gen_spi())
236 pin_function
= SUNXI_GPIO_DISABLE
;
238 spi0_disable_clock();
239 spi0_pinmux_setup(pin_function
);
242 /*****************************************************************************/
244 #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
246 static void sunxi_spi0_read_data(u8
*buf
, u32 addr
, u32 bufsize
,
248 ulong spi_ctl_xch_bitmask
,
256 writel(4 + bufsize
, spi_bc_reg
); /* Burst counter (total bytes) */
257 writel(4, spi_tc_reg
); /* Transfer counter (bytes to send) */
259 writel(4, spi_bcc_reg
); /* SUN6I also needs this */
261 /* Send the Read Data Bytes (03h) command header */
262 writeb(0x03, spi_tx_reg
);
263 writeb((u8
)(addr
>> 16), spi_tx_reg
);
264 writeb((u8
)(addr
>> 8), spi_tx_reg
);
265 writeb((u8
)(addr
), spi_tx_reg
);
267 /* Start the data transfer */
268 setbits_le32(spi_ctl_reg
, spi_ctl_xch_bitmask
);
270 /* Wait until everything is received in the RX FIFO */
271 while ((readl(spi_fifo_reg
) & 0x7F) < 4 + bufsize
)
278 while (bufsize
-- > 0)
279 *buf
++ = readb(spi_rx_reg
);
281 /* tSHSL time is up to 100 ns in various SPI flash datasheets */
285 static void spi0_read_data(void *buf
, u32 addr
, u32 len
)
289 uintptr_t base
= spi0_base_address();
293 if (chunk_len
> SPI_READ_MAX_SIZE
)
294 chunk_len
= SPI_READ_MAX_SIZE
;
296 if (is_sun6i_gen_spi()) {
297 sunxi_spi0_read_data(buf8
, addr
, chunk_len
,
298 base
+ SUN6I_SPI0_TCR
,
300 base
+ SUN6I_SPI0_FIFO_STA
,
301 base
+ SUN6I_SPI0_TXD
,
302 base
+ SUN6I_SPI0_RXD
,
303 base
+ SUN6I_SPI0_MBC
,
304 base
+ SUN6I_SPI0_MTC
,
305 base
+ SUN6I_SPI0_BCC
);
307 sunxi_spi0_read_data(buf8
, addr
, chunk_len
,
308 base
+ SUN4I_SPI0_CTL
,
310 base
+ SUN4I_SPI0_FIFO_STA
,
311 base
+ SUN4I_SPI0_TX
,
312 base
+ SUN4I_SPI0_RX
,
313 base
+ SUN4I_SPI0_BC
,
314 base
+ SUN4I_SPI0_TC
,
324 static ulong
spi_load_read(struct spl_load_info
*load
, ulong sector
,
325 ulong count
, void *buf
)
327 spi0_read_data(buf
, sector
, count
);
332 /*****************************************************************************/
334 static int spl_spi_load_image(struct spl_image_info
*spl_image
,
335 struct spl_boot_device
*bootdev
)
338 struct image_header
*header
;
339 header
= (struct image_header
*)(CONFIG_SYS_TEXT_BASE
);
340 uint32_t load_offset
= sunxi_get_spl_size();
342 load_offset
= max_t(uint32_t, load_offset
, CONFIG_SYS_SPI_U_BOOT_OFFS
);
346 spi0_read_data((void *)header
, load_offset
, 0x40);
348 if (IS_ENABLED(CONFIG_SPL_LOAD_FIT
) &&
349 image_get_magic(header
) == FDT_MAGIC
) {
350 struct spl_load_info load
;
352 debug("Found FIT image\n");
355 load
.filename
= NULL
;
357 load
.read
= spi_load_read
;
358 ret
= spl_load_simple_fit(spl_image
, &load
,
359 load_offset
, header
);
361 ret
= spl_parse_image_header(spl_image
, bootdev
, header
);
365 spi0_read_data((void *)spl_image
->load_addr
,
366 load_offset
, spl_image
->size
);
373 /* Use priorty 0 to override the default if it happens to be linked in */
374 SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI
, spl_spi_load_image
);