arch/arm/mach-sunxi/spl_spi_sunxi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <image.h>
   8 #include <log.h>
   9 #include <spl.h>
  10 #include <asm/arch/spl.h>
  11 #include <asm/gpio.h>
  12 #include <asm/io.h>
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <linux/libfdt.h>
  16
  17 #ifdef CONFIG_SPL_OS_BOOT
  18 #error CONFIG_SPL_OS_BOOT is not supported yet
  19 #endif
  20
  21 /*
  22  * This is a very simple U-Boot image loading implementation, trying to
  23  * replicate what the boot ROM is doing when loading the SPL. Because we
  24  * know the exact pins where the SPI Flash is connected and also know
  25  * that the Read Data Bytes (03h) command is supported, the hardware
  26  * configuration is very simple and we don't need the extra flexibility
  27  * of the SPI framework. Moreover, we rely on the default settings of
  28  * the SPI controler hardware registers and only adjust what needs to
  29  * be changed. This is good for the code size and this implementation
  30  * adds less than 400 bytes to the SPL.
  31  *
  32  * There are two variants of the SPI controller in Allwinner SoCs:
  33  * A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
  34  * Both of them are supported.
  35  *
  36  * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
  37  * supported at the moment.
  38  */
  39
  40 /*****************************************************************************/
  41 /* SUN4I variant of the SPI controller                                       */
  42 /*****************************************************************************/
  43
  44 #define SUN4I_SPI0_CCTL             0x1C
  45 #define SUN4I_SPI0_CTL              0x08
  46 #define SUN4I_SPI0_RX               0x00
  47 #define SUN4I_SPI0_TX               0x04
  48 #define SUN4I_SPI0_FIFO_STA         0x28
  49 #define SUN4I_SPI0_BC               0x20
  50 #define SUN4I_SPI0_TC               0x24
  51
  52 #define SUN4I_CTL_ENABLE            BIT(0)
  53 #define SUN4I_CTL_MASTER            BIT(1)
  54 #define SUN4I_CTL_TF_RST            BIT(8)
  55 #define SUN4I_CTL_RF_RST            BIT(9)
  56 #define SUN4I_CTL_XCH               BIT(10)
  57
  58 /*****************************************************************************/
  59 /* SUN6I variant of the SPI controller                                       */
  60 /*****************************************************************************/
  61
  62 #define SUN6I_SPI0_CCTL             0x24
  63 #define SUN6I_SPI0_GCR              0x04
  64 #define SUN6I_SPI0_TCR              0x08
  65 #define SUN6I_SPI0_FIFO_STA         0x1C
  66 #define SUN6I_SPI0_MBC              0x30
  67 #define SUN6I_SPI0_MTC              0x34
  68 #define SUN6I_SPI0_BCC              0x38
  69 #define SUN6I_SPI0_TXD              0x200
  70 #define SUN6I_SPI0_RXD              0x300
  71
  72 #define SUN6I_CTL_ENABLE            BIT(0)
  73 #define SUN6I_CTL_MASTER            BIT(1)
  74 #define SUN6I_CTL_SRST              BIT(31)
  75 #define SUN6I_TCR_XCH               BIT(31)
  76
  77 /*****************************************************************************/
  78
  79 #define CCM_AHB_GATING0             (0x01C20000 + 0x60)
  80 #define CCM_H6_SPI_BGR_REG          (0x03001000 + 0x96c)
  81 #ifdef CONFIG_SUN50I_GEN_H6
  82 #define CCM_SPI0_CLK                (0x03001000 + 0x940)
  83 #else
  84 #define CCM_SPI0_CLK                (0x01C20000 + 0xA0)
  85 #endif
  86 #define SUN6I_BUS_SOFT_RST_REG0     (0x01C20000 + 0x2C0)
  87
  88 #define AHB_RESET_SPI0_SHIFT        20
  89 #define AHB_GATE_OFFSET_SPI0        20
  90
  91 #define SPI0_CLK_DIV_BY_2           0x1000
  92 #define SPI0_CLK_DIV_BY_4           0x1001
  93 #define SPI0_CLK_DIV_BY_32          0x100f
  94
  95 /*****************************************************************************/
  96
  97 /*
  98  * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
  99  * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
 100  * The H6 uses PC0, PC2, PC3, PC5, the H616 PC0, PC2, PC3, PC4.
 101  */
 102 static void spi0_pinmux_setup(unsigned int pin_function)
 103 {
 104         /* All chips use PC0 and PC2. */
 105         sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
 106         sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
 107
 108         /* All chips except H6 and H616 use PC1. */
 109         if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6))
 110                 sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
 111
 112         if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 113                 sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
 114         if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
 115                 sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function);
 116
 117         /* Older generations use PC23 for CS, newer ones use PC3. */
 118         if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
 119             IS_ENABLED(CONFIG_MACH_SUN8I_R40))
 120                 sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
 121         else
 122                 sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
 123 }
 124
 125 static bool is_sun6i_gen_spi(void)
 126 {
 127         return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
 128                IS_ENABLED(CONFIG_SUN50I_GEN_H6);
 129 }
 130
 131 static uintptr_t spi0_base_address(void)
 132 {
 133         if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
 134                 return 0x01C05000;
 135
 136         if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
 137                 return 0x05010000;
 138
 139         if (!is_sun6i_gen_spi() ||
 140             IS_ENABLED(CONFIG_MACH_SUNIV))
 141                 return 0x01C05000;
 142
 143         return 0x01C68000;
 144 }
 145
 146 /*
 147  * Setup 6 MHz from OSC24M (because the BROM is doing the same).
 148  */
 149 static void spi0_enable_clock(void)
 150 {
 151         uintptr_t base = spi0_base_address();
 152
 153         /* Deassert SPI0 reset on SUN6I */
 154         if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
 155                 setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
 156         else if (is_sun6i_gen_spi())
 157                 setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
 158                              (1 << AHB_RESET_SPI0_SHIFT));
 159
 160         /* Open the SPI0 gate */
 161         if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6))
 162                 setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
 163
 164         if (IS_ENABLED(CONFIG_MACH_SUNIV)) {
 165                 /* Divide by 32, clock source is AHB clock 200MHz */
 166                 writel(SPI0_CLK_DIV_BY_32, base + SUN6I_SPI0_CCTL);
 167         } else {
 168                 /* Divide by 4 */
 169                 writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
 170                                           SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
 171                 /* 24MHz from OSC24M */
 172                 writel((1 << 31), CCM_SPI0_CLK);
 173         }
 174
 175         if (is_sun6i_gen_spi()) {
 176                 /* Enable SPI in the master mode and do a soft reset */
 177                 setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
 178                              SUN6I_CTL_ENABLE | SUN6I_CTL_SRST);
 179                 /* Wait for completion */
 180                 while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
 181                         ;
 182         } else {
 183                 /* Enable SPI in the master mode and reset FIFO */
 184                 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
 185                                                     SUN4I_CTL_ENABLE |
 186                                                     SUN4I_CTL_TF_RST |
 187                                                     SUN4I_CTL_RF_RST);
 188         }
 189 }
 190
 191 static void spi0_disable_clock(void)
 192 {
 193         uintptr_t base = spi0_base_address();
 194
 195         /* Disable the SPI0 controller */
 196         if (is_sun6i_gen_spi())
 197                 clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
 198                                              SUN6I_CTL_ENABLE);
 199         else
 200                 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
 201                                              SUN4I_CTL_ENABLE);
 202
 203         /* Disable the SPI0 clock */
 204         if (!IS_ENABLED(CONFIG_MACH_SUNIV))
 205                 writel(0, CCM_SPI0_CLK);
 206
 207         /* Close the SPI0 gate */
 208         if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6))
 209                 clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
 210
 211         /* Assert SPI0 reset on SUN6I */
 212         if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
 213                 clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
 214         else if (is_sun6i_gen_spi())
 215                 clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
 216                              (1 << AHB_RESET_SPI0_SHIFT));
 217 }
 218
 219 static void spi0_init(void)
 220 {
 221         unsigned int pin_function = SUNXI_GPC_SPI0;
 222
 223         if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
 224             IS_ENABLED(CONFIG_SUN50I_GEN_H6))
 225                 pin_function = SUN50I_GPC_SPI0;
 226         else if (IS_ENABLED(CONFIG_MACH_SUNIV))
 227                 pin_function = SUNIV_GPC_SPI0;
 228
 229         spi0_pinmux_setup(pin_function);
 230         spi0_enable_clock();
 231 }
 232
 233 static void spi0_deinit(void)
 234 {
 235         /* New SoCs can disable pins, older could only set them as input */
 236         unsigned int pin_function = SUNXI_GPIO_INPUT;
 237
 238         if (is_sun6i_gen_spi())
 239                 pin_function = SUNXI_GPIO_DISABLE;
 240
 241         spi0_disable_clock();
 242         spi0_pinmux_setup(pin_function);
 243 }
 244
 245 /*****************************************************************************/
 246
 247 #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
 248
 249 static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
 250                                  ulong spi_ctl_reg,
 251                                  ulong spi_ctl_xch_bitmask,
 252                                  ulong spi_fifo_reg,
 253                                  ulong spi_tx_reg,
 254                                  ulong spi_rx_reg,
 255                                  ulong spi_bc_reg,
 256                                  ulong spi_tc_reg,
 257                                  ulong spi_bcc_reg)
 258 {
 259         writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
 260         writel(4, spi_tc_reg);           /* Transfer counter (bytes to send) */
 261         if (spi_bcc_reg)
 262                 writel(4, spi_bcc_reg);  /* SUN6I also needs this */
 263
 264         /* Send the Read Data Bytes (03h) command header */
 265         writeb(0x03, spi_tx_reg);
 266         writeb((u8)(addr >> 16), spi_tx_reg);
 267         writeb((u8)(addr >> 8), spi_tx_reg);
 268         writeb((u8)(addr), spi_tx_reg);
 269
 270         /* Start the data transfer */
 271         setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);
 272
 273         /* Wait until everything is received in the RX FIFO */
 274         while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize)
 275                 ;
 276
 277         /* Skip 4 bytes */
 278         readl(spi_rx_reg);
 279
 280         /* Read the data */
 281         while (bufsize-- > 0)
 282                 *buf++ = readb(spi_rx_reg);
 283
 284         /* tSHSL time is up to 100 ns in various SPI flash datasheets */
 285         udelay(1);
 286 }
 287
 288 static void spi0_read_data(void *buf, u32 addr, u32 len)
 289 {
 290         u8 *buf8 = buf;
 291         u32 chunk_len;
 292         uintptr_t base = spi0_base_address();
 293
 294         while (len > 0) {
 295                 chunk_len = len;
 296                 if (chunk_len > SPI_READ_MAX_SIZE)
 297                         chunk_len = SPI_READ_MAX_SIZE;
 298
 299                 if (is_sun6i_gen_spi()) {
 300                         sunxi_spi0_read_data(buf8, addr, chunk_len,
 301                                              base + SUN6I_SPI0_TCR,
 302                                              SUN6I_TCR_XCH,
 303                                              base + SUN6I_SPI0_FIFO_STA,
 304                                              base + SUN6I_SPI0_TXD,
 305                                              base + SUN6I_SPI0_RXD,
 306                                              base + SUN6I_SPI0_MBC,
 307                                              base + SUN6I_SPI0_MTC,
 308                                              base + SUN6I_SPI0_BCC);
 309                 } else {
 310                         sunxi_spi0_read_data(buf8, addr, chunk_len,
 311                                              base + SUN4I_SPI0_CTL,
 312                                              SUN4I_CTL_XCH,
 313                                              base + SUN4I_SPI0_FIFO_STA,
 314                                              base + SUN4I_SPI0_TX,
 315                                              base + SUN4I_SPI0_RX,
 316                                              base + SUN4I_SPI0_BC,
 317                                              base + SUN4I_SPI0_TC,
 318                                              0);
 319                 }
 320
 321                 len  -= chunk_len;
 322                 buf8 += chunk_len;
 323                 addr += chunk_len;
 324         }
 325 }
 326
 327 static ulong spi_load_read(struct spl_load_info *load, ulong sector,
 328                            ulong count, void *buf)
 329 {
 330         spi0_read_data(buf, sector, count);
 331
 332         return count;
 333 }
 334
 335 /*****************************************************************************/
 336
 337 static int spl_spi_load_image(struct spl_image_info *spl_image,
 338                               struct spl_boot_device *bootdev)
 339 {
 340         int ret = 0;
 341         struct legacy_img_hdr *header;
 342         uint32_t load_offset = sunxi_get_spl_size();
 343
 344         header = (struct legacy_img_hdr *)CONFIG_SYS_TEXT_BASE;
 345         load_offset = max_t(uint32_t, load_offset, CONFIG_SYS_SPI_U_BOOT_OFFS);
 346
 347         spi0_init();
 348
 349         spi0_read_data((void *)header, load_offset, 0x40);
 350
 351         if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
 352                 image_get_magic(header) == FDT_MAGIC) {
 353                 struct spl_load_info load;
 354
 355                 debug("Found FIT image\n");
 356                 load.dev = NULL;
 357                 load.priv = NULL;
 358                 load.filename = NULL;
 359                 load.bl_len = 1;
 360                 load.read = spi_load_read;
 361                 ret = spl_load_simple_fit(spl_image, &load,
 362                                           load_offset, header);
 363         } else {
 364                 ret = spl_parse_image_header(spl_image, bootdev, header);
 365                 if (ret)
 366                         return ret;
 367
 368                 spi0_read_data((void *)spl_image->load_addr,
 369                                load_offset, spl_image->size);
 370         }
 371
 372         spi0_deinit();
 373
 374         return ret;
 375 }
 376 /* Use priorty 0 to override the default if it happens to be linked in */
 377 SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image);