arch/arm/mach-sunxi/spl_spi_sunxi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <image.h>
   8 #include <log.h>
   9 #include <spl.h>
  10 #include <asm/gpio.h>
  11 #include <asm/io.h>
  12 #include <linux/libfdt.h>
  13
  14 #ifdef CONFIG_SPL_OS_BOOT
  15 #error CONFIG_SPL_OS_BOOT is not supported yet
  16 #endif
  17
  18 /*
  19  * This is a very simple U-Boot image loading implementation, trying to
  20  * replicate what the boot ROM is doing when loading the SPL. Because we
  21  * know the exact pins where the SPI Flash is connected and also know
  22  * that the Read Data Bytes (03h) command is supported, the hardware
  23  * configuration is very simple and we don't need the extra flexibility
  24  * of the SPI framework. Moreover, we rely on the default settings of
  25  * the SPI controler hardware registers and only adjust what needs to
  26  * be changed. This is good for the code size and this implementation
  27  * adds less than 400 bytes to the SPL.
  28  *
  29  * There are two variants of the SPI controller in Allwinner SoCs:
  30  * A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
  31  * Both of them are supported.
  32  *
  33  * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
  34  * supported at the moment.
  35  */
  36
  37 /*****************************************************************************/
  38 /* SUN4I variant of the SPI controller                                       */
  39 /*****************************************************************************/
  40
  41 #define SUN4I_SPI0_CCTL             0x1C
  42 #define SUN4I_SPI0_CTL              0x08
  43 #define SUN4I_SPI0_RX               0x00
  44 #define SUN4I_SPI0_TX               0x04
  45 #define SUN4I_SPI0_FIFO_STA         0x28
  46 #define SUN4I_SPI0_BC               0x20
  47 #define SUN4I_SPI0_TC               0x24
  48
  49 #define SUN4I_CTL_ENABLE            BIT(0)
  50 #define SUN4I_CTL_MASTER            BIT(1)
  51 #define SUN4I_CTL_TF_RST            BIT(8)
  52 #define SUN4I_CTL_RF_RST            BIT(9)
  53 #define SUN4I_CTL_XCH               BIT(10)
  54
  55 /*****************************************************************************/
  56 /* SUN6I variant of the SPI controller                                       */
  57 /*****************************************************************************/
  58
  59 #define SUN6I_SPI0_CCTL             0x24
  60 #define SUN6I_SPI0_GCR              0x04
  61 #define SUN6I_SPI0_TCR              0x08
  62 #define SUN6I_SPI0_FIFO_STA         0x1C
  63 #define SUN6I_SPI0_MBC              0x30
  64 #define SUN6I_SPI0_MTC              0x34
  65 #define SUN6I_SPI0_BCC              0x38
  66 #define SUN6I_SPI0_TXD              0x200
  67 #define SUN6I_SPI0_RXD              0x300
  68
  69 #define SUN6I_CTL_ENABLE            BIT(0)
  70 #define SUN6I_CTL_MASTER            BIT(1)
  71 #define SUN6I_CTL_SRST              BIT(31)
  72 #define SUN6I_TCR_XCH               BIT(31)
  73
  74 /*****************************************************************************/
  75
  76 #define CCM_AHB_GATING0             (0x01C20000 + 0x60)
  77 #define CCM_H6_SPI_BGR_REG          (0x03001000 + 0x96c)
  78 #ifdef CONFIG_MACH_SUN50I_H6
  79 #define CCM_SPI0_CLK                (0x03001000 + 0x940)
  80 #else
  81 #define CCM_SPI0_CLK                (0x01C20000 + 0xA0)
  82 #endif
  83 #define SUN6I_BUS_SOFT_RST_REG0     (0x01C20000 + 0x2C0)
  84
  85 #define AHB_RESET_SPI0_SHIFT        20
  86 #define AHB_GATE_OFFSET_SPI0        20
  87
  88 #define SPI0_CLK_DIV_BY_2           0x1000
  89 #define SPI0_CLK_DIV_BY_4           0x1001
  90
  91 /*****************************************************************************/
  92
  93 /*
  94  * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
  95  * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
  96  * The H6 uses PC0, PC2, PC3, PC5.
  97  */
  98 static void spi0_pinmux_setup(unsigned int pin_function)
  99 {
 100         /* All chips use PC0 and PC2. */
 101         sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
 102         sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
 103
 104         /* All chips except H6 use PC1, and only H6 uses PC5. */
 105         if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 106                 sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
 107         else
 108                 sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
 109
 110         /* Older generations use PC23 for CS, newer ones use PC3. */
 111         if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
 112             IS_ENABLED(CONFIG_MACH_SUN8I_R40))
 113                 sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
 114         else
 115                 sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
 116 }
 117
 118 static bool is_sun6i_gen_spi(void)
 119 {
 120         return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
 121                IS_ENABLED(CONFIG_MACH_SUN50I_H6);
 122 }
 123
 124 static uintptr_t spi0_base_address(void)
 125 {
 126         if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
 127                 return 0x01C05000;
 128
 129         if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 130                 return 0x05010000;
 131
 132         if (!is_sun6i_gen_spi())
 133                 return 0x01C05000;
 134
 135         return 0x01C68000;
 136 }
 137
 138 /*
 139  * Setup 6 MHz from OSC24M (because the BROM is doing the same).
 140  */
 141 static void spi0_enable_clock(void)
 142 {
 143         uintptr_t base = spi0_base_address();
 144
 145         /* Deassert SPI0 reset on SUN6I */
 146         if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 147                 setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
 148         else if (is_sun6i_gen_spi())
 149                 setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
 150                              (1 << AHB_RESET_SPI0_SHIFT));
 151
 152         /* Open the SPI0 gate */
 153         if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 154                 setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
 155
 156         /* Divide by 4 */
 157         writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
 158                                   SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
 159         /* 24MHz from OSC24M */
 160         writel((1 << 31), CCM_SPI0_CLK);
 161
 162         if (is_sun6i_gen_spi()) {
 163                 /* Enable SPI in the master mode and do a soft reset */
 164                 setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
 165                              SUN6I_CTL_ENABLE | SUN6I_CTL_SRST);
 166                 /* Wait for completion */
 167                 while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
 168                         ;
 169         } else {
 170                 /* Enable SPI in the master mode and reset FIFO */
 171                 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
 172                                                     SUN4I_CTL_ENABLE |
 173                                                     SUN4I_CTL_TF_RST |
 174                                                     SUN4I_CTL_RF_RST);
 175         }
 176 }
 177
 178 static void spi0_disable_clock(void)
 179 {
 180         uintptr_t base = spi0_base_address();
 181
 182         /* Disable the SPI0 controller */
 183         if (is_sun6i_gen_spi())
 184                 clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
 185                                              SUN6I_CTL_ENABLE);
 186         else
 187                 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
 188                                              SUN4I_CTL_ENABLE);
 189
 190         /* Disable the SPI0 clock */
 191         writel(0, CCM_SPI0_CLK);
 192
 193         /* Close the SPI0 gate */
 194         if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 195                 clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
 196
 197         /* Assert SPI0 reset on SUN6I */
 198         if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 199                 clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
 200         else if (is_sun6i_gen_spi())
 201                 clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
 202                              (1 << AHB_RESET_SPI0_SHIFT));
 203 }
 204
 205 static void spi0_init(void)
 206 {
 207         unsigned int pin_function = SUNXI_GPC_SPI0;
 208
 209         if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
 210             IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 211                 pin_function = SUN50I_GPC_SPI0;
 212
 213         spi0_pinmux_setup(pin_function);
 214         spi0_enable_clock();
 215 }
 216
 217 static void spi0_deinit(void)
 218 {
 219         /* New SoCs can disable pins, older could only set them as input */
 220         unsigned int pin_function = SUNXI_GPIO_INPUT;
 221
 222         if (is_sun6i_gen_spi())
 223                 pin_function = SUNXI_GPIO_DISABLE;
 224
 225         spi0_disable_clock();
 226         spi0_pinmux_setup(pin_function);
 227 }
 228
 229 /*****************************************************************************/
 230
 231 #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
 232
 233 static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
 234                                  ulong spi_ctl_reg,
 235                                  ulong spi_ctl_xch_bitmask,
 236                                  ulong spi_fifo_reg,
 237                                  ulong spi_tx_reg,
 238                                  ulong spi_rx_reg,
 239                                  ulong spi_bc_reg,
 240                                  ulong spi_tc_reg,
 241                                  ulong spi_bcc_reg)
 242 {
 243         writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
 244         writel(4, spi_tc_reg);           /* Transfer counter (bytes to send) */
 245         if (spi_bcc_reg)
 246                 writel(4, spi_bcc_reg);  /* SUN6I also needs this */
 247
 248         /* Send the Read Data Bytes (03h) command header */
 249         writeb(0x03, spi_tx_reg);
 250         writeb((u8)(addr >> 16), spi_tx_reg);
 251         writeb((u8)(addr >> 8), spi_tx_reg);
 252         writeb((u8)(addr), spi_tx_reg);
 253
 254         /* Start the data transfer */
 255         setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);
 256
 257         /* Wait until everything is received in the RX FIFO */
 258         while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize)
 259                 ;
 260
 261         /* Skip 4 bytes */
 262         readl(spi_rx_reg);
 263
 264         /* Read the data */
 265         while (bufsize-- > 0)
 266                 *buf++ = readb(spi_rx_reg);
 267
 268         /* tSHSL time is up to 100 ns in various SPI flash datasheets */
 269         udelay(1);
 270 }
 271
 272 static void spi0_read_data(void *buf, u32 addr, u32 len)
 273 {
 274         u8 *buf8 = buf;
 275         u32 chunk_len;
 276         uintptr_t base = spi0_base_address();
 277
 278         while (len > 0) {
 279                 chunk_len = len;
 280                 if (chunk_len > SPI_READ_MAX_SIZE)
 281                         chunk_len = SPI_READ_MAX_SIZE;
 282
 283                 if (is_sun6i_gen_spi()) {
 284                         sunxi_spi0_read_data(buf8, addr, chunk_len,
 285                                              base + SUN6I_SPI0_TCR,
 286                                              SUN6I_TCR_XCH,
 287                                              base + SUN6I_SPI0_FIFO_STA,
 288                                              base + SUN6I_SPI0_TXD,
 289                                              base + SUN6I_SPI0_RXD,
 290                                              base + SUN6I_SPI0_MBC,
 291                                              base + SUN6I_SPI0_MTC,
 292                                              base + SUN6I_SPI0_BCC);
 293                 } else {
 294                         sunxi_spi0_read_data(buf8, addr, chunk_len,
 295                                              base + SUN4I_SPI0_CTL,
 296                                              SUN4I_CTL_XCH,
 297                                              base + SUN4I_SPI0_FIFO_STA,
 298                                              base + SUN4I_SPI0_TX,
 299                                              base + SUN4I_SPI0_RX,
 300                                              base + SUN4I_SPI0_BC,
 301                                              base + SUN4I_SPI0_TC,
 302                                              0);
 303                 }
 304
 305                 len  -= chunk_len;
 306                 buf8 += chunk_len;
 307                 addr += chunk_len;
 308         }
 309 }
 310
 311 static ulong spi_load_read(struct spl_load_info *load, ulong sector,
 312                            ulong count, void *buf)
 313 {
 314         spi0_read_data(buf, sector, count);
 315
 316         return count;
 317 }
 318
 319 /*****************************************************************************/
 320
 321 static int spl_spi_load_image(struct spl_image_info *spl_image,
 322                               struct spl_boot_device *bootdev)
 323 {
 324         int ret = 0;
 325         struct image_header *header;
 326         header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
 327
 328         spi0_init();
 329
 330         spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40);
 331
 332         if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
 333                 image_get_magic(header) == FDT_MAGIC) {
 334                 struct spl_load_info load;
 335
 336                 debug("Found FIT image\n");
 337                 load.dev = NULL;
 338                 load.priv = NULL;
 339                 load.filename = NULL;
 340                 load.bl_len = 1;
 341                 load.read = spi_load_read;
 342                 ret = spl_load_simple_fit(spl_image, &load,
 343                                           CONFIG_SYS_SPI_U_BOOT_OFFS, header);
 344         } else {
 345                 ret = spl_parse_image_header(spl_image, header);
 346                 if (ret)
 347                         return ret;
 348
 349                 spi0_read_data((void *)spl_image->load_addr,
 350                                CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size);
 351         }
 352
 353         spi0_deinit();
 354
 355         return ret;
 356 }
 357 /* Use priorty 0 to override the default if it happens to be linked in */
 358 SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image);