arch/arm/mach-tegra/board.c

   1 /*
   2  *  (C) Copyright 2010-2015
   3  *  NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <spl.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/funcmux.h>
  13 #include <asm/arch/mc.h>
  14 #include <asm/arch/tegra.h>
  15 #include <asm/arch-tegra/ap.h>
  16 #include <asm/arch-tegra/board.h>
  17 #include <asm/arch-tegra/pmc.h>
  18 #include <asm/arch-tegra/sys_proto.h>
  19 #include <asm/arch-tegra/warmboot.h>
  20
  21 void save_boot_params_ret(void);
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 enum {
  26         /* UARTs which we can enable */
  27         UARTA   = 1 << 0,
  28         UARTB   = 1 << 1,
  29         UARTC   = 1 << 2,
  30         UARTD   = 1 << 3,
  31         UARTE   = 1 << 4,
  32         UART_COUNT = 5,
  33 };
  34
  35 static bool from_spl __attribute__ ((section(".data")));
  36
  37 #ifndef CONFIG_SPL_BUILD
  38 void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
  39 {
  40         from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
  41         save_boot_params_ret();
  42 }
  43 #endif
  44
  45 bool spl_was_boot_source(void)
  46 {
  47         return from_spl;
  48 }
  49
  50 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  51 #if !defined(CONFIG_TEGRA124)
  52 #error tegra_cpu_is_non_secure has only been validated on Tegra124
  53 #endif
  54 bool tegra_cpu_is_non_secure(void)
  55 {
  56         /*
  57          * This register reads 0xffffffff in non-secure mode. This register
  58          * only implements bits 31:20, so the lower bits will always read 0 in
  59          * secure mode. Thus, the lower bits are an indicator for secure vs.
  60          * non-secure mode.
  61          */
  62         struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  63         uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
  64         return (mc_s_cfg0 & 1) == 1;
  65 }
  66 #endif
  67
  68 /* Read the RAM size directly from the memory controller */
  69 unsigned int query_sdram_size(void)
  70 {
  71         struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  72         u32 emem_cfg, size_bytes;
  73
  74         emem_cfg = readl(&mc->mc_emem_cfg);
  75 #if defined(CONFIG_TEGRA20)
  76         debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
  77         size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
  78 #else
  79         debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
  80         /*
  81          * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
  82          * and will wrap. Clip the reported size to the maximum that a 32-bit
  83          * variable can represent (rounded to a page).
  84          */
  85         if (emem_cfg >= 4096) {
  86                 size_bytes = U32_MAX & ~(0x1000 - 1);
  87         } else {
  88                 /* RAM size EMC is programmed to. */
  89                 size_bytes = emem_cfg * 1024 * 1024;
  90                 /*
  91                  * If all RAM fits within 32-bits, it can be accessed without
  92                  * LPAE, so go test the RAM size. Otherwise, we can't access
  93                  * all the RAM, and get_ram_size() would get confused, so
  94                  * avoid using it. There's no reason we should need this
  95                  * validation step anyway.
  96                  */
  97                 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
  98                         size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
  99                                                   size_bytes);
 100         }
 101 #endif
 102
 103 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
 104         /* External memory limited to 2047 MB due to IROM/HI-VEC */
 105         if (size_bytes == SZ_2G)
 106                 size_bytes -= SZ_1M;
 107 #endif
 108
 109         return size_bytes;
 110 }
 111
 112 int dram_init(void)
 113 {
 114         /* We do not initialise DRAM here. We just query the size */
 115         gd->ram_size = query_sdram_size();
 116         return 0;
 117 }
 118
 119 static int uart_configs[] = {
 120 #if defined(CONFIG_TEGRA20)
 121  #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
 122         FUNCMUX_UART1_UAA_UAB,
 123  #elif defined(CONFIG_TEGRA_UARTA_GPU)
 124         FUNCMUX_UART1_GPU,
 125  #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
 126         FUNCMUX_UART1_SDIO1,
 127  #else
 128         FUNCMUX_UART1_IRRX_IRTX,
 129 #endif
 130         FUNCMUX_UART2_UAD,
 131         -1,
 132         FUNCMUX_UART4_GMC,
 133         -1,
 134 #elif defined(CONFIG_TEGRA30)
 135         FUNCMUX_UART1_ULPI,     /* UARTA */
 136         -1,
 137         -1,
 138         -1,
 139         -1,
 140 #elif defined(CONFIG_TEGRA114)
 141         -1,
 142         -1,
 143         -1,
 144         FUNCMUX_UART4_GMI,      /* UARTD */
 145         -1,
 146 #elif defined(CONFIG_TEGRA124)
 147         FUNCMUX_UART1_KBC,      /* UARTA */
 148         -1,
 149         -1,
 150         FUNCMUX_UART4_GPIO,     /* UARTD */
 151         -1,
 152 #else   /* Tegra210 */
 153         FUNCMUX_UART1_UART1,    /* UARTA */
 154         -1,
 155         -1,
 156         FUNCMUX_UART4_UART4,    /* UARTD */
 157         -1,
 158 #endif
 159 };
 160
 161 /**
 162  * Set up the specified uarts
 163  *
 164  * @param uarts_ids     Mask containing UARTs to init (UARTx)
 165  */
 166 static void setup_uarts(int uart_ids)
 167 {
 168         static enum periph_id id_for_uart[] = {
 169                 PERIPH_ID_UART1,
 170                 PERIPH_ID_UART2,
 171                 PERIPH_ID_UART3,
 172                 PERIPH_ID_UART4,
 173                 PERIPH_ID_UART5,
 174         };
 175         size_t i;
 176
 177         for (i = 0; i < UART_COUNT; i++) {
 178                 if (uart_ids & (1 << i)) {
 179                         enum periph_id id = id_for_uart[i];
 180
 181                         funcmux_select(id, uart_configs[i]);
 182                         clock_ll_start_uart(id);
 183                 }
 184         }
 185 }
 186
 187 void board_init_uart_f(void)
 188 {
 189         int uart_ids = 0;       /* bit mask of which UART ids to enable */
 190
 191 #ifdef CONFIG_TEGRA_ENABLE_UARTA
 192         uart_ids |= UARTA;
 193 #endif
 194 #ifdef CONFIG_TEGRA_ENABLE_UARTB
 195         uart_ids |= UARTB;
 196 #endif
 197 #ifdef CONFIG_TEGRA_ENABLE_UARTC
 198         uart_ids |= UARTC;
 199 #endif
 200 #ifdef CONFIG_TEGRA_ENABLE_UARTD
 201         uart_ids |= UARTD;
 202 #endif
 203 #ifdef CONFIG_TEGRA_ENABLE_UARTE
 204         uart_ids |= UARTE;
 205 #endif
 206         setup_uarts(uart_ids);
 207 }
 208
 209 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
 210 void enable_caches(void)
 211 {
 212         /* Enable D-cache. I-cache is already enabled in start.S */
 213         dcache_enable();
 214 }
 215 #endif