arch/arm/mach-tegra/pinmux-common.c

   1 /*
   2  * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
   3  * Copyright (c) 2011 The Chromium OS Authors.
   4  *
   5  * SPDX-License-Identifier: GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/pinmux.h>
  11
  12 /* return 1 if a pingrp is in range */
  13 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
  14
  15 /* return 1 if a pmux_func is in range */
  16 #define pmux_func_isvalid(func) \
  17         (((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
  18
  19 /* return 1 if a pin_pupd_is in range */
  20 #define pmux_pin_pupd_isvalid(pupd) \
  21         (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
  22
  23 /* return 1 if a pin_tristate_is in range */
  24 #define pmux_pin_tristate_isvalid(tristate) \
  25         (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
  26
  27 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
  28 /* return 1 if a pin_io_is in range */
  29 #define pmux_pin_io_isvalid(io) \
  30         (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
  31 #endif
  32
  33 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
  34 /* return 1 if a pin_lock is in range */
  35 #define pmux_pin_lock_isvalid(lock) \
  36         (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
  37 #endif
  38
  39 #ifdef TEGRA_PMX_PINS_HAVE_OD
  40 /* return 1 if a pin_od is in range */
  41 #define pmux_pin_od_isvalid(od) \
  42         (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
  43 #endif
  44
  45 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
  46 /* return 1 if a pin_ioreset_is in range */
  47 #define pmux_pin_ioreset_isvalid(ioreset) \
  48         (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
  49          ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
  50 #endif
  51
  52 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
  53 /* return 1 if a pin_rcv_sel_is in range */
  54 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
  55         (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
  56          ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
  57 #endif
  58
  59 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
  60 #define pmux_lpmd_isvalid(lpm) \
  61         (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
  62 #endif
  63
  64 #if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
  65 #define pmux_schmt_isvalid(schmt) \
  66         (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
  67 #endif
  68
  69 #if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
  70 #define pmux_hsm_isvalid(hsm) \
  71         (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
  72 #endif
  73
  74 #define _R(offset)      (u32 *)(NV_PA_APB_MISC_BASE + (offset))
  75
  76 #if defined(CONFIG_TEGRA20)
  77
  78 #define MUX_REG(grp)    _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
  79 #define MUX_SHIFT(grp)  ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
  80
  81 #define PULL_REG(grp)   _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
  82 #define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
  83
  84 #define TRI_REG(grp)    _R(0x14 + (((grp) / 32) * 4))
  85 #define TRI_SHIFT(grp)  ((grp) % 32)
  86
  87 #else
  88
  89 #define REG(pin)        _R(0x3000 + ((pin) * 4))
  90
  91 #define MUX_REG(pin)    REG(pin)
  92 #define MUX_SHIFT(pin)  0
  93
  94 #define PULL_REG(pin)   REG(pin)
  95 #define PULL_SHIFT(pin) 2
  96
  97 #define TRI_REG(pin)    REG(pin)
  98 #define TRI_SHIFT(pin)  4
  99
 100 #endif /* CONFIG_TEGRA20 */
 101
 102 #define DRV_REG(group)  _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4))
 103
 104 /*
 105  * We could force arch-tegraNN/pinmux.h to define all of these. However,
 106  * that's a lot of defines, and for now it's manageable to just put a
 107  * special case here. It's possible this decision will change with future
 108  * SoCs.
 109  */
 110 #ifdef CONFIG_TEGRA210
 111 #define IO_SHIFT        6
 112 #define LOCK_SHIFT      7
 113 #ifdef TEGRA_PMX_PINS_HAVE_HSM
 114 #define HSM_SHIFT       9
 115 #endif
 116 #define OD_SHIFT        11
 117 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
 118 #define SCHMT_SHIFT     12
 119 #endif
 120 #else
 121 #define IO_SHIFT        5
 122 #define OD_SHIFT        6
 123 #define LOCK_SHIFT      7
 124 #define IO_RESET_SHIFT  8
 125 #define RCV_SEL_SHIFT   9
 126 #endif
 127
 128 #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
 129 /* This register/field only exists on Tegra114 and later */
 130 #define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
 131 #define CLAMP_INPUTS_WHEN_TRISTATED 1
 132
 133 void pinmux_set_tristate_input_clamping(void)
 134 {
 135         u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
 136
 137         setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
 138 }
 139
 140 void pinmux_clear_tristate_input_clamping(void)
 141 {
 142         u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
 143
 144         clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
 145 }
 146 #endif
 147
 148 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
 149 {
 150         u32 *reg = MUX_REG(pin);
 151         int i, mux = -1;
 152         u32 val;
 153
 154         if (func == PMUX_FUNC_DEFAULT)
 155                 return;
 156
 157         /* Error check on pin and func */
 158         assert(pmux_pingrp_isvalid(pin));
 159         assert(pmux_func_isvalid(func));
 160
 161         if (func >= PMUX_FUNC_RSVD1) {
 162                 mux = (func - PMUX_FUNC_RSVD1) & 3;
 163         } else {
 164                 /* Search for the appropriate function */
 165                 for (i = 0; i < 4; i++) {
 166                         if (tegra_soc_pingroups[pin].funcs[i] == func) {
 167                                 mux = i;
 168                                 break;
 169                         }
 170                 }
 171         }
 172         assert(mux != -1);
 173
 174         val = readl(reg);
 175         val &= ~(3 << MUX_SHIFT(pin));
 176         val |= (mux << MUX_SHIFT(pin));
 177         writel(val, reg);
 178 }
 179
 180 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
 181 {
 182         u32 *reg = PULL_REG(pin);
 183         u32 val;
 184
 185         /* Error check on pin and pupd */
 186         assert(pmux_pingrp_isvalid(pin));
 187         assert(pmux_pin_pupd_isvalid(pupd));
 188
 189         val = readl(reg);
 190         val &= ~(3 << PULL_SHIFT(pin));
 191         val |= (pupd << PULL_SHIFT(pin));
 192         writel(val, reg);
 193 }
 194
 195 static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
 196 {
 197         u32 *reg = TRI_REG(pin);
 198         u32 val;
 199
 200         /* Error check on pin */
 201         assert(pmux_pingrp_isvalid(pin));
 202         assert(pmux_pin_tristate_isvalid(tri));
 203
 204         val = readl(reg);
 205         if (tri == PMUX_TRI_TRISTATE)
 206                 val |= (1 << TRI_SHIFT(pin));
 207         else
 208                 val &= ~(1 << TRI_SHIFT(pin));
 209         writel(val, reg);
 210 }
 211
 212 void pinmux_tristate_enable(enum pmux_pingrp pin)
 213 {
 214         pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
 215 }
 216
 217 void pinmux_tristate_disable(enum pmux_pingrp pin)
 218 {
 219         pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
 220 }
 221
 222 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 223 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
 224 {
 225         u32 *reg = REG(pin);
 226         u32 val;
 227
 228         if (io == PMUX_PIN_NONE)
 229                 return;
 230
 231         /* Error check on pin and io */
 232         assert(pmux_pingrp_isvalid(pin));
 233         assert(pmux_pin_io_isvalid(io));
 234
 235         val = readl(reg);
 236         if (io == PMUX_PIN_INPUT)
 237                 val |= (io & 1) << IO_SHIFT;
 238         else
 239                 val &= ~(1 << IO_SHIFT);
 240         writel(val, reg);
 241 }
 242 #endif
 243
 244 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
 245 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
 246 {
 247         u32 *reg = REG(pin);
 248         u32 val;
 249
 250         if (lock == PMUX_PIN_LOCK_DEFAULT)
 251                 return;
 252
 253         /* Error check on pin and lock */
 254         assert(pmux_pingrp_isvalid(pin));
 255         assert(pmux_pin_lock_isvalid(lock));
 256
 257         val = readl(reg);
 258         if (lock == PMUX_PIN_LOCK_ENABLE) {
 259                 val |= (1 << LOCK_SHIFT);
 260         } else {
 261                 if (val & (1 << LOCK_SHIFT))
 262                         printf("%s: Cannot clear LOCK bit!\n", __func__);
 263                 val &= ~(1 << LOCK_SHIFT);
 264         }
 265         writel(val, reg);
 266
 267         return;
 268 }
 269 #endif
 270
 271 #ifdef TEGRA_PMX_PINS_HAVE_OD
 272 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
 273 {
 274         u32 *reg = REG(pin);
 275         u32 val;
 276
 277         if (od == PMUX_PIN_OD_DEFAULT)
 278                 return;
 279
 280         /* Error check on pin and od */
 281         assert(pmux_pingrp_isvalid(pin));
 282         assert(pmux_pin_od_isvalid(od));
 283
 284         val = readl(reg);
 285         if (od == PMUX_PIN_OD_ENABLE)
 286                 val |= (1 << OD_SHIFT);
 287         else
 288                 val &= ~(1 << OD_SHIFT);
 289         writel(val, reg);
 290
 291         return;
 292 }
 293 #endif
 294
 295 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 296 static void pinmux_set_ioreset(enum pmux_pingrp pin,
 297                                 enum pmux_pin_ioreset ioreset)
 298 {
 299         u32 *reg = REG(pin);
 300         u32 val;
 301
 302         if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
 303                 return;
 304
 305         /* Error check on pin and ioreset */
 306         assert(pmux_pingrp_isvalid(pin));
 307         assert(pmux_pin_ioreset_isvalid(ioreset));
 308
 309         val = readl(reg);
 310         if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
 311                 val |= (1 << IO_RESET_SHIFT);
 312         else
 313                 val &= ~(1 << IO_RESET_SHIFT);
 314         writel(val, reg);
 315
 316         return;
 317 }
 318 #endif
 319
 320 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 321 static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
 322                                 enum pmux_pin_rcv_sel rcv_sel)
 323 {
 324         u32 *reg = REG(pin);
 325         u32 val;
 326
 327         if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
 328                 return;
 329
 330         /* Error check on pin and rcv_sel */
 331         assert(pmux_pingrp_isvalid(pin));
 332         assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
 333
 334         val = readl(reg);
 335         if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
 336                 val |= (1 << RCV_SEL_SHIFT);
 337         else
 338                 val &= ~(1 << RCV_SEL_SHIFT);
 339         writel(val, reg);
 340
 341         return;
 342 }
 343 #endif
 344
 345 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
 346 static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt)
 347 {
 348         u32 *reg = REG(grp);
 349         u32 val;
 350
 351         /* NONE means unspecified/do not change/use POR value */
 352         if (schmt == PMUX_SCHMT_NONE)
 353                 return;
 354
 355         /* Error check pad */
 356         assert(pmux_pingrp_isvalid(pin));
 357         assert(pmux_schmt_isvalid(schmt));
 358
 359         val = readl(reg);
 360         if (schmt == PMUX_SCHMT_ENABLE)
 361                 val |= (1 << SCHMT_SHIFT);
 362         else
 363                 val &= ~(1 << SCHMT_SHIFT);
 364         writel(val, reg);
 365
 366         return;
 367 }
 368 #endif
 369
 370 #ifdef TEGRA_PMX_PINS_HAVE_HSM
 371 static void pinmux_set_hsm(enum pmux_pingrp pin, enum pmux_hsm hsm)
 372 {
 373         u32 *reg = REG(grp);
 374         u32 val;
 375
 376         /* NONE means unspecified/do not change/use POR value */
 377         if (hsm == PMUX_HSM_NONE)
 378                 return;
 379
 380         /* Error check pad */
 381         assert(pmux_pingrp_isvalid(pin));
 382         assert(pmux_hsm_isvalid(hsm));
 383
 384         val = readl(reg);
 385         if (hsm == PMUX_HSM_ENABLE)
 386                 val |= (1 << HSM_SHIFT);
 387         else
 388                 val &= ~(1 << HSM_SHIFT);
 389         writel(val, reg);
 390
 391         return;
 392 }
 393 #endif
 394
 395 static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
 396 {
 397         enum pmux_pingrp pin = config->pingrp;
 398
 399         pinmux_set_func(pin, config->func);
 400         pinmux_set_pullupdown(pin, config->pull);
 401         pinmux_set_tristate(pin, config->tristate);
 402 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 403         pinmux_set_io(pin, config->io);
 404 #endif
 405 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
 406         pinmux_set_lock(pin, config->lock);
 407 #endif
 408 #ifdef TEGRA_PMX_PINS_HAVE_OD
 409         pinmux_set_od(pin, config->od);
 410 #endif
 411 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 412         pinmux_set_ioreset(pin, config->ioreset);
 413 #endif
 414 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 415         pinmux_set_rcv_sel(pin, config->rcv_sel);
 416 #endif
 417 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
 418         pinmux_set_schmt(pin, config->schmt);
 419 #endif
 420 #ifdef TEGRA_PMX_PINS_HAVE_HSM
 421         pinmux_set_hsm(pin, config->hsm);
 422 #endif
 423 }
 424
 425 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
 426                                 int len)
 427 {
 428         int i;
 429
 430         for (i = 0; i < len; i++)
 431                 pinmux_config_pingrp(&config[i]);
 432 }
 433
 434 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
 435
 436 #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
 437
 438 #define pmux_slw_isvalid(slw) \
 439         (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
 440
 441 #define pmux_drv_isvalid(drv) \
 442         (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
 443
 444 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
 445 #define HSM_SHIFT       2
 446 #endif
 447 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 448 #define SCHMT_SHIFT     3
 449 #endif
 450 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 451 #define LPMD_SHIFT      4
 452 #define LPMD_MASK       (3 << LPMD_SHIFT)
 453 #endif
 454 /*
 455  * Note that the following DRV* and SLW* defines are accurate for many drive
 456  * groups on many SoCs. We really need a per-group data structure to solve
 457  * this, since the fields are in different positions/sizes in different
 458  * registers (for different groups).
 459  *
 460  * On Tegra30/114/124, the DRV*_SHIFT values vary.
 461  * On Tegra30, the SLW*_SHIFT values vary.
 462  * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
 463  *   below are wide enough to cover the widest fields, and hopefully don't
 464  *   interfere with any other fields.
 465  * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
 466  *   wide enough to cover all cases, since that would cause the field to
 467  *   overlap with other fields in the narrower cases.
 468  */
 469 #define DRVDN_SHIFT     12
 470 #define DRVDN_MASK      (0x7F << DRVDN_SHIFT)
 471 #define DRVUP_SHIFT     20
 472 #define DRVUP_MASK      (0x7F << DRVUP_SHIFT)
 473 #define SLWR_SHIFT      28
 474 #define SLWR_MASK       (3 << SLWR_SHIFT)
 475 #define SLWF_SHIFT      30
 476 #define SLWF_MASK       (3 << SLWF_SHIFT)
 477
 478 static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
 479 {
 480         u32 *reg = DRV_REG(grp);
 481         u32 val;
 482
 483         /* NONE means unspecified/do not change/use POR value */
 484         if (slwf == PMUX_SLWF_NONE)
 485                 return;
 486
 487         /* Error check on pad and slwf */
 488         assert(pmux_drvgrp_isvalid(grp));
 489         assert(pmux_slw_isvalid(slwf));
 490
 491         val = readl(reg);
 492         val &= ~SLWF_MASK;
 493         val |= (slwf << SLWF_SHIFT);
 494         writel(val, reg);
 495
 496         return;
 497 }
 498
 499 static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
 500 {
 501         u32 *reg = DRV_REG(grp);
 502         u32 val;
 503
 504         /* NONE means unspecified/do not change/use POR value */
 505         if (slwr == PMUX_SLWR_NONE)
 506                 return;
 507
 508         /* Error check on pad and slwr */
 509         assert(pmux_drvgrp_isvalid(grp));
 510         assert(pmux_slw_isvalid(slwr));
 511
 512         val = readl(reg);
 513         val &= ~SLWR_MASK;
 514         val |= (slwr << SLWR_SHIFT);
 515         writel(val, reg);
 516
 517         return;
 518 }
 519
 520 static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
 521 {
 522         u32 *reg = DRV_REG(grp);
 523         u32 val;
 524
 525         /* NONE means unspecified/do not change/use POR value */
 526         if (drvup == PMUX_DRVUP_NONE)
 527                 return;
 528
 529         /* Error check on pad and drvup */
 530         assert(pmux_drvgrp_isvalid(grp));
 531         assert(pmux_drv_isvalid(drvup));
 532
 533         val = readl(reg);
 534         val &= ~DRVUP_MASK;
 535         val |= (drvup << DRVUP_SHIFT);
 536         writel(val, reg);
 537
 538         return;
 539 }
 540
 541 static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
 542 {
 543         u32 *reg = DRV_REG(grp);
 544         u32 val;
 545
 546         /* NONE means unspecified/do not change/use POR value */
 547         if (drvdn == PMUX_DRVDN_NONE)
 548                 return;
 549
 550         /* Error check on pad and drvdn */
 551         assert(pmux_drvgrp_isvalid(grp));
 552         assert(pmux_drv_isvalid(drvdn));
 553
 554         val = readl(reg);
 555         val &= ~DRVDN_MASK;
 556         val |= (drvdn << DRVDN_SHIFT);
 557         writel(val, reg);
 558
 559         return;
 560 }
 561
 562 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 563 static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
 564 {
 565         u32 *reg = DRV_REG(grp);
 566         u32 val;
 567
 568         /* NONE means unspecified/do not change/use POR value */
 569         if (lpmd == PMUX_LPMD_NONE)
 570                 return;
 571
 572         /* Error check pad and lpmd value */
 573         assert(pmux_drvgrp_isvalid(grp));
 574         assert(pmux_lpmd_isvalid(lpmd));
 575
 576         val = readl(reg);
 577         val &= ~LPMD_MASK;
 578         val |= (lpmd << LPMD_SHIFT);
 579         writel(val, reg);
 580
 581         return;
 582 }
 583 #endif
 584
 585 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 586 static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
 587 {
 588         u32 *reg = DRV_REG(grp);
 589         u32 val;
 590
 591         /* NONE means unspecified/do not change/use POR value */
 592         if (schmt == PMUX_SCHMT_NONE)
 593                 return;
 594
 595         /* Error check pad */
 596         assert(pmux_drvgrp_isvalid(grp));
 597         assert(pmux_schmt_isvalid(schmt));
 598
 599         val = readl(reg);
 600         if (schmt == PMUX_SCHMT_ENABLE)
 601                 val |= (1 << SCHMT_SHIFT);
 602         else
 603                 val &= ~(1 << SCHMT_SHIFT);
 604         writel(val, reg);
 605
 606         return;
 607 }
 608 #endif
 609
 610 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
 611 static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
 612 {
 613         u32 *reg = DRV_REG(grp);
 614         u32 val;
 615
 616         /* NONE means unspecified/do not change/use POR value */
 617         if (hsm == PMUX_HSM_NONE)
 618                 return;
 619
 620         /* Error check pad */
 621         assert(pmux_drvgrp_isvalid(grp));
 622         assert(pmux_hsm_isvalid(hsm));
 623
 624         val = readl(reg);
 625         if (hsm == PMUX_HSM_ENABLE)
 626                 val |= (1 << HSM_SHIFT);
 627         else
 628                 val &= ~(1 << HSM_SHIFT);
 629         writel(val, reg);
 630
 631         return;
 632 }
 633 #endif
 634
 635 static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
 636 {
 637         enum pmux_drvgrp grp = config->drvgrp;
 638
 639         pinmux_set_drvup_slwf(grp, config->slwf);
 640         pinmux_set_drvdn_slwr(grp, config->slwr);
 641         pinmux_set_drvup(grp, config->drvup);
 642         pinmux_set_drvdn(grp, config->drvdn);
 643 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 644         pinmux_set_lpmd(grp, config->lpmd);
 645 #endif
 646 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 647         pinmux_set_schmt(grp, config->schmt);
 648 #endif
 649 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
 650         pinmux_set_hsm(grp, config->hsm);
 651 #endif
 652 }
 653
 654 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
 655                                 int len)
 656 {
 657         int i;
 658
 659         for (i = 0; i < len; i++)
 660                 pinmux_config_drvgrp(&config[i]);
 661 }
 662 #endif /* TEGRA_PMX_HAS_DRVGRPS */