arch/arm/mach-tegra/pinmux-common.c

   1 /*
   2  * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
   3  * Copyright (c) 2011 The Chromium OS Authors.
   4  *
   5  * SPDX-License-Identifier: GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/pinmux.h>
  11
  12 /* return 1 if a pingrp is in range */
  13 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
  14
  15 /* return 1 if a pmux_func is in range */
  16 #define pmux_func_isvalid(func) \
  17         (((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
  18
  19 /* return 1 if a pin_pupd_is in range */
  20 #define pmux_pin_pupd_isvalid(pupd) \
  21         (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
  22
  23 /* return 1 if a pin_tristate_is in range */
  24 #define pmux_pin_tristate_isvalid(tristate) \
  25         (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
  26
  27 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
  28 /* return 1 if a pin_io_is in range */
  29 #define pmux_pin_io_isvalid(io) \
  30         (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
  31 #endif
  32
  33 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
  34 /* return 1 if a pin_lock is in range */
  35 #define pmux_pin_lock_isvalid(lock) \
  36         (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
  37 #endif
  38
  39 #ifdef TEGRA_PMX_PINS_HAVE_OD
  40 /* return 1 if a pin_od is in range */
  41 #define pmux_pin_od_isvalid(od) \
  42         (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
  43 #endif
  44
  45 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
  46 /* return 1 if a pin_ioreset_is in range */
  47 #define pmux_pin_ioreset_isvalid(ioreset) \
  48         (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
  49          ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
  50 #endif
  51
  52 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
  53 /* return 1 if a pin_rcv_sel_is in range */
  54 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
  55         (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
  56          ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
  57 #endif
  58
  59 #define _R(offset)      (u32 *)(NV_PA_APB_MISC_BASE + (offset))
  60
  61 #if defined(CONFIG_TEGRA20)
  62
  63 #define MUX_REG(grp)    _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
  64 #define MUX_SHIFT(grp)  ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
  65
  66 #define PULL_REG(grp)   _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
  67 #define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
  68
  69 #define TRI_REG(grp)    _R(0x14 + (((grp) / 32) * 4))
  70 #define TRI_SHIFT(grp)  ((grp) % 32)
  71
  72 #else
  73
  74 #define REG(pin)        _R(0x3000 + ((pin) * 4))
  75
  76 #define MUX_REG(pin)    REG(pin)
  77 #define MUX_SHIFT(pin)  0
  78
  79 #define PULL_REG(pin)   REG(pin)
  80 #define PULL_SHIFT(pin) 2
  81
  82 #define TRI_REG(pin)    REG(pin)
  83 #define TRI_SHIFT(pin)  4
  84
  85 #endif /* CONFIG_TEGRA20 */
  86
  87 #define DRV_REG(group)  _R(0x868 + ((group) * 4))
  88
  89 #define IO_SHIFT        5
  90 #define OD_SHIFT        6
  91 #define LOCK_SHIFT      7
  92 #define IO_RESET_SHIFT  8
  93 #define RCV_SEL_SHIFT   9
  94
  95 #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
  96 /* This register/field only exists on Tegra114 and later */
  97 #define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
  98 #define CLAMP_INPUTS_WHEN_TRISTATED 1
  99
 100 void pinmux_set_tristate_input_clamping(void)
 101 {
 102         u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
 103
 104         setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
 105 }
 106
 107 void pinmux_clear_tristate_input_clamping(void)
 108 {
 109         u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
 110
 111         clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
 112 }
 113 #endif
 114
 115 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
 116 {
 117         u32 *reg = MUX_REG(pin);
 118         int i, mux = -1;
 119         u32 val;
 120
 121         if (func == PMUX_FUNC_DEFAULT)
 122                 return;
 123
 124         /* Error check on pin and func */
 125         assert(pmux_pingrp_isvalid(pin));
 126         assert(pmux_func_isvalid(func));
 127
 128         if (func >= PMUX_FUNC_RSVD1) {
 129                 mux = (func - PMUX_FUNC_RSVD1) & 3;
 130         } else {
 131                 /* Search for the appropriate function */
 132                 for (i = 0; i < 4; i++) {
 133                         if (tegra_soc_pingroups[pin].funcs[i] == func) {
 134                                 mux = i;
 135                                 break;
 136                         }
 137                 }
 138         }
 139         assert(mux != -1);
 140
 141         val = readl(reg);
 142         val &= ~(3 << MUX_SHIFT(pin));
 143         val |= (mux << MUX_SHIFT(pin));
 144         writel(val, reg);
 145 }
 146
 147 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
 148 {
 149         u32 *reg = PULL_REG(pin);
 150         u32 val;
 151
 152         /* Error check on pin and pupd */
 153         assert(pmux_pingrp_isvalid(pin));
 154         assert(pmux_pin_pupd_isvalid(pupd));
 155
 156         val = readl(reg);
 157         val &= ~(3 << PULL_SHIFT(pin));
 158         val |= (pupd << PULL_SHIFT(pin));
 159         writel(val, reg);
 160 }
 161
 162 static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
 163 {
 164         u32 *reg = TRI_REG(pin);
 165         u32 val;
 166
 167         /* Error check on pin */
 168         assert(pmux_pingrp_isvalid(pin));
 169         assert(pmux_pin_tristate_isvalid(tri));
 170
 171         val = readl(reg);
 172         if (tri == PMUX_TRI_TRISTATE)
 173                 val |= (1 << TRI_SHIFT(pin));
 174         else
 175                 val &= ~(1 << TRI_SHIFT(pin));
 176         writel(val, reg);
 177 }
 178
 179 void pinmux_tristate_enable(enum pmux_pingrp pin)
 180 {
 181         pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
 182 }
 183
 184 void pinmux_tristate_disable(enum pmux_pingrp pin)
 185 {
 186         pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
 187 }
 188
 189 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 190 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
 191 {
 192         u32 *reg = REG(pin);
 193         u32 val;
 194
 195         if (io == PMUX_PIN_NONE)
 196                 return;
 197
 198         /* Error check on pin and io */
 199         assert(pmux_pingrp_isvalid(pin));
 200         assert(pmux_pin_io_isvalid(io));
 201
 202         val = readl(reg);
 203         if (io == PMUX_PIN_INPUT)
 204                 val |= (io & 1) << IO_SHIFT;
 205         else
 206                 val &= ~(1 << IO_SHIFT);
 207         writel(val, reg);
 208 }
 209 #endif
 210
 211 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
 212 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
 213 {
 214         u32 *reg = REG(pin);
 215         u32 val;
 216
 217         if (lock == PMUX_PIN_LOCK_DEFAULT)
 218                 return;
 219
 220         /* Error check on pin and lock */
 221         assert(pmux_pingrp_isvalid(pin));
 222         assert(pmux_pin_lock_isvalid(lock));
 223
 224         val = readl(reg);
 225         if (lock == PMUX_PIN_LOCK_ENABLE) {
 226                 val |= (1 << LOCK_SHIFT);
 227         } else {
 228                 if (val & (1 << LOCK_SHIFT))
 229                         printf("%s: Cannot clear LOCK bit!\n", __func__);
 230                 val &= ~(1 << LOCK_SHIFT);
 231         }
 232         writel(val, reg);
 233
 234         return;
 235 }
 236 #endif
 237
 238 #ifdef TEGRA_PMX_PINS_HAVE_OD
 239 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
 240 {
 241         u32 *reg = REG(pin);
 242         u32 val;
 243
 244         if (od == PMUX_PIN_OD_DEFAULT)
 245                 return;
 246
 247         /* Error check on pin and od */
 248         assert(pmux_pingrp_isvalid(pin));
 249         assert(pmux_pin_od_isvalid(od));
 250
 251         val = readl(reg);
 252         if (od == PMUX_PIN_OD_ENABLE)
 253                 val |= (1 << OD_SHIFT);
 254         else
 255                 val &= ~(1 << OD_SHIFT);
 256         writel(val, reg);
 257
 258         return;
 259 }
 260 #endif
 261
 262 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 263 static void pinmux_set_ioreset(enum pmux_pingrp pin,
 264                                 enum pmux_pin_ioreset ioreset)
 265 {
 266         u32 *reg = REG(pin);
 267         u32 val;
 268
 269         if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
 270                 return;
 271
 272         /* Error check on pin and ioreset */
 273         assert(pmux_pingrp_isvalid(pin));
 274         assert(pmux_pin_ioreset_isvalid(ioreset));
 275
 276         val = readl(reg);
 277         if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
 278                 val |= (1 << IO_RESET_SHIFT);
 279         else
 280                 val &= ~(1 << IO_RESET_SHIFT);
 281         writel(val, reg);
 282
 283         return;
 284 }
 285 #endif
 286
 287 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 288 static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
 289                                 enum pmux_pin_rcv_sel rcv_sel)
 290 {
 291         u32 *reg = REG(pin);
 292         u32 val;
 293
 294         if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
 295                 return;
 296
 297         /* Error check on pin and rcv_sel */
 298         assert(pmux_pingrp_isvalid(pin));
 299         assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
 300
 301         val = readl(reg);
 302         if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
 303                 val |= (1 << RCV_SEL_SHIFT);
 304         else
 305                 val &= ~(1 << RCV_SEL_SHIFT);
 306         writel(val, reg);
 307
 308         return;
 309 }
 310 #endif
 311
 312 static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
 313 {
 314         enum pmux_pingrp pin = config->pingrp;
 315
 316         pinmux_set_func(pin, config->func);
 317         pinmux_set_pullupdown(pin, config->pull);
 318         pinmux_set_tristate(pin, config->tristate);
 319 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 320         pinmux_set_io(pin, config->io);
 321 #endif
 322 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
 323         pinmux_set_lock(pin, config->lock);
 324 #endif
 325 #ifdef TEGRA_PMX_PINS_HAVE_OD
 326         pinmux_set_od(pin, config->od);
 327 #endif
 328 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 329         pinmux_set_ioreset(pin, config->ioreset);
 330 #endif
 331 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 332         pinmux_set_rcv_sel(pin, config->rcv_sel);
 333 #endif
 334 }
 335
 336 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
 337                                 int len)
 338 {
 339         int i;
 340
 341         for (i = 0; i < len; i++)
 342                 pinmux_config_pingrp(&config[i]);
 343 }
 344
 345 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
 346
 347 #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
 348
 349 #define pmux_slw_isvalid(slw) \
 350         (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
 351
 352 #define pmux_drv_isvalid(drv) \
 353         (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
 354
 355 #define pmux_lpmd_isvalid(lpm) \
 356         (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
 357
 358 #define pmux_schmt_isvalid(schmt) \
 359         (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
 360
 361 #define pmux_hsm_isvalid(hsm) \
 362         (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
 363
 364 #define HSM_SHIFT       2
 365 #define SCHMT_SHIFT     3
 366 #define LPMD_SHIFT      4
 367 #define LPMD_MASK       (3 << LPMD_SHIFT)
 368 /*
 369  * Note that the following DRV* and SLW* defines are accurate for many drive
 370  * groups on many SoCs. We really need a per-group data structure to solve
 371  * this, since the fields are in different positions/sizes in different
 372  * registers (for different groups).
 373  *
 374  * On Tegra30/114/124, the DRV*_SHIFT values vary.
 375  * On Tegra30, the SLW*_SHIFT values vary.
 376  * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
 377  *   below are wide enough to cover the widest fields, and hopefully don't
 378  *   interfere with any other fields.
 379  * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
 380  *   wide enough to cover all cases, since that would cause the field to
 381  *   overlap with other fields in the narrower cases.
 382  */
 383 #define DRVDN_SHIFT     12
 384 #define DRVDN_MASK      (0x7F << DRVDN_SHIFT)
 385 #define DRVUP_SHIFT     20
 386 #define DRVUP_MASK      (0x7F << DRVUP_SHIFT)
 387 #define SLWR_SHIFT      28
 388 #define SLWR_MASK       (3 << SLWR_SHIFT)
 389 #define SLWF_SHIFT      30
 390 #define SLWF_MASK       (3 << SLWF_SHIFT)
 391
 392 static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
 393 {
 394         u32 *reg = DRV_REG(grp);
 395         u32 val;
 396
 397         /* NONE means unspecified/do not change/use POR value */
 398         if (slwf == PMUX_SLWF_NONE)
 399                 return;
 400
 401         /* Error check on pad and slwf */
 402         assert(pmux_drvgrp_isvalid(grp));
 403         assert(pmux_slw_isvalid(slwf));
 404
 405         val = readl(reg);
 406         val &= ~SLWF_MASK;
 407         val |= (slwf << SLWF_SHIFT);
 408         writel(val, reg);
 409
 410         return;
 411 }
 412
 413 static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
 414 {
 415         u32 *reg = DRV_REG(grp);
 416         u32 val;
 417
 418         /* NONE means unspecified/do not change/use POR value */
 419         if (slwr == PMUX_SLWR_NONE)
 420                 return;
 421
 422         /* Error check on pad and slwr */
 423         assert(pmux_drvgrp_isvalid(grp));
 424         assert(pmux_slw_isvalid(slwr));
 425
 426         val = readl(reg);
 427         val &= ~SLWR_MASK;
 428         val |= (slwr << SLWR_SHIFT);
 429         writel(val, reg);
 430
 431         return;
 432 }
 433
 434 static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
 435 {
 436         u32 *reg = DRV_REG(grp);
 437         u32 val;
 438
 439         /* NONE means unspecified/do not change/use POR value */
 440         if (drvup == PMUX_DRVUP_NONE)
 441                 return;
 442
 443         /* Error check on pad and drvup */
 444         assert(pmux_drvgrp_isvalid(grp));
 445         assert(pmux_drv_isvalid(drvup));
 446
 447         val = readl(reg);
 448         val &= ~DRVUP_MASK;
 449         val |= (drvup << DRVUP_SHIFT);
 450         writel(val, reg);
 451
 452         return;
 453 }
 454
 455 static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
 456 {
 457         u32 *reg = DRV_REG(grp);
 458         u32 val;
 459
 460         /* NONE means unspecified/do not change/use POR value */
 461         if (drvdn == PMUX_DRVDN_NONE)
 462                 return;
 463
 464         /* Error check on pad and drvdn */
 465         assert(pmux_drvgrp_isvalid(grp));
 466         assert(pmux_drv_isvalid(drvdn));
 467
 468         val = readl(reg);
 469         val &= ~DRVDN_MASK;
 470         val |= (drvdn << DRVDN_SHIFT);
 471         writel(val, reg);
 472
 473         return;
 474 }
 475
 476 static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
 477 {
 478         u32 *reg = DRV_REG(grp);
 479         u32 val;
 480
 481         /* NONE means unspecified/do not change/use POR value */
 482         if (lpmd == PMUX_LPMD_NONE)
 483                 return;
 484
 485         /* Error check pad and lpmd value */
 486         assert(pmux_drvgrp_isvalid(grp));
 487         assert(pmux_lpmd_isvalid(lpmd));
 488
 489         val = readl(reg);
 490         val &= ~LPMD_MASK;
 491         val |= (lpmd << LPMD_SHIFT);
 492         writel(val, reg);
 493
 494         return;
 495 }
 496
 497 static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
 498 {
 499         u32 *reg = DRV_REG(grp);
 500         u32 val;
 501
 502         /* NONE means unspecified/do not change/use POR value */
 503         if (schmt == PMUX_SCHMT_NONE)
 504                 return;
 505
 506         /* Error check pad */
 507         assert(pmux_drvgrp_isvalid(grp));
 508         assert(pmux_schmt_isvalid(schmt));
 509
 510         val = readl(reg);
 511         if (schmt == PMUX_SCHMT_ENABLE)
 512                 val |= (1 << SCHMT_SHIFT);
 513         else
 514                 val &= ~(1 << SCHMT_SHIFT);
 515         writel(val, reg);
 516
 517         return;
 518 }
 519
 520 static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
 521 {
 522         u32 *reg = DRV_REG(grp);
 523         u32 val;
 524
 525         /* NONE means unspecified/do not change/use POR value */
 526         if (hsm == PMUX_HSM_NONE)
 527                 return;
 528
 529         /* Error check pad */
 530         assert(pmux_drvgrp_isvalid(grp));
 531         assert(pmux_hsm_isvalid(hsm));
 532
 533         val = readl(reg);
 534         if (hsm == PMUX_HSM_ENABLE)
 535                 val |= (1 << HSM_SHIFT);
 536         else
 537                 val &= ~(1 << HSM_SHIFT);
 538         writel(val, reg);
 539
 540         return;
 541 }
 542
 543 static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
 544 {
 545         enum pmux_drvgrp grp = config->drvgrp;
 546
 547         pinmux_set_drvup_slwf(grp, config->slwf);
 548         pinmux_set_drvdn_slwr(grp, config->slwr);
 549         pinmux_set_drvup(grp, config->drvup);
 550         pinmux_set_drvdn(grp, config->drvdn);
 551         pinmux_set_lpmd(grp, config->lpmd);
 552         pinmux_set_schmt(grp, config->schmt);
 553         pinmux_set_hsm(grp, config->hsm);
 554 }
 555
 556 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
 557                                 int len)
 558 {
 559         int i;
 560
 561         for (i = 0; i < len; i++)
 562                 pinmux_config_drvgrp(&config[i]);
 563 }
 564 #endif /* TEGRA_PMX_HAS_DRVGRPS */