2 * (C) Copyright 2013-2015
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra124 Clock control functions */
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sysctr.h>
14 #include <asm/arch/tegra.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
21 * Clock types that we can use as a source. The Tegra124 has muxes for the
22 * peripheral clocks, and in most cases there are four options for the clock
23 * source. This gives us a clock 'type' and exploits what commonality exists
26 * Letters are obvious, except for T which means CLK_M, and S which means the
27 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
28 * datasheet) and PLL_M are different things. The former is the basic
29 * clock supplied to the SOC from an external oscillator. The latter is the
32 * See definitions in clock_id in the header file.
35 CLOCK_TYPE_AXPT
, /* PLL_A, PLL_X, PLL_P, CLK_M */
36 CLOCK_TYPE_MCPA
, /* and so on */
50 CLOCK_TYPE_PC2CC3M_T16
, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
53 CLOCK_TYPE_MCPTM2C2C3
,
55 CLOCK_TYPE_AC2CC3P_TS2
,
58 CLOCK_TYPE_NONE
= -1, /* invalid clock type */
62 CLOCK_MAX_MUX
= 8 /* number of source options for each clock */
66 * Clock source mux for each clock type. This just converts our enum into
67 * a list of mux sources for use by the code.
70 * The extra column in each clock source array is used to store the mask
71 * bits in its register for the source.
73 #define CLK(x) CLOCK_ID_ ## x
74 static enum clock_id clock_source
[CLOCK_TYPE_COUNT
][CLOCK_MAX_MUX
+1] = {
75 { CLK(AUDIO
), CLK(XCPU
), CLK(PERIPH
), CLK(OSC
),
76 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
78 { CLK(MEMORY
), CLK(CGENERAL
), CLK(PERIPH
), CLK(AUDIO
),
79 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
81 { CLK(MEMORY
), CLK(CGENERAL
), CLK(PERIPH
), CLK(OSC
),
82 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
84 { CLK(PERIPH
), CLK(CGENERAL
), CLK(MEMORY
), CLK(NONE
),
85 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
87 { CLK(PERIPH
), CLK(CGENERAL
), CLK(MEMORY
), CLK(OSC
),
88 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
90 { CLK(PERIPH
), CLK(DISPLAY
), CLK(CGENERAL
), CLK(OSC
),
91 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
93 { CLK(AUDIO
), CLK(CGENERAL
), CLK(PERIPH
), CLK(OSC
),
94 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
96 { CLK(AUDIO
), CLK(SFROM32KHZ
), CLK(PERIPH
), CLK(OSC
),
97 CLK(EPCI
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
99 { CLK(PERIPH
), CLK(MEMORY
), CLK(DISPLAY
), CLK(AUDIO
),
100 CLK(CGENERAL
), CLK(DISPLAY2
), CLK(OSC
), CLK(NONE
),
102 { CLK(PERIPH
), CLK(CGENERAL
), CLK(SFROM32KHZ
), CLK(OSC
),
103 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
106 { CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
107 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
110 /* Additional clock types on Tegra114+ */
111 /* CLOCK_TYPE_PC2CC3M */
112 { CLK(PERIPH
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
113 CLK(MEMORY
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
115 /* CLOCK_TYPE_PC2CC3S_T */
116 { CLK(PERIPH
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
117 CLK(SFROM32KHZ
), CLK(NONE
), CLK(OSC
), CLK(NONE
),
119 /* CLOCK_TYPE_PC2CC3M_T */
120 { CLK(PERIPH
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
121 CLK(MEMORY
), CLK(NONE
), CLK(OSC
), CLK(NONE
),
123 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
124 { CLK(PERIPH
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
125 CLK(MEMORY
), CLK(NONE
), CLK(OSC
), CLK(NONE
),
127 /* CLOCK_TYPE_MC2CC3P_A */
128 { CLK(MEMORY
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
129 CLK(PERIPH
), CLK(NONE
), CLK(AUDIO
), CLK(NONE
),
132 { CLK(MEMORY
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
133 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
135 /* CLOCK_TYPE_MCPTM2C2C3 */
136 { CLK(MEMORY
), CLK(CGENERAL
), CLK(PERIPH
), CLK(OSC
),
137 CLK(MEMORY2
), CLK(CGENERAL2
), CLK(CGENERAL3
), CLK(NONE
),
139 /* CLOCK_TYPE_PC2CC3T_S */
140 { CLK(PERIPH
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
141 CLK(OSC
), CLK(NONE
), CLK(SFROM32KHZ
), CLK(NONE
),
143 /* CLOCK_TYPE_AC2CC3P_TS2 */
144 { CLK(AUDIO
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
145 CLK(PERIPH
), CLK(NONE
), CLK(OSC
), CLK(SRC2
),
150 * Clock type for each peripheral clock source. We put the name in each
151 * record just so it is easy to match things up
153 #define TYPE(name, type) type
154 static enum clock_type_id clock_periph_type
[PERIPHC_COUNT
] = {
156 TYPE(PERIPHC_I2S1
, CLOCK_TYPE_AXPT
),
157 TYPE(PERIPHC_I2S2
, CLOCK_TYPE_AXPT
),
158 TYPE(PERIPHC_SPDIF_OUT
, CLOCK_TYPE_AXPT
),
159 TYPE(PERIPHC_SPDIF_IN
, CLOCK_TYPE_PC2CC3M
),
160 TYPE(PERIPHC_PWM
, CLOCK_TYPE_PC2CC3S_T
),
161 TYPE(PERIPHC_05h
, CLOCK_TYPE_NONE
),
162 TYPE(PERIPHC_SBC2
, CLOCK_TYPE_PC2CC3M_T
),
163 TYPE(PERIPHC_SBC3
, CLOCK_TYPE_PC2CC3M_T
),
166 TYPE(PERIPHC_08h
, CLOCK_TYPE_NONE
),
167 TYPE(PERIPHC_I2C1
, CLOCK_TYPE_PC2CC3M_T16
),
168 TYPE(PERIPHC_I2C5
, CLOCK_TYPE_PC2CC3M_T16
),
169 TYPE(PERIPHC_0bh
, CLOCK_TYPE_NONE
),
170 TYPE(PERIPHC_0ch
, CLOCK_TYPE_NONE
),
171 TYPE(PERIPHC_SBC1
, CLOCK_TYPE_PC2CC3M_T
),
172 TYPE(PERIPHC_DISP1
, CLOCK_TYPE_PMDACD2T
),
173 TYPE(PERIPHC_DISP2
, CLOCK_TYPE_PMDACD2T
),
176 TYPE(PERIPHC_10h
, CLOCK_TYPE_NONE
),
177 TYPE(PERIPHC_11h
, CLOCK_TYPE_NONE
),
178 TYPE(PERIPHC_VI
, CLOCK_TYPE_MC2CC3P_A
),
179 TYPE(PERIPHC_13h
, CLOCK_TYPE_NONE
),
180 TYPE(PERIPHC_SDMMC1
, CLOCK_TYPE_PC2CC3M_T
),
181 TYPE(PERIPHC_SDMMC2
, CLOCK_TYPE_PC2CC3M_T
),
182 TYPE(PERIPHC_16h
, CLOCK_TYPE_NONE
),
183 TYPE(PERIPHC_17h
, CLOCK_TYPE_NONE
),
186 TYPE(PERIPHC_18h
, CLOCK_TYPE_NONE
),
187 TYPE(PERIPHC_SDMMC4
, CLOCK_TYPE_PC2CC3M_T
),
188 TYPE(PERIPHC_VFIR
, CLOCK_TYPE_PC2CC3M_T
),
189 TYPE(PERIPHC_1Bh
, CLOCK_TYPE_NONE
),
190 TYPE(PERIPHC_1Ch
, CLOCK_TYPE_NONE
),
191 TYPE(PERIPHC_HSI
, CLOCK_TYPE_PC2CC3M_T
),
192 TYPE(PERIPHC_UART1
, CLOCK_TYPE_PC2CC3M_T
),
193 TYPE(PERIPHC_UART2
, CLOCK_TYPE_PC2CC3M_T
),
196 TYPE(PERIPHC_HOST1X
, CLOCK_TYPE_MC2CC3P_A
),
197 TYPE(PERIPHC_21h
, CLOCK_TYPE_NONE
),
198 TYPE(PERIPHC_22h
, CLOCK_TYPE_NONE
),
199 TYPE(PERIPHC_HDMI
, CLOCK_TYPE_PMDACD2T
),
200 TYPE(PERIPHC_24h
, CLOCK_TYPE_NONE
),
201 TYPE(PERIPHC_25h
, CLOCK_TYPE_NONE
),
202 TYPE(PERIPHC_I2C2
, CLOCK_TYPE_PC2CC3M_T16
),
203 TYPE(PERIPHC_EMC
, CLOCK_TYPE_MCPTM2C2C3
),
206 TYPE(PERIPHC_UART3
, CLOCK_TYPE_PC2CC3M_T
),
207 TYPE(PERIPHC_29h
, CLOCK_TYPE_NONE
),
208 TYPE(PERIPHC_VI_SENSOR
, CLOCK_TYPE_MC2CC3P_A
),
209 TYPE(PERIPHC_2bh
, CLOCK_TYPE_NONE
),
210 TYPE(PERIPHC_2ch
, CLOCK_TYPE_NONE
),
211 TYPE(PERIPHC_SBC4
, CLOCK_TYPE_PC2CC3M_T
),
212 TYPE(PERIPHC_I2C3
, CLOCK_TYPE_PC2CC3M_T16
),
213 TYPE(PERIPHC_SDMMC3
, CLOCK_TYPE_PC2CC3M_T
),
216 TYPE(PERIPHC_UART4
, CLOCK_TYPE_PC2CC3M_T
),
217 TYPE(PERIPHC_UART5
, CLOCK_TYPE_PC2CC3M_T
),
218 TYPE(PERIPHC_VDE
, CLOCK_TYPE_PC2CC3M_T
),
219 TYPE(PERIPHC_OWR
, CLOCK_TYPE_PC2CC3M_T
),
220 TYPE(PERIPHC_NOR
, CLOCK_TYPE_PC2CC3M_T
),
221 TYPE(PERIPHC_CSITE
, CLOCK_TYPE_PC2CC3M_T
),
222 TYPE(PERIPHC_I2S0
, CLOCK_TYPE_AXPT
),
223 TYPE(PERIPHC_DTV
, CLOCK_TYPE_NONE
),
226 TYPE(PERIPHC_38h
, CLOCK_TYPE_NONE
),
227 TYPE(PERIPHC_39h
, CLOCK_TYPE_NONE
),
228 TYPE(PERIPHC_3ah
, CLOCK_TYPE_NONE
),
229 TYPE(PERIPHC_3bh
, CLOCK_TYPE_NONE
),
230 TYPE(PERIPHC_MSENC
, CLOCK_TYPE_MC2CC3P_A
),
231 TYPE(PERIPHC_TSEC
, CLOCK_TYPE_PC2CC3M_T
),
232 TYPE(PERIPHC_3eh
, CLOCK_TYPE_NONE
),
233 TYPE(PERIPHC_OSC
, CLOCK_TYPE_NONE
),
236 TYPE(PERIPHC_40h
, CLOCK_TYPE_NONE
), /* start with 0x3b0 */
237 TYPE(PERIPHC_MSELECT
, CLOCK_TYPE_PC2CC3M_T
),
238 TYPE(PERIPHC_TSENSOR
, CLOCK_TYPE_PC2CC3T_S
),
239 TYPE(PERIPHC_I2S3
, CLOCK_TYPE_AXPT
),
240 TYPE(PERIPHC_I2S4
, CLOCK_TYPE_AXPT
),
241 TYPE(PERIPHC_I2C4
, CLOCK_TYPE_PC2CC3M_T16
),
242 TYPE(PERIPHC_SBC5
, CLOCK_TYPE_PC2CC3M_T
),
243 TYPE(PERIPHC_SBC6
, CLOCK_TYPE_PC2CC3M_T
),
246 TYPE(PERIPHC_AUDIO
, CLOCK_TYPE_AC2CC3P_TS2
),
247 TYPE(PERIPHC_49h
, CLOCK_TYPE_NONE
),
248 TYPE(PERIPHC_DAM0
, CLOCK_TYPE_AC2CC3P_TS2
),
249 TYPE(PERIPHC_DAM1
, CLOCK_TYPE_AC2CC3P_TS2
),
250 TYPE(PERIPHC_DAM2
, CLOCK_TYPE_AC2CC3P_TS2
),
251 TYPE(PERIPHC_HDA2CODEC2X
, CLOCK_TYPE_PC2CC3M_T
),
252 TYPE(PERIPHC_ACTMON
, CLOCK_TYPE_PC2CC3S_T
),
253 TYPE(PERIPHC_EXTPERIPH1
, CLOCK_TYPE_ASPTE
),
256 TYPE(PERIPHC_EXTPERIPH2
, CLOCK_TYPE_ASPTE
),
257 TYPE(PERIPHC_EXTPERIPH3
, CLOCK_TYPE_ASPTE
),
258 TYPE(PERIPHC_52h
, CLOCK_TYPE_NONE
),
259 TYPE(PERIPHC_I2CSLOW
, CLOCK_TYPE_PC2CC3S_T
),
260 TYPE(PERIPHC_SYS
, CLOCK_TYPE_NONE
),
261 TYPE(PERIPHC_55h
, CLOCK_TYPE_NONE
),
262 TYPE(PERIPHC_56h
, CLOCK_TYPE_NONE
),
263 TYPE(PERIPHC_57h
, CLOCK_TYPE_NONE
),
266 TYPE(PERIPHC_58h
, CLOCK_TYPE_NONE
),
267 TYPE(PERIPHC_SOR
, CLOCK_TYPE_NONE
),
268 TYPE(PERIPHC_5ah
, CLOCK_TYPE_NONE
),
269 TYPE(PERIPHC_5bh
, CLOCK_TYPE_NONE
),
270 TYPE(PERIPHC_SATAOOB
, CLOCK_TYPE_PCMT
),
271 TYPE(PERIPHC_SATA
, CLOCK_TYPE_PCMT
),
272 TYPE(PERIPHC_HDA
, CLOCK_TYPE_PC2CC3M_T
),
273 TYPE(PERIPHC_5fh
, CLOCK_TYPE_NONE
),
276 TYPE(PERIPHC_XUSB_CORE_HOST
, CLOCK_TYPE_NONE
),
277 TYPE(PERIPHC_XUSB_FALCON
, CLOCK_TYPE_NONE
),
278 TYPE(PERIPHC_XUSB_FS
, CLOCK_TYPE_NONE
),
279 TYPE(PERIPHC_XUSB_CORE_DEV
, CLOCK_TYPE_NONE
),
280 TYPE(PERIPHC_XUSB_SS
, CLOCK_TYPE_NONE
),
281 TYPE(PERIPHC_CILAB
, CLOCK_TYPE_NONE
),
282 TYPE(PERIPHC_CILCD
, CLOCK_TYPE_NONE
),
283 TYPE(PERIPHC_CILE
, CLOCK_TYPE_NONE
),
286 TYPE(PERIPHC_DSIA_LP
, CLOCK_TYPE_NONE
),
287 TYPE(PERIPHC_DSIB_LP
, CLOCK_TYPE_NONE
),
288 TYPE(PERIPHC_ENTROPY
, CLOCK_TYPE_NONE
),
289 TYPE(PERIPHC_DVFS_REF
, CLOCK_TYPE_NONE
),
290 TYPE(PERIPHC_DVFS_SOC
, CLOCK_TYPE_NONE
),
291 TYPE(PERIPHC_TRACECLKIN
, CLOCK_TYPE_NONE
),
292 TYPE(PERIPHC_ADX0
, CLOCK_TYPE_NONE
),
293 TYPE(PERIPHC_AMX0
, CLOCK_TYPE_NONE
),
296 TYPE(PERIPHC_EMC_LATENCY
, CLOCK_TYPE_NONE
),
297 TYPE(PERIPHC_SOC_THERM
, CLOCK_TYPE_NONE
),
298 TYPE(PERIPHC_72h
, CLOCK_TYPE_NONE
),
299 TYPE(PERIPHC_73h
, CLOCK_TYPE_NONE
),
300 TYPE(PERIPHC_74h
, CLOCK_TYPE_NONE
),
301 TYPE(PERIPHC_75h
, CLOCK_TYPE_NONE
),
302 TYPE(PERIPHC_VI_SENSOR2
, CLOCK_TYPE_NONE
),
303 TYPE(PERIPHC_I2C6
, CLOCK_TYPE_PC2CC3M_T16
),
306 TYPE(PERIPHC_78h
, CLOCK_TYPE_NONE
),
307 TYPE(PERIPHC_EMC_DLL
, CLOCK_TYPE_MCPTM2C2C3
),
308 TYPE(PERIPHC_HDMI_AUDIO
, CLOCK_TYPE_NONE
),
309 TYPE(PERIPHC_CLK72MHZ
, CLOCK_TYPE_NONE
),
310 TYPE(PERIPHC_ADX1
, CLOCK_TYPE_AC2CC3P_TS2
),
311 TYPE(PERIPHC_AMX1
, CLOCK_TYPE_AC2CC3P_TS2
),
312 TYPE(PERIPHC_VIC
, CLOCK_TYPE_NONE
),
313 TYPE(PERIPHC_7Fh
, CLOCK_TYPE_NONE
),
317 * This array translates a periph_id to a periphc_internal_id
319 * Not present/matched up:
320 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
321 * SPDIF - which is both 0x08 and 0x0c
324 #define NONE(name) (-1)
325 #define OFFSET(name, value) PERIPHC_ ## name
326 static s8 periph_id_to_internal_id
[PERIPH_ID_COUNT
] = {
335 PERIPHC_UART2
, /* and vfir 0x68 */
367 /* Middle word: 63:32 */
379 PERIPHC_SBC1
, /* SBCx = SPIx */
407 /* Upper word 95:64 */
569 * PLL divider shift/mask tables for all PLL IDs.
571 struct clk_pll_info tegra_pll_info_table
[CLOCK_ID_PLL_COUNT
] = {
573 * T124: same as T114, some deviations from T2x/T30.
574 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
575 * If lock_ena or lock_det are >31, they're not used in that PLL.
578 { .m_shift
= 0, .m_mask
= 0xFF, .n_shift
= 8, .n_mask
= 0xFF, .p_shift
= 20, .p_mask
= 0x0F,
579 .lock_ena
= 24, .lock_det
= 27, .kcp_shift
= 28, .kcp_mask
= 3, .kvco_shift
= 27, .kvco_mask
= 1 }, /* PLLC */
580 { .m_shift
= 0, .m_mask
= 0xFF, .n_shift
= 8, .n_mask
= 0xFF, .p_shift
= 0, .p_mask
= 0,
581 .lock_ena
= 0, .lock_det
= 27, .kcp_shift
= 1, .kcp_mask
= 3, .kvco_shift
= 0, .kvco_mask
= 1 }, /* PLLM */
582 { .m_shift
= 0, .m_mask
= 0x1F, .n_shift
= 8, .n_mask
= 0x3FF, .p_shift
= 20, .p_mask
= 0x07,
583 .lock_ena
= 18, .lock_det
= 27, .kcp_shift
= 8, .kcp_mask
= 0xF, .kvco_shift
= 4, .kvco_mask
= 0xF }, /* PLLP */
584 { .m_shift
= 0, .m_mask
= 0x1F, .n_shift
= 8, .n_mask
= 0x3FF, .p_shift
= 20, .p_mask
= 0x07,
585 .lock_ena
= 18, .lock_det
= 27, .kcp_shift
= 8, .kcp_mask
= 0xF, .kvco_shift
= 4, .kvco_mask
= 0xF }, /* PLLA */
586 { .m_shift
= 0, .m_mask
= 0x1F, .n_shift
= 8, .n_mask
= 0x3FF, .p_shift
= 20, .p_mask
= 0x01,
587 .lock_ena
= 22, .lock_det
= 27, .kcp_shift
= 8, .kcp_mask
= 0xF, .kvco_shift
= 4, .kvco_mask
= 0xF }, /* PLLU */
588 { .m_shift
= 0, .m_mask
= 0x1F, .n_shift
= 8, .n_mask
= 0x3FF, .p_shift
= 20, .p_mask
= 0x07,
589 .lock_ena
= 22, .lock_det
= 27, .kcp_shift
= 8, .kcp_mask
= 0xF, .kvco_shift
= 4, .kvco_mask
= 0xF }, /* PLLD */
590 { .m_shift
= 0, .m_mask
= 0xFF, .n_shift
= 8, .n_mask
= 0xFF, .p_shift
= 20, .p_mask
= 0x0F,
591 .lock_ena
= 18, .lock_det
= 27, .kcp_shift
= 0, .kcp_mask
= 0, .kvco_shift
= 0, .kvco_mask
= 0 }, /* PLLX */
592 { .m_shift
= 0, .m_mask
= 0xFF, .n_shift
= 8, .n_mask
= 0xFF, .p_shift
= 0, .p_mask
= 0,
593 .lock_ena
= 9, .lock_det
= 11, .kcp_shift
= 6, .kcp_mask
= 3, .kvco_shift
= 0, .kvco_mask
= 1 }, /* PLLE */
594 { .m_shift
= 0, .m_mask
= 0x0F, .n_shift
= 8, .n_mask
= 0x3FF, .p_shift
= 20, .p_mask
= 0x07,
595 .lock_ena
= 18, .lock_det
= 27, .kcp_shift
= 8, .kcp_mask
= 0xF, .kvco_shift
= 4, .kvco_mask
= 0xF }, /* PLLS (RESERVED) */
599 * Get the oscillator frequency, from the corresponding hardware configuration
600 * field. Note that Tegra30+ support 3 new higher freqs, but we map back
601 * to the old T20 freqs. Support for the higher oscillators is TBD.
603 enum clock_osc_freq
clock_get_osc_freq(void)
605 struct clk_rst_ctlr
*clkrst
=
606 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
609 reg
= readl(&clkrst
->crc_osc_ctrl
);
610 reg
= (reg
& OSC_FREQ_MASK
) >> OSC_FREQ_SHIFT
;
612 if (reg
& 1) /* one of the newer freqs */
613 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg
);
615 return reg
>> 2; /* Map to most common (T20) freqs */
618 /* Returns a pointer to the clock source register for a peripheral */
619 u32
*get_periph_source_reg(enum periph_id periph_id
)
621 struct clk_rst_ctlr
*clkrst
=
622 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
623 enum periphc_internal_id internal_id
;
625 /* Coresight is a special case */
626 if (periph_id
== PERIPH_ID_CSI
)
627 return &clkrst
->crc_clk_src
[PERIPH_ID_CSI
+1];
629 assert(periph_id
>= PERIPH_ID_FIRST
&& periph_id
< PERIPH_ID_COUNT
);
630 internal_id
= periph_id_to_internal_id
[periph_id
];
631 assert(internal_id
!= -1);
632 if (internal_id
>= PERIPHC_X_FIRST
) {
633 internal_id
-= PERIPHC_X_FIRST
;
634 return &clkrst
->crc_clk_src_x
[internal_id
];
635 } else if (internal_id
>= PERIPHC_VW_FIRST
) {
636 internal_id
-= PERIPHC_VW_FIRST
;
637 return &clkrst
->crc_clk_src_vw
[internal_id
];
639 return &clkrst
->crc_clk_src
[internal_id
];
644 * Given a peripheral ID and the required source clock, this returns which
645 * value should be programmed into the source mux for that peripheral.
647 * There is special code here to handle the one source type with 5 sources.
649 * @param periph_id peripheral to start
650 * @param source PLL id of required parent clock
651 * @param mux_bits Set to number of bits in mux register: 2 or 4
652 * @param divider_bits Set to number of divider bits (8 or 16)
653 * @return mux value (0-4, or -1 if not found)
655 int get_periph_clock_source(enum periph_id periph_id
,
656 enum clock_id parent
, int *mux_bits
, int *divider_bits
)
658 enum clock_type_id type
;
659 enum periphc_internal_id internal_id
;
662 assert(clock_periph_id_isvalid(periph_id
));
664 internal_id
= periph_id_to_internal_id
[periph_id
];
665 assert(periphc_internal_id_isvalid(internal_id
));
667 type
= clock_periph_type
[internal_id
];
668 assert(clock_type_id_isvalid(type
));
670 *mux_bits
= clock_source
[type
][CLOCK_MAX_MUX
];
672 if (type
== CLOCK_TYPE_PC2CC3M_T16
)
677 for (mux
= 0; mux
< CLOCK_MAX_MUX
; mux
++)
678 if (clock_source
[type
][mux
] == parent
)
681 /* if we get here, either us or the caller has made a mistake */
682 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id
,
687 void clock_set_enable(enum periph_id periph_id
, int enable
)
689 struct clk_rst_ctlr
*clkrst
=
690 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
694 /* Enable/disable the clock to this peripheral */
695 assert(clock_periph_id_isvalid(periph_id
));
696 if ((int)periph_id
< (int)PERIPH_ID_VW_FIRST
)
697 clk
= &clkrst
->crc_clk_out_enb
[PERIPH_REG(periph_id
)];
698 else if ((int)periph_id
< PERIPH_ID_X_FIRST
)
699 clk
= &clkrst
->crc_clk_out_enb_vw
[PERIPH_REG(periph_id
)];
701 clk
= &clkrst
->crc_clk_out_enb_x
;
704 reg
|= PERIPH_MASK(periph_id
);
706 reg
&= ~PERIPH_MASK(periph_id
);
710 void reset_set_enable(enum periph_id periph_id
, int enable
)
712 struct clk_rst_ctlr
*clkrst
=
713 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
717 /* Enable/disable reset to the peripheral */
718 assert(clock_periph_id_isvalid(periph_id
));
719 if (periph_id
< PERIPH_ID_VW_FIRST
)
720 reset
= &clkrst
->crc_rst_dev
[PERIPH_REG(periph_id
)];
721 else if ((int)periph_id
< PERIPH_ID_X_FIRST
)
722 reset
= &clkrst
->crc_rst_dev_vw
[PERIPH_REG(periph_id
)];
724 reset
= &clkrst
->crc_rst_devices_x
;
727 reg
|= PERIPH_MASK(periph_id
);
729 reg
&= ~PERIPH_MASK(periph_id
);
733 #ifdef CONFIG_OF_CONTROL
735 * Convert a device tree clock ID to our peripheral ID. They are mostly
736 * the same but we are very cautious so we check that a valid clock ID is
739 * @param clk_id Clock ID according to tegra124 device tree binding
740 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
742 enum periph_id
clk_id_to_periph_id(int clk_id
)
744 if (clk_id
> PERIPH_ID_COUNT
)
745 return PERIPH_ID_NONE
;
748 case PERIPH_ID_RESERVED4
:
749 case PERIPH_ID_RESERVED25
:
750 case PERIPH_ID_RESERVED35
:
751 case PERIPH_ID_RESERVED36
:
752 case PERIPH_ID_RESERVED38
:
753 case PERIPH_ID_RESERVED43
:
754 case PERIPH_ID_RESERVED49
:
755 case PERIPH_ID_RESERVED53
:
756 case PERIPH_ID_RESERVED64
:
757 case PERIPH_ID_RESERVED84
:
758 case PERIPH_ID_RESERVED85
:
759 case PERIPH_ID_RESERVED86
:
760 case PERIPH_ID_RESERVED88
:
761 case PERIPH_ID_RESERVED90
:
762 case PERIPH_ID_RESERVED92
:
763 case PERIPH_ID_RESERVED93
:
764 case PERIPH_ID_RESERVED94
:
765 case PERIPH_ID_V_RESERVED2
:
766 case PERIPH_ID_V_RESERVED4
:
767 case PERIPH_ID_V_RESERVED17
:
768 case PERIPH_ID_V_RESERVED18
:
769 case PERIPH_ID_V_RESERVED19
:
770 case PERIPH_ID_V_RESERVED20
:
771 case PERIPH_ID_V_RESERVED21
:
772 case PERIPH_ID_V_RESERVED22
:
773 case PERIPH_ID_W_RESERVED2
:
774 case PERIPH_ID_W_RESERVED3
:
775 case PERIPH_ID_W_RESERVED4
:
776 case PERIPH_ID_W_RESERVED5
:
777 case PERIPH_ID_W_RESERVED6
:
778 case PERIPH_ID_W_RESERVED7
:
779 case PERIPH_ID_W_RESERVED9
:
780 case PERIPH_ID_W_RESERVED10
:
781 case PERIPH_ID_W_RESERVED11
:
782 case PERIPH_ID_W_RESERVED12
:
783 case PERIPH_ID_W_RESERVED13
:
784 case PERIPH_ID_W_RESERVED15
:
785 case PERIPH_ID_W_RESERVED16
:
786 case PERIPH_ID_W_RESERVED17
:
787 case PERIPH_ID_W_RESERVED18
:
788 case PERIPH_ID_W_RESERVED19
:
789 case PERIPH_ID_W_RESERVED20
:
790 case PERIPH_ID_W_RESERVED23
:
791 case PERIPH_ID_W_RESERVED29
:
792 case PERIPH_ID_W_RESERVED30
:
793 case PERIPH_ID_W_RESERVED31
:
794 return PERIPH_ID_NONE
;
799 #endif /* CONFIG_OF_CONTROL */
801 void clock_early_init(void)
803 struct clk_rst_ctlr
*clkrst
=
804 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
805 struct clk_pll_info
*pllinfo
;
808 tegra30_set_up_pllp();
811 * PLLC output frequency set to 600Mhz
812 * PLLD output frequency set to 925Mhz
814 switch (clock_get_osc_freq()) {
815 case CLOCK_OSC_FREQ_12_0
: /* OSC is 12Mhz */
816 clock_set_rate(CLOCK_ID_CGENERAL
, 600, 12, 0, 8);
817 clock_set_rate(CLOCK_ID_DISPLAY
, 925, 12, 0, 12);
820 case CLOCK_OSC_FREQ_26_0
: /* OSC is 26Mhz */
821 clock_set_rate(CLOCK_ID_CGENERAL
, 600, 26, 0, 8);
822 clock_set_rate(CLOCK_ID_DISPLAY
, 925, 26, 0, 12);
825 case CLOCK_OSC_FREQ_13_0
: /* OSC is 13Mhz */
826 clock_set_rate(CLOCK_ID_CGENERAL
, 600, 13, 0, 8);
827 clock_set_rate(CLOCK_ID_DISPLAY
, 925, 13, 0, 12);
829 case CLOCK_OSC_FREQ_19_2
:
832 * These are not supported. It is too early to print a
833 * message and the UART likely won't work anyway due to the
834 * oscillator being wrong.
839 /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
840 writel(0x00561600, &clkrst
->crc_pll
[CLOCK_ID_CGENERAL
].pll_out
[1]);
842 /* PLLC_MISC: Set LOCK_ENABLE */
843 pllinfo
= &tegra_pll_info_table
[CLOCK_ID_CGENERAL
];
844 setbits_le32(&clkrst
->crc_pll
[CLOCK_ID_CGENERAL
].pll_misc
, (1 << pllinfo
->lock_ena
));
847 /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */
848 pllinfo
= &tegra_pll_info_table
[CLOCK_ID_DISPLAY
];
849 data
= (12 << pllinfo
->kcp_shift
) | (1 << pllinfo
->kvco_shift
);
850 data
|= (1 << PLLD_CLKENABLE
) | (1 << pllinfo
->lock_ena
);
851 writel(data
, &clkrst
->crc_pll
[CLOCK_ID_DISPLAY
].pll_misc
);
855 void arch_timer_init(void)
857 struct sysctr_ctlr
*sysctr
= (struct sysctr_ctlr
*)NV_PA_TSC_BASE
;
860 freq
= clock_get_rate(CLOCK_ID_OSC
);
861 debug("%s: osc freq is %dHz [0x%08X]\n", __func__
, freq
, freq
);
864 asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq
));
866 /* Only Tegra114+ has the System Counter regs */
867 debug("%s: setting CNTFID0 to 0x%08X\n", __func__
, freq
);
868 writel(freq
, &sysctr
->cntfid0
);
870 val
= readl(&sysctr
->cntcr
);
871 val
|= TSC_CNTCR_ENABLE
| TSC_CNTCR_HDBG
;
872 writel(val
, &sysctr
->cntcr
);
873 debug("%s: TSC CNTCR = 0x%08X\n", __func__
, val
);
876 #define PLLE_SS_CNTL 0x68
877 #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
878 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
879 #define PLLE_SS_CNTL_SSCINVERT (1 << 15)
880 #define PLLE_SS_CNTL_SSCCENTER (1 << 14)
881 #define PLLE_SS_CNTL_SSCBYP (1 << 12)
882 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
883 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
884 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
886 #define PLLE_BASE 0x0e8
887 #define PLLE_BASE_ENABLE (1 << 30)
888 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29)
889 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
890 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
891 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
893 #define PLLE_MISC 0x0ec
894 #define PLLE_MISC_IDDQ_SWCTL (1 << 14)
895 #define PLLE_MISC_IDDQ_OVERRIDE (1 << 13)
896 #define PLLE_MISC_LOCK_ENABLE (1 << 9)
897 #define PLLE_MISC_PTS (1 << 8)
898 #define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4)
899 #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
901 #define PLLE_AUX 0x48c
902 #define PLLE_AUX_SEQ_ENABLE (1 << 24)
903 #define PLLE_AUX_ENABLE_SWCTL (1 << 4)
905 int tegra_plle_enable(void)
907 unsigned int m
= 1, n
= 200, cpcon
= 13;
910 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_BASE
);
911 value
&= ~PLLE_BASE_LOCK_OVERRIDE
;
912 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_BASE
);
914 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_AUX
);
915 value
|= PLLE_AUX_ENABLE_SWCTL
;
916 value
&= ~PLLE_AUX_SEQ_ENABLE
;
917 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_AUX
);
921 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_MISC
);
922 value
|= PLLE_MISC_IDDQ_SWCTL
;
923 value
&= ~PLLE_MISC_IDDQ_OVERRIDE
;
924 value
|= PLLE_MISC_LOCK_ENABLE
;
925 value
|= PLLE_MISC_PTS
;
926 value
|= PLLE_MISC_VREG_BG_CTRL(3);
927 value
|= PLLE_MISC_VREG_CTRL(2);
928 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_MISC
);
932 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_SS_CNTL
);
933 value
|= PLLE_SS_CNTL_SSCBYP
| PLLE_SS_CNTL_INTERP_RESET
|
934 PLLE_SS_CNTL_BYPASS_SS
;
935 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_SS_CNTL
);
937 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_BASE
);
938 value
&= ~PLLE_BASE_PLDIV_CML(0xf);
939 value
&= ~PLLE_BASE_NDIV(0xff);
940 value
&= ~PLLE_BASE_MDIV(0xff);
941 value
|= PLLE_BASE_PLDIV_CML(cpcon
);
942 value
|= PLLE_BASE_NDIV(n
);
943 value
|= PLLE_BASE_MDIV(m
);
944 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_BASE
);
948 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_BASE
);
949 value
|= PLLE_BASE_ENABLE
;
950 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_BASE
);
955 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_SS_CNTL
);
956 value
&= ~PLLE_SS_CNTL_SSCINVERT
;
957 value
&= ~PLLE_SS_CNTL_SSCCENTER
;
959 value
&= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
960 value
&= ~PLLE_SS_CNTL_SSCINC(0xff);
961 value
&= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
963 value
|= PLLE_SS_CNTL_SSCINCINTR(0x20);
964 value
|= PLLE_SS_CNTL_SSCINC(0x01);
965 value
|= PLLE_SS_CNTL_SSCMAX(0x25);
967 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_SS_CNTL
);
969 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_SS_CNTL
);
970 value
&= ~PLLE_SS_CNTL_SSCBYP
;
971 value
&= ~PLLE_SS_CNTL_BYPASS_SS
;
972 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_SS_CNTL
);
976 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_SS_CNTL
);
977 value
&= ~PLLE_SS_CNTL_INTERP_RESET
;
978 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_SS_CNTL
);
985 void clock_sor_enable_edp_clock(void)
989 /* uses PLLP, has a non-standard bit layout. */
990 reg
= get_periph_source_reg(PERIPH_ID_SOR0
);
991 setbits_le32(reg
, SOR0_CLK_SEL0
);
994 u32
clock_set_display_rate(u32 frequency
)
997 * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz
998 * = (cf * n) >> p, where 1MHz < cf < 6MHz
999 * = ((ref / m) * n) >> p
1001 * Iterate the possible values of p (3 bits, 2^7) to find out a minimum
1002 * safe vco, then find best (m, n). since m has only 5 bits, we can
1003 * iterate all possible values. Note Tegra 124 supports 11 bits for n,
1004 * but our pll_fields has only 10 bits for n.
1006 * Note values undershoot or overshoot target output frequency may not
1007 * work if the values are not in "safe" range by panel specification.
1009 u32 ref
= clock_get_rate(CLOCK_ID_OSC
);
1010 u32 divm
, divn
, divp
, cpcon
;
1011 u32 cf
, vco
, rounded_rate
= frequency
;
1012 u32 diff
, best_diff
, best_m
= 0, best_n
= 0, best_p
;
1013 const u32 max_m
= 1 << 5, max_n
= 1 << 10, max_p
= 1 << 3,
1014 mhz
= 1000 * 1000, min_vco
= 500 * mhz
, max_vco
= 1000 * mhz
,
1015 min_cf
= 1 * mhz
, max_cf
= 6 * mhz
;
1016 int mux_bits
, divider_bits
, source
;
1018 for (divp
= 0, vco
= frequency
; vco
< min_vco
&& divp
< max_p
; divp
++)
1021 if (vco
< min_vco
|| vco
> max_vco
) {
1022 printf("%s: Cannot find out a supported VCO for Frequency (%u)\n",
1023 __func__
, frequency
);
1030 for (divm
= 1; divm
< max_m
&& best_diff
; divm
++) {
1041 diff
= vco
- divn
* cf
;
1042 if (divn
+ 1 < max_n
&& diff
> cf
/ 2) {
1047 if (diff
>= best_diff
)
1057 else if (best_n
< 300)
1059 else if (best_n
< 600)
1065 printf("%s: Failed to match output frequency %u, best difference is %u\n",
1066 __func__
, frequency
, best_diff
);
1067 rounded_rate
= (ref
/ best_m
* best_n
) >> best_p
;
1070 debug("%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n",
1071 __func__
, rounded_rate
, ref
, best_m
, best_n
, best_p
, cpcon
);
1073 source
= get_periph_clock_source(PERIPH_ID_DISP1
, CLOCK_ID_DISPLAY
,
1074 &mux_bits
, ÷r_bits
);
1075 clock_ll_set_source_bits(PERIPH_ID_DISP1
, mux_bits
, source
);
1076 clock_set_rate(CLOCK_ID_DISPLAY
, best_n
, best_m
, best_p
, cpcon
);
1078 return rounded_rate
;
1081 void clock_set_up_plldp(void)
1083 struct clk_rst_ctlr
*clkrst
=
1084 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
1087 value
= PLLDP_SS_CFG_UNDOCUMENTED
| PLLDP_SS_CFG_DITHER
;
1088 writel(value
| PLLDP_SS_CFG_CLAMP
, &clkrst
->crc_plldp_ss_cfg
);
1089 clock_start_pll(CLOCK_ID_DP
, 1, 90, 3, 0, 0);
1090 writel(value
, &clkrst
->crc_plldp_ss_cfg
);
1093 struct clk_pll_simple
*clock_get_simple_pll(enum clock_id clkid
)
1095 struct clk_rst_ctlr
*clkrst
=
1096 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
1098 if (clkid
== CLOCK_ID_DP
)
1099 return &clkrst
->plldp
;