arch/arm/mach-uniphier/arm-mpcore.h

   1 /*
   2  * Copyright (C) 2011-2014 Panasonic Corporation
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef ARCH_ARM_MPCORE_H
   8 #define ARCH_ARM_MPCORE_H
   9
  10 /* Snoop Control Unit */
  11 #define SCU_OFFSET              0x00
  12
  13 /* SCU Control Register */
  14 #define SCU_CTRL                0x00
  15 /* SCU Configuration Register */
  16 #define SCU_CONF                0x04
  17 /* SCU CPU Power Status Register */
  18 #define SCU_PWR_STATUS          0x08
  19 /* SCU Invalidate All Registers in Secure State */
  20 #define SCU_INV_ALL             0x0C
  21 /* SCU Filtering Start Address Register */
  22 #define SCU_FILTER_START        0x40
  23 /* SCU Filtering End Address Register */
  24 #define SCU_FILTER_END          0x44
  25 /* SCU Access Control Register */
  26 #define SCU_SAC                 0x50
  27 /* SCU Non-secure Access Control Register */
  28 #define SCU_SNSAC               0x54
  29
  30 /* Global Timer */
  31 #define GLOBAL_TIMER_OFFSET     0x200
  32
  33 /* Global Timer Counter Registers */
  34 #define GTIMER_CNT_L            0x00
  35 #define GTIMER_CNT_H            0x04
  36 /* Global Timer Control Register */
  37 #define GTIMER_CTRL             0x08
  38 /* Global Timer Interrupt Status Register */
  39 #define GTIMER_STAT             0x0C
  40 /* Comparator Value Registers */
  41 #define GTIMER_CMP_L            0x10
  42 #define GTIMER_CMP_H            0x14
  43 /* Auto-increment Register */
  44 #define GTIMER_INC              0x18
  45
  46 #endif /* ARCH_ARM_MPCORE_H */