arch/arm/mach-uniphier/arm32/debug_ll.S

   1 /*
   2  * On-chip UART initializaion for low-level debugging
   3  *
   4  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <linux/serial_reg.h>
  10 #include <linux/linkage.h>
  11
  12 #include "../bcu/bcu-regs.h"
  13 #include "../sc-regs.h"
  14 #include "../sg-regs.h"
  15
  16 #if !defined(CONFIG_DEBUG_SEMIHOSTING)
  17 #include CONFIG_DEBUG_LL_INCLUDE
  18 #endif
  19
  20 #define BAUDRATE                115200
  21 #define DIV_ROUND(x, d)         (((x) + ((d) / 2)) / (d))
  22
  23 ENTRY(debug_ll_init)
  24         ldr             r0, =SG_REVISION
  25         ldr             r1, [r0]
  26         and             r1, r1, #SG_REVISION_TYPE_MASK
  27         mov             r1, r1, lsr #SG_REVISION_TYPE_SHIFT
  28
  29 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
  30 #define UNIPHIER_SLD3_UART_CLK          36864000
  31         cmp             r1, #0x25
  32         bne             sld3_end
  33
  34         sg_set_pinsel   64, 1, 4, 4, r0, r1     @ TXD0 -> TXD0
  35
  36         ldr             r0, =BCSCR5
  37         ldr             r1, =0x24440000
  38         str             r1, [r0]
  39
  40         ldr             r0, =SC_CLKCTRL
  41         ldr             r1, [r0]
  42         orr             r1, r1, #SC_CLKCTRL_CEN_PERI
  43         str             r1, [r0]
  44
  45         ldr             r3, =DIV_ROUND(UNIPHIER_SLD3_UART_CLK, 16 * BAUDRATE)
  46
  47         b               init_uart
  48 sld3_end:
  49 #endif
  50 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
  51 #define UNIPHIER_LD4_UART_CLK           36864000
  52         cmp             r1, #0x26
  53         bne             ld4_end
  54
  55         ldr             r0, =SG_IECTRL
  56         ldr             r1, [r0]
  57         orr             r1, r1, #1
  58         str             r1, [r0]
  59
  60         sg_set_pinsel   88, 1, 8, 4, r0, r1     @ HSDOUT6 -> TXD0
  61
  62         ldr             r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE)
  63
  64         b               init_uart
  65 ld4_end:
  66 #endif
  67 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
  68 #define UNIPHIER_PRO4_UART_CLK          73728000
  69         cmp             r1, #0x28
  70         bne             pro4_end
  71
  72         sg_set_pinsel   128, 0, 4, 8, r0, r1    @ TXD0 -> TXD0
  73
  74         ldr             r0, =SG_LOADPINCTRL
  75         mov             r1, #1
  76         str             r1, [r0]
  77
  78         ldr             r0, =SC_CLKCTRL
  79         ldr             r1, [r0]
  80         orr             r1, r1, #SC_CLKCTRL_CEN_PERI
  81         str             r1, [r0]
  82
  83         ldr             r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE)
  84
  85         b               init_uart
  86 pro4_end:
  87 #endif
  88 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
  89 #define UNIPHIER_SLD8_UART_CLK          80000000
  90         cmp             r1, #0x29
  91         bne             sld8_end
  92
  93         ldr             r0, =SG_IECTRL
  94         ldr             r1, [r0]
  95         orr             r1, r1, #1
  96         str             r1, [r0]
  97
  98         sg_set_pinsel   70, 3, 8, 4, r0, r1     @ HSDOUT0 -> TXD0
  99
 100         ldr             r3, =DIV_ROUND(UNIPHIER_SLD8_UART_CLK, 16 * BAUDRATE)
 101
 102         b               init_uart
 103 sld8_end:
 104 #endif
 105 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
 106 #define UNIPHIER_PRO5_UART_CLK          73728000
 107         cmp             r1, #0x2A
 108         bne             pro5_end
 109
 110         sg_set_pinsel   47, 0, 4, 8, r0, r1     @ TXD0 -> TXD0
 111         sg_set_pinsel   49, 0, 4, 8, r0, r1     @ TXD1 -> TXD1
 112         sg_set_pinsel   51, 0, 4, 8, r0, r1     @ TXD2 -> TXD2
 113         sg_set_pinsel   53, 0, 4, 8, r0, r1     @ TXD3 -> TXD3
 114
 115         ldr             r0, =SG_LOADPINCTRL
 116         mov             r1, #1
 117         str             r1, [r0]
 118
 119         ldr             r0, =SC_CLKCTRL
 120         ldr             r1, [r0]
 121         orr             r1, r1, #SC_CLKCTRL_CEN_PERI
 122         str             r1, [r0]
 123
 124         ldr             r3, =DIV_ROUND(UNIPHIER_PRO5_UART_CLK, 16 * BAUDRATE)
 125
 126         b               init_uart
 127 pro5_end:
 128 #endif
 129 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
 130 #define UNIPHIER_PXS2_UART_CLK          88900000
 131         cmp             r1, #0x2E
 132         bne             pxs2_end
 133
 134         ldr             r0, =SG_IECTRL
 135         ldr             r1, [r0]
 136         orr             r1, r1, #1
 137         str             r1, [r0]
 138
 139         sg_set_pinsel   217, 8, 8, 4, r0, r1    @ TXD0 -> TXD0
 140         sg_set_pinsel   115, 8, 8, 4, r0, r1    @ TXD1 -> TXD1
 141         sg_set_pinsel   113, 8, 8, 4, r0, r1    @ TXD2 -> TXD2
 142         sg_set_pinsel   219, 8, 8, 4, r0, r1    @ TXD3 -> TXD3
 143
 144         ldr             r0, =SC_CLKCTRL
 145         ldr             r1, [r0]
 146         orr             r1, r1, #SC_CLKCTRL_CEN_PERI
 147         str             r1, [r0]
 148
 149         ldr             r3, =DIV_ROUND(UNIPHIER_PXS2_UART_CLK, 16 * BAUDRATE)
 150
 151         b               init_uart
 152 pxs2_end:
 153 #endif
 154 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
 155 #define UNIPHIER_LD6B_UART_CLK          88900000
 156         cmp             r1, #0x2F
 157         bne             ld6b_end
 158
 159         ldr             r0, =SG_IECTRL
 160         ldr             r1, [r0]
 161         orr             r1, r1, #1
 162         str             r1, [r0]
 163
 164         sg_set_pinsel   135, 3, 8, 4, r0, r1    @ PORT10 -> TXD0
 165         sg_set_pinsel   115, 0, 8, 4, r0, r1    @ TXD1 -> TXD1
 166         sg_set_pinsel   113, 2, 8, 4, r0, r1    @ SBO0 -> TXD2
 167
 168         ldr             r0, =SC_CLKCTRL
 169         ldr             r1, [r0]
 170         orr             r1, r1, #SC_CLKCTRL_CEN_PERI
 171         str             r1, [r0]
 172
 173         ldr             r3, =DIV_ROUND(UNIPHIER_LD6B_UART_CLK, 16 * BAUDRATE)
 174
 175         b               init_uart
 176 ld6b_end:
 177 #endif
 178         mov             pc, lr
 179
 180 init_uart:
 181         addruart        r0, r1, r2
 182         mov             r1, #UART_LCR_WLEN8 << 8
 183         str             r1, [r0, #0x10]
 184         str             r3, [r0, #0x24]
 185
 186         mov             pc, lr
 187 ENDPROC(debug_ll_init)