arch/arm/mach-uniphier/clk/dpll-ld4.c

   1 /*
   2  * Copyright (C) 2013-2014 Panasonic Corporation
   3  * Copyright (C) 2015-2016 Socionext Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <linux/errno.h>
  10 #include <linux/io.h>
  11
  12 #include "../init.h"
  13 #include "../sc-regs.h"
  14
  15 #undef DPLL_SSC_RATE_1PER
  16
  17 int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd)
  18 {
  19         unsigned int dram_freq = bd->dram_freq;
  20         u32 tmp;
  21
  22         /*
  23          * Set Frequency
  24          * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
  25          * to FOUT (DPLLCTRL.bit[29:20])
  26          */
  27         tmp = readl(SC_DPLLCTRL);
  28         tmp &= ~0x000f0000;
  29         switch (dram_freq) {
  30         case 1333:
  31                 tmp |= 0x000d0000;
  32                 break;
  33         case 1600:
  34                 tmp |= 0x000c0000;
  35                 break;
  36         default:
  37                 pr_err("Unsupported frequency");
  38                 return -EINVAL;
  39         }
  40
  41 #if defined(DPLL_SSC_RATE_1PER)
  42         tmp &= ~SC_DPLLCTRL_SSC_RATE;
  43 #else
  44         tmp |= SC_DPLLCTRL_SSC_RATE;
  45 #endif
  46         writel(tmp, SC_DPLLCTRL);
  47
  48         tmp = readl(SC_DPLLCTRL2);
  49         tmp |= SC_DPLLCTRL2_NRSTDS;
  50         writel(tmp, SC_DPLLCTRL2);
  51
  52         /* Wait 500 usec until dpll gets stable */
  53         udelay(500);
  54
  55         return 0;
  56 }