arch/arm/mach-uniphier/clk/dpll-sld8.c

   1 /*
   2  * Copyright (C) 2013-2014 Panasonic Corporation
   3  * Copyright (C) 2015-2016 Socionext Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <linux/io.h>
  10
  11 #include "../init.h"
  12 #include "../sc-regs.h"
  13
  14 int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd)
  15 {
  16         u32 tmp;
  17         /*
  18          * Set DPLL SSC parameters for DPLLCTRL3
  19          * [23]    DIVN_TEST    0x1
  20          * [22:16] DIVN         0x50
  21          * [10]    FREFSEL_TEST 0x1
  22          * [9:8]   FREFSEL      0x2
  23          * [4]     ICPD_TEST    0x1
  24          * [3:0]   ICPD         0xb
  25          */
  26         tmp = readl(SC_DPLLCTRL3);
  27         tmp &= ~0x00ff0717;
  28         tmp |= 0x00d0061b;
  29         writel(tmp, SC_DPLLCTRL3);
  30
  31         /*
  32          * Set DPLL SSC parameters for DPLLCTRL
  33          *                    <-1%>          <-2%>
  34          * [29:20] SSC_UPCNT 132 (0x084)    132  (0x084)
  35          * [14:0]  SSC_dK    6335(0x18bf)   12710(0x31a6)
  36          */
  37         tmp = readl(SC_DPLLCTRL);
  38         tmp &= ~0x3ff07fff;
  39 #ifdef DPLL_SSC_RATE_1PER
  40         tmp |= 0x084018bf;
  41 #else
  42         tmp |= 0x084031a6;
  43 #endif
  44         writel(tmp, SC_DPLLCTRL);
  45
  46         /*
  47          * Set DPLL SSC parameters for DPLLCTRL2
  48          * [31:29]  SSC_STEP     0
  49          * [27]     SSC_REG_REF  1
  50          * [26:20]  SSC_M        79     (0x4f)
  51          * [19:0]   SSC_K        964689 (0xeb851)
  52          */
  53         tmp = readl(SC_DPLLCTRL2);
  54         tmp &= ~0xefffffff;
  55         tmp |= 0x0cfeb851;
  56         writel(tmp, SC_DPLLCTRL2);
  57
  58         /* Wait 500 usec until dpll gets stable */
  59         udelay(500);
  60
  61         return 0;
  62 }