arch/arm/mach-uniphier/clk/pll.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2016 Socionext Inc.
   4  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   5  */
   6
   7 #ifndef MACH_PLL_H
   8 #define MACH_PLL_H
   9
  10 #define UNIPHIER_PLL_FREQ_DEFAULT       (0)
  11
  12 void uniphier_ld4_dpll_ssc_en(void);
  13
  14 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
  15                               unsigned int ssc_rate, unsigned int divn);
  16 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
  17 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
  18 int uniphier_ld20_vpll27_init(unsigned long reg_base);
  19 int uniphier_ld20_dspll_init(unsigned long reg_base);
  20
  21 #endif /* MACH_PLL_H */