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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/mach-uniphier/dram/cmd_ddrphy.c
0a5a73d8eea2ec6268adcbde76b6f50637300615
2 * Copyright (C) 2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/sizes.h>
13 #include "../soc-info.h"
14 #include "ddrphy-regs.h"
16 /* Select either decimal or hexadecimal */
18 #define PRINTF_FORMAT "%2d"
20 #define PRINTF_FORMAT "%02x"
25 static unsigned long uniphier_ld4_base
[] = {
31 static unsigned long uniphier_pro4_base
[] = {
37 static unsigned long uniphier_sld8_base
[] = {
43 static u32
read_bdl(struct ddrphy_datx8 __iomem
*dx
, int index
)
45 return (readl(&dx
->bdlr
[index
/ 5]) >> (index
% 5 * 6)) & 0x3f;
48 static void dump_loop(unsigned long *base
,
49 void (*callback
)(struct ddrphy_datx8 __iomem
*))
51 struct ddrphy __iomem
*phy
;
54 for (p
= 0; *base
; base
++, p
++) {
55 phy
= ioremap(*base
, SZ_4K
);
57 for (dx
= 0; dx
< NR_DATX8_PER_DDRPHY
; dx
++) {
58 printf("PHY%dDX%d:", p
, dx
);
59 (*callback
)(&phy
->dx
[dx
]);
67 static void __wbdl_dump(struct ddrphy_datx8 __iomem
*dx
)
71 for (i
= 0; i
< 10; i
++)
72 printf(FS PRINTF_FORMAT
, read_bdl(dx
, i
));
74 printf(FS
"(+" PRINTF_FORMAT
")", readl(&dx
->lcdlr
[1]) & 0xff);
77 static void wbdl_dump(unsigned long *base
)
79 printf("\n--- Write Bit Delay Line ---\n");
80 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
82 dump_loop(base
, &__wbdl_dump
);
85 static void __rbdl_dump(struct ddrphy_datx8 __iomem
*dx
)
89 for (i
= 15; i
< 24; i
++)
90 printf(FS PRINTF_FORMAT
, read_bdl(dx
, i
));
92 printf(FS
"(+" PRINTF_FORMAT
")", (readl(&dx
->lcdlr
[1]) >> 8) & 0xff);
95 static void rbdl_dump(unsigned long *base
)
97 printf("\n--- Read Bit Delay Line ---\n");
98 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
100 dump_loop(base
, &__rbdl_dump
);
103 static void __wld_dump(struct ddrphy_datx8 __iomem
*dx
)
106 u32 lcdlr0
= readl(&dx
->lcdlr
[0]);
107 u32 gtr
= readl(&dx
->gtr
);
109 for (rank
= 0; rank
< 4; rank
++) {
110 u32 wld
= (lcdlr0
>> (8 * rank
)) & 0xff; /* Delay */
111 u32 wlsl
= (gtr
>> (12 + 2 * rank
)) & 0x3; /* System Latency */
113 printf(FS PRINTF_FORMAT
"%sT", wld
,
114 wlsl
== 0 ? "-1" : wlsl
== 1 ? "+0" : "+1");
118 static void wld_dump(unsigned long *base
)
120 printf("\n--- Write Leveling Delay ---\n");
121 printf(" Rank0 Rank1 Rank2 Rank3\n");
123 dump_loop(base
, &__wld_dump
);
126 static void __dqsgd_dump(struct ddrphy_datx8 __iomem
*dx
)
129 u32 lcdlr2
= readl(&dx
->lcdlr
[2]);
130 u32 gtr
= readl(&dx
->gtr
);
132 for (rank
= 0; rank
< 4; rank
++) {
133 u32 dqsgd
= (lcdlr2
>> (8 * rank
)) & 0xff; /* Delay */
134 u32 dgsl
= (gtr
>> (3 * rank
)) & 0x7; /* System Latency */
136 printf(FS PRINTF_FORMAT
"+%dT", dqsgd
, dgsl
);
140 static void dqsgd_dump(unsigned long *base
)
142 printf("\n--- DQS Gating Delay ---\n");
143 printf(" Rank0 Rank1 Rank2 Rank3\n");
145 dump_loop(base
, &__dqsgd_dump
);
148 static void __mdl_dump(struct ddrphy_datx8 __iomem
*dx
)
151 u32 mdl
= readl(&dx
->mdlr
);
152 for (i
= 0; i
< 3; i
++)
153 printf(FS PRINTF_FORMAT
, (mdl
>> (8 * i
)) & 0xff);
156 static void mdl_dump(unsigned long *base
)
158 printf("\n--- Master Delay Line ---\n");
159 printf(" IPRD TPRD MDLD\n");
161 dump_loop(base
, &__mdl_dump
);
164 #define REG_DUMP(x) \
165 { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
166 p - (u32 *)phy, #x, p, readl(p)); }
168 static void reg_dump(unsigned long *base
)
170 struct ddrphy __iomem
*phy
;
173 printf("\n--- DDR PHY registers ---\n");
175 for (p
= 0; *base
; base
++, p
++) {
176 phy
= ioremap(*base
, SZ_4K
);
178 printf("== PHY%d (base: %p) ==\n", p
, phy
);
179 printf(" No: Name : Address : Data\n");
214 static int do_ddr(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
219 switch (uniphier_get_soc_type()) {
220 case SOC_UNIPHIER_LD4
:
221 base
= uniphier_ld4_base
;
223 case SOC_UNIPHIER_PRO4
:
224 base
= uniphier_pro4_base
;
226 case SOC_UNIPHIER_SLD8
:
227 base
= uniphier_sld8_base
;
230 printf("unsupported SoC\n");
231 return CMD_RET_FAILURE
;
237 if (!strcmp(cmd
, "wbdl") || !strcmp(cmd
, "all"))
240 if (!strcmp(cmd
, "rbdl") || !strcmp(cmd
, "all"))
243 if (!strcmp(cmd
, "wld") || !strcmp(cmd
, "all"))
246 if (!strcmp(cmd
, "dqsgd") || !strcmp(cmd
, "all"))
249 if (!strcmp(cmd
, "mdl") || !strcmp(cmd
, "all"))
252 if (!strcmp(cmd
, "reg") || !strcmp(cmd
, "all"))
255 return CMD_RET_SUCCESS
;
260 "UniPhier DDR PHY parameters dumper",
261 "- dump all of the followings\n"
262 "ddr wbdl - dump Write Bit Delay\n"
263 "ddr rbdl - dump Read Bit Delay\n"
264 "ddr wld - dump Write Leveling\n"
265 "ddr dqsgd - dump DQS Gating Delay\n"
266 "ddr mdl - dump Master Delay Line\n"
267 "ddr reg - dump registers\n"