arch/arm/mach-uniphier/dram/ddrphy-regs.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * UniPhier DDR PHY registers
   4  *
   5  * Copyright (C) 2014      Panasonic Corporation
   6  * Copyright (C) 2015-2016 Socionext Inc.
   7  */
   8
   9 #ifndef ARCH_DDRPHY_REGS_H
  10 #define ARCH_DDRPHY_REGS_H
  11
  12 #define PHY_REG_SHIFT           2
  13
  14 #define PHY_RIDR                (0x000 << PHY_REG_SHIFT)
  15 #define PHY_PIR                 (0x001 << PHY_REG_SHIFT)
  16 #define   PHY_PIR_INIT                  BIT(0)  /* Initialization Trigger */
  17 #define   PHY_PIR_ZCAL                  BIT(1)  /* Impedance Calibration */
  18 #define   PHY_PIR_PLLINIT               BIT(4)  /* PLL Initialization */
  19 #define   PHY_PIR_DCAL                  BIT(5)  /* DDL Calibration */
  20 #define   PHY_PIR_PHYRST                BIT(6)  /* PHY Reset */
  21 #define   PHY_PIR_DRAMRST               BIT(7)  /* DRAM Reset */
  22 #define   PHY_PIR_DRAMINIT              BIT(8)  /* DRAM Initialization */
  23 #define   PHY_PIR_WL                    BIT(9)  /* Write Leveling */
  24 #define   PHY_PIR_QSGATE                BIT(10) /* Read DQS Gate Training */
  25 #define   PHY_PIR_WLADJ                 BIT(11) /* Write Leveling Adjust */
  26 #define   PHY_PIR_RDDSKW                BIT(12) /* Read Data Bit Deskew */
  27 #define   PHY_PIR_WRDSKW                BIT(13) /* Write Data Bit Deskew */
  28 #define   PHY_PIR_RDEYE                 BIT(14) /* Read Data Eye Training */
  29 #define   PHY_PIR_WREYE                 BIT(15) /* Write Data Eye Training */
  30 #define   PHY_PIR_LOCKBYP               BIT(28) /* PLL Lock Bypass */
  31 #define   PHY_PIR_DCALBYP               BIT(29) /* DDL Calibration Bypass */
  32 #define   PHY_PIR_ZCALBYP               BIT(30) /* Impedance Calib Bypass */
  33 #define   PHY_PIR_INITBYP               BIT(31) /* Initialization Bypass */
  34 #define PHY_PGCR0               (0x002 << PHY_REG_SHIFT)
  35 #define PHY_PGCR1               (0x003 << PHY_REG_SHIFT)
  36 #define   PHY_PGCR1_INHVT               BIT(26) /* VT Calculation Inhibit */
  37 #define PHY_PGSR0               (0x004 << PHY_REG_SHIFT)
  38 #define   PHY_PGSR0_IDONE               BIT(0)  /* Initialization Done */
  39 #define   PHY_PGSR0_PLDONE              BIT(1)  /* PLL Lock Done */
  40 #define   PHY_PGSR0_DCDONE              BIT(2)  /* DDL Calibration Done */
  41 #define   PHY_PGSR0_ZCDONE              BIT(3)  /* Impedance Calibration Done */
  42 #define   PHY_PGSR0_DIDONE              BIT(4)  /* DRAM Initialization Done */
  43 #define   PHY_PGSR0_WLDONE              BIT(5)  /* Write Leveling Done */
  44 #define   PHY_PGSR0_QSGDONE             BIT(6)  /* DQS Gate Training Done */
  45 #define   PHY_PGSR0_WLADONE             BIT(7)  /* Write Leveling Adjust Done */
  46 #define   PHY_PGSR0_RDDONE              BIT(8)  /* Read Bit Deskew Done */
  47 #define   PHY_PGSR0_WDDONE              BIT(9)  /* Write Bit Deskew Done */
  48 #define   PHY_PGSR0_REDONE              BIT(10) /* Read Eye Training Done */
  49 #define   PHY_PGSR0_WEDONE              BIT(11) /* Write Eye Training Done */
  50 #define   PHY_PGSR0_DIERR               BIT(20) /* DRAM Initialization Error */
  51 #define   PHY_PGSR0_WLERR               BIT(21) /* Write Leveling Error */
  52 #define   PHY_PGSR0_QSGERR              BIT(22) /* DQS Gate Training Error */
  53 #define   PHY_PGSR0_WLAERR              BIT(23) /* Write Leveling Adj Error */
  54 #define   PHY_PGSR0_RDERR               BIT(24) /* Read Bit Deskew Error */
  55 #define   PHY_PGSR0_WDERR               BIT(25) /* Write Bit Deskew Error */
  56 #define   PHY_PGSR0_REERR               BIT(26) /* Read Eye Training Error */
  57 #define   PHY_PGSR0_WEERR               BIT(27) /* Write Eye Training Error */
  58 #define   PHY_PGSR0_DTERR_SHIFT         28      /* Data Training Error Status*/
  59 #define   PHY_PGSR0_DTERR               (7 << (PHY_PGSR0_DTERR_SHIFT))
  60 #define PHY_PGSR1               (0x005 << PHY_REG_SHIFT)
  61 #define   PHY_PGSR1_VTSTOP              BIT(30) /* VT Stop (v3-) */
  62 #define PHY_PLLCR               (0x006 << PHY_REG_SHIFT)
  63 #define PHY_PTR0                (0x007 << PHY_REG_SHIFT)
  64 #define PHY_PTR1                (0x008 << PHY_REG_SHIFT)
  65 #define PHY_PTR2                (0x009 << PHY_REG_SHIFT)
  66 #define PHY_PTR3                (0x00A << PHY_REG_SHIFT)
  67 #define PHY_PTR4                (0x00B << PHY_REG_SHIFT)
  68 #define PHY_ACMDLR              (0x00C << PHY_REG_SHIFT)
  69 #define PHY_ACBDLR              (0x00D << PHY_REG_SHIFT)
  70 #define PHY_ACIOCR              (0x00E << PHY_REG_SHIFT)
  71 #define PHY_DXCCR               (0x00F << PHY_REG_SHIFT)
  72 #define   PHY_DXCCR_DQSRES_OPEN         (0 << 5)
  73 #define   PHY_DXCCR_DQSRES_688_OHM      (1 << 5)
  74 #define   PHY_DXCCR_DQSRES_611_OHM      (2 << 5)
  75 #define   PHY_DXCCR_DQSRES_550_OHM      (3 << 5)
  76 #define   PHY_DXCCR_DQSRES_500_OHM      (4 << 5)
  77 #define   PHY_DXCCR_DQSRES_458_OHM      (5 << 5)
  78 #define   PHY_DXCCR_DQSRES_393_OHM      (6 << 5)
  79 #define   PHY_DXCCR_DQSRES_344_OHM      (7 << 5)
  80 #define   PHY_DXCCR_DQSNRES_OPEN        (0 << 9)
  81 #define   PHY_DXCCR_DQSNRES_688_OHM     (1 << 9)
  82 #define   PHY_DXCCR_DQSNRES_611_OHM     (2 << 9)
  83 #define   PHY_DXCCR_DQSNRES_550_OHM     (3 << 9)
  84 #define   PHY_DXCCR_DQSNRES_500_OHM     (4 << 9)
  85 #define   PHY_DXCCR_DQSNRES_458_OHM     (5 << 9)
  86 #define   PHY_DXCCR_DQSNRES_393_OHM     (6 << 9)
  87 #define   PHY_DXCCR_DQSNRES_344_OHM     (7 << 9)
  88 #define PHY_DSGCR               (0x010 << PHY_REG_SHIFT)
  89 #define PHY_DCR                 (0x011 << PHY_REG_SHIFT)
  90 #define PHY_DTPR0               (0x012 << PHY_REG_SHIFT)
  91 #define PHY_DTPR1               (0x013 << PHY_REG_SHIFT)
  92 #define PHY_DTPR2               (0x014 << PHY_REG_SHIFT)
  93 #define PHY_MR0                 (0x015 << PHY_REG_SHIFT)
  94 #define PHY_MR1                 (0x016 << PHY_REG_SHIFT)
  95 #define PHY_MR2                 (0x017 << PHY_REG_SHIFT)
  96 #define PHY_MR3                 (0x018 << PHY_REG_SHIFT)
  97 #define PHY_ODTCR               (0x019 << PHY_REG_SHIFT)
  98 #define PHY_DTCR                (0x01A << PHY_REG_SHIFT)
  99 #define   PHY_DTCR_DTRANK_SHIFT         4       /* Data Training Rank */
 100 #define   PHY_DTCR_DTRANK_MASK          (0x3 << (PHY_DTCR_DTRANK_SHIFT))
 101 #define   PHY_DTCR_DTMPR                BIT(6)  /* Data Training using MPR */
 102 #define   PHY_DTCR_RANKEN_SHIFT         24      /* Rank Enable */
 103 #define   PHY_DTCR_RANKEN_MASK          (0xf << (PHY_DTCR_RANKEN_SHIFT))
 104 #define PHY_DTAR0               (0x01B << PHY_REG_SHIFT)
 105 #define PHY_DTAR1               (0x01C << PHY_REG_SHIFT)
 106 #define PHY_DTAR2               (0x01D << PHY_REG_SHIFT)
 107 #define PHY_DTAR3               (0x01E << PHY_REG_SHIFT)
 108 #define PHY_DTDR0               (0x01F << PHY_REG_SHIFT)
 109 #define PHY_DTDR1               (0x020 << PHY_REG_SHIFT)
 110 #define PHY_DTEDR0              (0x021 << PHY_REG_SHIFT)
 111 #define PHY_DTEDR1              (0x022 << PHY_REG_SHIFT)
 112 #define PHY_PGCR2               (0x023 << PHY_REG_SHIFT)
 113 #define PHY_GPR0                (0x05E << PHY_REG_SHIFT)
 114 #define PHY_GPR1                (0x05F << PHY_REG_SHIFT)
 115 /* ZQ */
 116 #define PHY_ZQ_BASE             (0x060 << PHY_REG_SHIFT)
 117 #define PHY_ZQ_STRIDE           (0x004 << PHY_REG_SHIFT)
 118 #define PHY_ZQ_CR0              (0x000 << PHY_REG_SHIFT)
 119 #define PHY_ZQ_CR1              (0x001 << PHY_REG_SHIFT)
 120 #define PHY_ZQ_SR0              (0x002 << PHY_REG_SHIFT)
 121 #define PHY_ZQ_SR1              (0x003 << PHY_REG_SHIFT)
 122 /* DATX8 */
 123 #define PHY_DX_BASE             (0x070 << PHY_REG_SHIFT)
 124 #define PHY_DX_STRIDE           (0x010 << PHY_REG_SHIFT)
 125 #define PHY_DX_GCR              (0x000 << PHY_REG_SHIFT)
 126 #define   PHY_DX_GCR_WLRKEN_SHIFT       26              /* Write Level Rank Enable */
 127 #define   PHY_DX_GCR_WLRKEN_MASK        (0xf << (PHY_DX_GCR_WLRKEN_SHIFT))
 128 #define PHY_DX_GSR0             (0x001 << PHY_REG_SHIFT)
 129 #define PHY_DX_GSR1             (0x002 << PHY_REG_SHIFT)
 130 #define PHY_DX_BDLR0            (0x003 << PHY_REG_SHIFT)
 131 #define PHY_DX_BDLR1            (0x004 << PHY_REG_SHIFT)
 132 #define PHY_DX_BDLR2            (0x005 << PHY_REG_SHIFT)
 133 #define PHY_DX_BDLR3            (0x006 << PHY_REG_SHIFT)
 134 #define PHY_DX_BDLR4            (0x007 << PHY_REG_SHIFT)
 135 #define PHY_DX_LCDLR0           (0x008 << PHY_REG_SHIFT)
 136 #define PHY_DX_LCDLR1           (0x009 << PHY_REG_SHIFT)
 137 #define PHY_DX_LCDLR2           (0x00A << PHY_REG_SHIFT)
 138 #define PHY_DX_MDLR             (0x00B << PHY_REG_SHIFT)
 139 #define PHY_DX_GTR              (0x00C << PHY_REG_SHIFT)
 140 #define PHY_DX_GSR2             (0x00D << PHY_REG_SHIFT)
 141
 142 #endif /* ARCH_DDRPHY_REGS_H */