2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
12 #include <linux/errno.h>
13 #include <linux/sizes.h>
18 #define pr_warn(fmt, args...) printf(fmt, ##args)
19 #define pr_err(fmt, args...) printf(fmt, ##args)
21 DECLARE_GLOBAL_DATA_PTR
;
23 struct uniphier_memif_data
{
25 unsigned long sparse_ch1_base
;
29 static const struct uniphier_memif_data uniphier_memif_data
[] = {
31 .soc_id
= UNIPHIER_SLD3_ID
,
32 .sparse_ch1_base
= 0xc0000000,
34 * In fact, SLD3 has DRAM ch2, but the memory regions for ch1
35 * and ch2 overlap, and host cannot get access to them at the
36 * same time. Hide the ch2 from U-Boot.
40 .soc_id
= UNIPHIER_LD4_ID
,
41 .sparse_ch1_base
= 0xc0000000,
44 .soc_id
= UNIPHIER_PRO4_ID
,
45 .sparse_ch1_base
= 0xa0000000,
48 .soc_id
= UNIPHIER_SLD8_ID
,
49 .sparse_ch1_base
= 0xc0000000,
52 .soc_id
= UNIPHIER_PRO5_ID
,
53 .sparse_ch1_base
= 0xc0000000,
56 .soc_id
= UNIPHIER_PXS2_ID
,
57 .sparse_ch1_base
= 0xc0000000,
61 .soc_id
= UNIPHIER_LD6B_ID
,
62 .sparse_ch1_base
= 0xc0000000,
66 .soc_id
= UNIPHIER_LD11_ID
,
67 .sparse_ch1_base
= 0xc0000000,
70 .soc_id
= UNIPHIER_LD20_ID
,
71 .sparse_ch1_base
= 0xc0000000,
75 .soc_id
= UNIPHIER_PXS3_ID
,
76 .sparse_ch1_base
= 0xc0000000,
80 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data
, uniphier_memif_data
)
82 struct uniphier_dram_map
{
87 static int uniphier_memconf_decode(struct uniphier_dram_map
*dram_map
)
89 const struct uniphier_memif_data
*data
;
93 data
= uniphier_get_memif_data();
95 pr_err("unsupported SoC\n");
99 val
= readl(SG_MEMCONF
);
102 dram_map
[0].base
= CONFIG_SYS_SDRAM_BASE
;
104 switch (val
& SG_MEMCONF_CH0_SZ_MASK
) {
105 case SG_MEMCONF_CH0_SZ_64M
:
108 case SG_MEMCONF_CH0_SZ_128M
:
111 case SG_MEMCONF_CH0_SZ_256M
:
114 case SG_MEMCONF_CH0_SZ_512M
:
117 case SG_MEMCONF_CH0_SZ_1G
:
121 pr_err("error: invalid value is set to MEMCONF ch0 size\n");
125 if ((val
& SG_MEMCONF_CH0_NUM_MASK
) == SG_MEMCONF_CH0_NUM_2
)
128 dram_map
[0].size
= size
;
131 dram_map
[1].base
= dram_map
[0].base
+ size
;
133 if (val
& SG_MEMCONF_SPARSEMEM
) {
134 if (dram_map
[1].base
> data
->sparse_ch1_base
) {
135 pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
136 pr_warn("Only ch0 is available\n");
137 dram_map
[1].base
= 0;
141 dram_map
[1].base
= data
->sparse_ch1_base
;
144 switch (val
& SG_MEMCONF_CH1_SZ_MASK
) {
145 case SG_MEMCONF_CH1_SZ_64M
:
148 case SG_MEMCONF_CH1_SZ_128M
:
151 case SG_MEMCONF_CH1_SZ_256M
:
154 case SG_MEMCONF_CH1_SZ_512M
:
157 case SG_MEMCONF_CH1_SZ_1G
:
161 pr_err("error: invalid value is set to MEMCONF ch1 size\n");
165 if ((val
& SG_MEMCONF_CH1_NUM_MASK
) == SG_MEMCONF_CH1_NUM_2
)
168 dram_map
[1].size
= size
;
170 if (!data
->have_ch2
|| val
& SG_MEMCONF_CH2_DISABLE
)
174 dram_map
[2].base
= dram_map
[1].base
+ size
;
176 switch (val
& SG_MEMCONF_CH2_SZ_MASK
) {
177 case SG_MEMCONF_CH2_SZ_64M
:
180 case SG_MEMCONF_CH2_SZ_128M
:
183 case SG_MEMCONF_CH2_SZ_256M
:
186 case SG_MEMCONF_CH2_SZ_512M
:
189 case SG_MEMCONF_CH2_SZ_1G
:
193 pr_err("error: invalid value is set to MEMCONF ch2 size\n");
197 if ((val
& SG_MEMCONF_CH2_NUM_MASK
) == SG_MEMCONF_CH2_NUM_2
)
200 dram_map
[2].size
= size
;
207 struct uniphier_dram_map dram_map
[3] = {};
212 ret
= uniphier_memconf_decode(dram_map
);
216 for (i
= 0; i
< ARRAY_SIZE(dram_map
); i
++) {
218 if (!dram_map
[i
].size
)
222 * U-Boot relocates itself to the tail of the memory region,
223 * but it does not expect sparse memory. We use the first
224 * contiguous chunk here.
226 if (i
> 0 && dram_map
[i
- 1].base
+ dram_map
[i
- 1].size
<
230 gd
->ram_size
+= dram_map
[i
].size
;
236 int dram_init_banksize(void)
238 struct uniphier_dram_map dram_map
[3] = {};
241 uniphier_memconf_decode(dram_map
);
243 for (i
= 0; i
< ARRAY_SIZE(dram_map
); i
++) {
244 if (i
>= ARRAY_SIZE(gd
->bd
->bi_dram
))
247 gd
->bd
->bi_dram
[i
].start
= dram_map
[i
].base
;
248 gd
->bd
->bi_dram
[i
].size
= dram_map
[i
].size
;
254 #ifdef CONFIG_OF_BOARD_SETUP
256 * The DRAM PHY requires 64 byte scratch area in each DRAM channel
257 * for its dynamic PHY training feature.
259 int ft_board_setup(void *fdt
, bd_t
*bd
)
261 unsigned long rsv_addr
;
262 const unsigned long rsv_size
= 64;
265 if (uniphier_get_soc_id() != UNIPHIER_LD20_ID
)
268 for (i
= 0; i
< ARRAY_SIZE(gd
->bd
->bi_dram
); i
++) {
269 if (!gd
->bd
->bi_dram
[i
].size
)
272 rsv_addr
= gd
->bd
->bi_dram
[i
].start
+ gd
->bd
->bi_dram
[i
].size
;
273 rsv_addr
-= rsv_size
;
275 ret
= fdt_add_mem_rsv(fdt
, rsv_addr
, rsv_size
);
279 printf(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n",