]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/mach-uniphier/ph1-ld4/umc_init.c
bbc3dcb3da8b4593e77889ea947a848d0171a880
2 * Copyright (C) 2011-2014 Panasonic Corporation
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/umc-regs.h>
10 #include <asm/arch/ddrphy-regs.h>
12 static void umc_start_ssif(void __iomem
*ssif_base
)
14 writel(0x00000000, ssif_base
+ 0x0000b004);
15 writel(0xffffffff, ssif_base
+ 0x0000c004);
16 writel(0x000fffcf, ssif_base
+ 0x0000c008);
17 writel(0x00000001, ssif_base
+ 0x0000b000);
18 writel(0x00000001, ssif_base
+ 0x0000c000);
19 writel(0x03010101, ssif_base
+ UMC_MDMCHSEL
);
20 writel(0x03010100, ssif_base
+ UMC_DMDCHSEL
);
22 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_FETCH
);
23 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMQUE0
);
24 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMWC0
);
25 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMRC0
);
26 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMQUE1
);
27 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMWC1
);
28 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMRC1
);
29 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_WC
);
30 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_RC
);
31 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_DST
);
33 writel(0x00000001, ssif_base
+ UMC_CPURST
);
34 writel(0x00000001, ssif_base
+ UMC_IDSRST
);
35 writel(0x00000001, ssif_base
+ UMC_IXMRST
);
36 writel(0x00000001, ssif_base
+ UMC_MDMRST
);
37 writel(0x00000001, ssif_base
+ UMC_MDDRST
);
38 writel(0x00000001, ssif_base
+ UMC_SIORST
);
39 writel(0x00000001, ssif_base
+ UMC_VIORST
);
40 writel(0x00000001, ssif_base
+ UMC_FRCRST
);
41 writel(0x00000001, ssif_base
+ UMC_RGLRST
);
42 writel(0x00000001, ssif_base
+ UMC_AIORST
);
43 writel(0x00000001, ssif_base
+ UMC_DMDRST
);
46 static void umc_dramcont_init(void __iomem
*dramcont
, void __iomem
*ca_base
,
50 writel(0x45990b11, dramcont
+ UMC_CMDCTLA
);
51 writel(0x16958924, dramcont
+ UMC_CMDCTLB
);
52 writel(0x5101046A, dramcont
+ UMC_INITCTLA
);
55 writel(0x27028B0A, dramcont
+ UMC_INITCTLB
);
57 writel(0x38028B0A, dramcont
+ UMC_INITCTLB
);
59 writel(0x000FF0FF, dramcont
+ UMC_INITCTLC
);
60 writel(0x00000b51, dramcont
+ UMC_DRMMR0
);
61 } else if (freq
== 1600) {
62 writel(0x36BB0F17, dramcont
+ UMC_CMDCTLA
);
63 writel(0x18C6AA24, dramcont
+ UMC_CMDCTLB
);
64 writel(0x5101387F, dramcont
+ UMC_INITCTLA
);
67 writel(0x2F030D3F, dramcont
+ UMC_INITCTLB
);
69 writel(0x43030D3F, dramcont
+ UMC_INITCTLB
);
71 writel(0x00FF00FF, dramcont
+ UMC_INITCTLC
);
72 writel(0x00000d71, dramcont
+ UMC_DRMMR0
);
75 writel(0x00000006, dramcont
+ UMC_DRMMR1
);
78 writel(0x00000290, dramcont
+ UMC_DRMMR2
);
79 else if (freq
== 1600)
80 writel(0x00000298, dramcont
+ UMC_DRMMR2
);
82 writel(0x00000800, dramcont
+ UMC_DRMMR3
);
86 writel(0x00240512, dramcont
+ UMC_SPCCTLA
);
88 writel(0x00350512, dramcont
+ UMC_SPCCTLA
);
90 writel(0x00ff0006, dramcont
+ UMC_SPCCTLB
);
91 writel(0x000a00ac, dramcont
+ UMC_RDATACTL_D0
);
92 } else if (freq
== 1600) {
94 writel(0x002B0617, dramcont
+ UMC_SPCCTLA
);
96 writel(0x003F0617, dramcont
+ UMC_SPCCTLA
);
98 writel(0x00ff0008, dramcont
+ UMC_SPCCTLB
);
99 writel(0x000c00ae, dramcont
+ UMC_RDATACTL_D0
);
102 writel(0x04060806, dramcont
+ UMC_WDATACTL_D0
);
103 writel(0x04a02000, dramcont
+ UMC_DATASET
);
104 writel(0x00000000, ca_base
+ 0x2300);
105 writel(0x00400020, dramcont
+ UMC_DCCGCTL
);
106 writel(0x00000003, dramcont
+ 0x7000);
107 writel(0x0000000f, dramcont
+ 0x8000);
108 writel(0x000000c3, dramcont
+ 0x8004);
109 writel(0x00000071, dramcont
+ 0x8008);
110 writel(0x0000003b, dramcont
+ UMC_DICGCTLA
);
111 writel(0x020a0808, dramcont
+ UMC_DICGCTLB
);
112 writel(0x00000004, dramcont
+ UMC_FLOWCTLG
);
113 writel(0x80000201, ca_base
+ 0xc20);
114 writel(0x0801e01e, dramcont
+ UMC_FLOWCTLA
);
115 writel(0x00200000, dramcont
+ UMC_FLOWCTLB
);
116 writel(0x00004444, dramcont
+ UMC_FLOWCTLC
);
117 writel(0x200a0a00, dramcont
+ UMC_SPCSETB
);
118 writel(0x00000000, dramcont
+ UMC_SPCSETD
);
119 writel(0x00000520, dramcont
+ UMC_DFICUPDCTLA
);
122 static int umc_init_sub(int freq
, int size_ch0
, int size_ch1
)
124 void __iomem
*ssif_base
= (void __iomem
*)UMC_SSIF_BASE
;
125 void __iomem
*ca_base0
= (void __iomem
*)UMC_CA_BASE(0);
126 void __iomem
*ca_base1
= (void __iomem
*)UMC_CA_BASE(1);
127 void __iomem
*dramcont0
= (void __iomem
*)UMC_DRAMCONT_BASE(0);
128 void __iomem
*dramcont1
= (void __iomem
*)UMC_DRAMCONT_BASE(1);
129 void __iomem
*phy0_0
= (void __iomem
*)DDRPHY_BASE(0, 0);
130 void __iomem
*phy1_0
= (void __iomem
*)DDRPHY_BASE(1, 0);
132 umc_dram_init_start(dramcont0
);
133 umc_dram_init_start(dramcont1
);
134 umc_dram_init_poll(dramcont0
);
135 umc_dram_init_poll(dramcont1
);
137 writel(0x00000101, dramcont0
+ UMC_DIOCTLA
);
139 ddrphy_init(phy0_0
, freq
, size_ch0
);
141 ddrphy_prepare_training(phy0_0
, 0);
142 ddrphy_training(phy0_0
);
144 writel(0x00000101, dramcont1
+ UMC_DIOCTLA
);
146 ddrphy_init(phy1_0
, freq
, size_ch1
);
148 ddrphy_prepare_training(phy1_0
, 1);
149 ddrphy_training(phy1_0
);
151 umc_dramcont_init(dramcont0
, ca_base0
, size_ch0
, freq
);
152 umc_dramcont_init(dramcont1
, ca_base1
, size_ch1
, freq
);
154 umc_start_ssif(ssif_base
);
161 return umc_init_sub(CONFIG_DDR_FREQ
, CONFIG_SDRAM0_SIZE
/ 0x08000000,
162 CONFIG_SDRAM1_SIZE
/ 0x08000000);
165 #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
166 (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
167 CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
170 #error Unsupported DDR configuration.