2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include "../sc-regs.h"
13 #include "../sg-regs.h"
15 #undef DPLL_SSC_RATE_1PER
17 static int dpll_init(unsigned int dram_freq
)
23 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
24 * to FOUT (DPLLCTRL.bit[29:20])
26 tmp
= readl(SC_DPLLCTRL
);
36 pr_err("Unsupported frequency");
40 #if defined(DPLL_SSC_RATE_1PER)
41 tmp
&= ~SC_DPLLCTRL_SSC_RATE
;
43 tmp
|= SC_DPLLCTRL_SSC_RATE
;
45 writel(tmp
, SC_DPLLCTRL
);
47 tmp
= readl(SC_DPLLCTRL2
);
48 tmp
|= SC_DPLLCTRL2_NRSTDS
;
49 writel(tmp
, SC_DPLLCTRL2
);
54 static void upll_init(void)
56 u32 tmp
, clk_mode_upll
, clk_mode_axosel
;
58 tmp
= readl(SG_PINMON0
);
59 clk_mode_upll
= tmp
& SG_PINMON0_CLK_MODE_UPLLSRC_MASK
;
60 clk_mode_axosel
= tmp
& SG_PINMON0_CLK_MODE_AXOSEL_MASK
;
62 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
63 tmp
= readl(SC_UPLLCTRL
);
65 writel(tmp
, SC_UPLLCTRL
);
67 if (clk_mode_upll
== SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT
) {
68 if (clk_mode_axosel
== SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U
||
69 clk_mode_axosel
== SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A
) {
74 /* AXO: default 24.576MHz */
80 writel(tmp
, SC_UPLLCTRL
);
82 /* set 1 to K_LD(UPLLCTRL.bit[27]) */
84 writel(tmp
, SC_UPLLCTRL
);
89 /* set 1 to SNRT(UPLLCTRL.bit[28]) */
91 writel(tmp
, SC_UPLLCTRL
);
94 static void vpll_init(void)
96 u32 tmp
, clk_mode_axosel
;
98 tmp
= readl(SG_PINMON0
);
99 clk_mode_axosel
= tmp
& SG_PINMON0_CLK_MODE_AXOSEL_MASK
;
101 /* set 1 to VPLA27WP and VPLA27WP */
102 tmp
= readl(SC_VPLL27ACTRL
);
104 writel(tmp
, SC_VPLL27ACTRL
);
105 tmp
= readl(SC_VPLL27BCTRL
);
107 writel(tmp
, SC_VPLL27BCTRL
);
109 /* Set 0 to VPLA_K_LD and VPLB_K_LD */
110 tmp
= readl(SC_VPLL27ACTRL3
);
112 writel(tmp
, SC_VPLL27ACTRL3
);
113 tmp
= readl(SC_VPLL27BCTRL3
);
115 writel(tmp
, SC_VPLL27BCTRL3
);
117 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
118 tmp
= readl(SC_VPLL27ACTRL2
);
120 writel(tmp
, SC_VPLL27ACTRL2
);
121 tmp
= readl(SC_VPLL27BCTRL2
);
123 writel(tmp
, SC_VPLL27BCTRL2
);
125 /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
126 tmp
= readl(SC_VPLL27ACTRL2
);
129 writel(tmp
, SC_VPLL27ACTRL2
);
130 tmp
= readl(SC_VPLL27BCTRL2
);
133 writel(tmp
, SC_VPLL27BCTRL2
);
135 if (clk_mode_axosel
== SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U
||
136 clk_mode_axosel
== SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A
) {
138 tmp
= readl(SC_VPLL27ACTRL3
);
141 writel(tmp
, SC_VPLL27ACTRL3
);
142 tmp
= readl(SC_VPLL27BCTRL3
);
145 writel(tmp
, SC_VPLL27BCTRL3
);
147 /* AXO: default 24.576MHz */
148 tmp
= readl(SC_VPLL27ACTRL3
);
151 writel(tmp
, SC_VPLL27ACTRL3
);
152 tmp
= readl(SC_VPLL27BCTRL3
);
155 writel(tmp
, SC_VPLL27BCTRL3
);
158 /* Set 1 to VPLA_K_LD and VPLB_K_LD */
159 tmp
= readl(SC_VPLL27ACTRL3
);
161 writel(tmp
, SC_VPLL27ACTRL3
);
162 tmp
= readl(SC_VPLL27BCTRL3
);
164 writel(tmp
, SC_VPLL27BCTRL3
);
169 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
170 tmp
= readl(SC_VPLL27ACTRL2
);
172 writel(tmp
, SC_VPLL27ACTRL2
);
173 tmp
= readl(SC_VPLL27BCTRL2
);
175 writel(tmp
, SC_VPLL27BCTRL2
);
177 /* set 0 to VPLA27WP and VPLA27WP */
178 tmp
= readl(SC_VPLL27ACTRL
);
180 writel(tmp
, SC_VPLL27ACTRL
);
181 tmp
= readl(SC_VPLL27BCTRL
);
183 writel(tmp
, SC_VPLL27BCTRL
);
186 int ph1_ld4_pll_init(const struct uniphier_board_data
*bd
)
190 ret
= dpll_init(bd
->dram_freq
);
197 * Wait 500 usec until dpll get stable
198 * We wait 10 usec in upll_init() and vpll_init()
199 * so 20 usec can be saved here.