2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <mach/init.h>
11 #include <mach/sc-regs.h>
12 #include <mach/sg-regs.h>
14 #undef DPLL_SSC_RATE_1PER
16 static int dpll_init(unsigned int dram_freq
)
22 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
23 * to FOUT ( DPLLCTRL.bit[29:20] )
25 tmp
= readl(SC_DPLLCTRL
);
35 pr_err("Unsupported frequency");
41 * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
43 #if defined(DPLL_SSC_RATE_1PER)
48 writel(tmp
, SC_DPLLCTRL
);
50 tmp
= readl(SC_DPLLCTRL2
);
51 tmp
|= SC_DPLLCTRL2_NRSTDS
;
52 writel(tmp
, SC_DPLLCTRL2
);
57 static void vpll_init(void)
59 u32 tmp
, clk_mode_axosel
;
61 /* Set VPLL27A & VPLL27B */
62 tmp
= readl(SG_PINMON0
);
63 clk_mode_axosel
= tmp
& SG_PINMON0_CLK_MODE_AXOSEL_MASK
;
65 /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
66 if (clk_mode_axosel
== SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ
||
67 clk_mode_axosel
== SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ
)
70 /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
71 tmp
= readl(SC_VPLL27ACTRL
);
73 writel(tmp
, SC_VPLL27ACTRL
);
74 tmp
= readl(SC_VPLL27BCTRL
);
76 writel(tmp
, SC_VPLL27BCTRL
);
78 /* Unset VPLA_K_LD and VPLB_K_LD bit */
79 tmp
= readl(SC_VPLL27ACTRL3
);
81 writel(tmp
, SC_VPLL27ACTRL3
);
82 tmp
= readl(SC_VPLL27BCTRL3
);
84 writel(tmp
, SC_VPLL27BCTRL3
);
86 /* Set VPLA_M and VPLB_M to 0x20 */
87 tmp
= readl(SC_VPLL27ACTRL2
);
90 writel(tmp
, SC_VPLL27ACTRL2
);
91 tmp
= readl(SC_VPLL27BCTRL2
);
94 writel(tmp
, SC_VPLL27BCTRL2
);
96 if (clk_mode_axosel
== SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ
||
97 clk_mode_axosel
== SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ
) {
98 /* Set VPLA_K and VPLB_K for AXO: 25MHz */
99 tmp
= readl(SC_VPLL27ACTRL3
);
102 writel(tmp
, SC_VPLL27ACTRL3
);
103 tmp
= readl(SC_VPLL27BCTRL3
);
106 writel(tmp
, SC_VPLL27BCTRL3
);
108 /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
109 tmp
= readl(SC_VPLL27ACTRL3
);
112 writel(tmp
, SC_VPLL27ACTRL3
);
113 tmp
= readl(SC_VPLL27BCTRL3
);
116 writel(tmp
, SC_VPLL27BCTRL3
);
122 /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
123 tmp
= readl(SC_VPLL27ACTRL3
);
125 writel(tmp
, SC_VPLL27ACTRL3
);
126 tmp
= readl(SC_VPLL27BCTRL3
);
128 writel(tmp
, SC_VPLL27BCTRL3
);
130 /* Unset VPLA_SNRST and VPLB_SNRST bit */
131 tmp
= readl(SC_VPLL27ACTRL2
);
133 writel(tmp
, SC_VPLL27ACTRL2
);
134 tmp
= readl(SC_VPLL27BCTRL2
);
136 writel(tmp
, SC_VPLL27BCTRL2
);
138 /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
139 tmp
= readl(SC_VPLL27ACTRL
);
141 writel(tmp
, SC_VPLL27ACTRL
);
142 tmp
= readl(SC_VPLL27BCTRL
);
144 writel(tmp
, SC_VPLL27BCTRL
);
147 int ph1_pro4_pll_init(const struct uniphier_board_data
*bd
)
151 ret
= dpll_init(bd
->dram_freq
);
157 * Wait 500 usec until dpll get stable
158 * We wait 1 usec in vpll_init() so 1 usec can be saved here.