arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c

   1 /*
   2  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/io.h>
   9
  10 #include "../init.h"
  11 #include "../sg-regs.h"
  12 #include "sbc-regs.h"
  13
  14 int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
  15 {
  16         /* only address/data multiplex mode is supported */
  17
  18         /*
  19          * Only CS1 is connected to support card.
  20          * BKSZ[1:0] should be set to "01".
  21          */
  22         writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
  23         writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
  24         writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
  25
  26         if (boot_is_swapped()) {
  27                 /*
  28                  * Boot Swap On: boot from external NOR/SRAM
  29                  * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
  30                  *
  31                  * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
  32                  * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
  33                  */
  34                 writel(0x0000bc01, SBBASE0);
  35         } else {
  36                 /*
  37                  * Boot Swap Off: boot from mask ROM
  38                  * 0x40000000-0x41ffffff: mask ROM
  39                  * 0x42000000-0x43efffff: memory bank (31MB)
  40                  * 0x43f00000-0x43ffffff: peripherals (1MB)
  41                  */
  42                 writel(0x0000be01, SBBASE0); /* dummy */
  43                 writel(0x0200be01, SBBASE1);
  44         }
  45
  46         sg_set_pinsel(99, 1, 4, 4);     /* GPIO26 -> EA24 */
  47
  48         return 0;
  49 }