arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c

   1 /*
   2  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/io.h>
   9 #include <mach/init.h>
  10 #include <mach/sbc-regs.h>
  11 #include <mach/sg-regs.h>
  12
  13 int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
  14 {
  15         /* only address/data multiplex mode is supported */
  16
  17         /*
  18          * Only CS1 is connected to support card.
  19          * BKSZ[1:0] should be set to "01".
  20          */
  21         writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
  22         writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
  23         writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
  24
  25         if (boot_is_swapped()) {
  26                 /*
  27                  * Boot Swap On: boot from external NOR/SRAM
  28                  * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
  29                  *
  30                  * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
  31                  * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
  32                  */
  33                 writel(0x0000bc01, SBBASE0);
  34         } else {
  35                 /*
  36                  * Boot Swap Off: boot from mask ROM
  37                  * 0x40000000-0x41ffffff: mask ROM
  38                  * 0x42000000-0x43efffff: memory bank (31MB)
  39                  * 0x43f00000-0x43ffffff: peripherals (1MB)
  40                  */
  41                 writel(0x0000be01, SBBASE0); /* dummy */
  42                 writel(0x0200be01, SBBASE1);
  43         }
  44
  45         sg_set_pinsel(99, 1, 4, 4);     /* GPIO26 -> EA24 */
  46
  47         return 0;
  48 }