2 * linux/arch/arm/mach-versatile/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29 #include <linux/amba/pl061.h>
30 #include <linux/amba/mmci.h>
31 #include <linux/clocksource.h>
32 #include <linux/clockchips.h>
33 #include <linux/cnt32_to_63.h>
35 #include <linux/gfp.h>
37 #include <asm/clkdev.h>
38 #include <asm/system.h>
39 #include <mach/hardware.h>
42 #include <asm/hardware/arm_timer.h>
43 #include <asm/hardware/icst307.h>
44 #include <asm/hardware/vic.h>
45 #include <asm/mach-types.h>
47 #include <asm/mach/arch.h>
48 #include <asm/mach/flash.h>
49 #include <asm/mach/irq.h>
50 #include <asm/mach/time.h>
51 #include <asm/mach/map.h>
57 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
60 * Setup a VA for the Versatile Vectored Interrupt Controller.
62 #define __io_address(n) __io(IO_ADDRESS(n))
63 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
64 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
66 static void sic_mask_irq(unsigned int irq
)
69 writel(1 << irq
, VA_SIC_BASE
+ SIC_IRQ_ENABLE_CLEAR
);
72 static void sic_unmask_irq(unsigned int irq
)
75 writel(1 << irq
, VA_SIC_BASE
+ SIC_IRQ_ENABLE_SET
);
78 static struct irq_chip sic_chip
= {
82 .unmask
= sic_unmask_irq
,
86 sic_handle_irq(unsigned int irq
, struct irq_desc
*desc
)
88 unsigned long status
= readl(VA_SIC_BASE
+ SIC_IRQ_STATUS
);
91 do_bad_IRQ(irq
, desc
);
96 irq
= ffs(status
) - 1;
97 status
&= ~(1 << irq
);
101 generic_handle_irq(irq
);
106 #define IRQ_MMCI0A IRQ_VICSOURCE22
107 #define IRQ_AACI IRQ_VICSOURCE24
108 #define IRQ_ETH IRQ_VICSOURCE25
109 #define PIC_MASK 0xFFD00000
111 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
112 #define IRQ_AACI IRQ_SIC_AACI
113 #define IRQ_ETH IRQ_SIC_ETH
117 void __init
versatile_init_irq(void)
121 vic_init(VA_VIC_BASE
, IRQ_VIC_START
, ~0, 0);
123 set_irq_chained_handler(IRQ_VICSOURCE31
, sic_handle_irq
);
125 /* Do second interrupt controller */
126 writel(~0, VA_SIC_BASE
+ SIC_IRQ_ENABLE_CLEAR
);
128 for (i
= IRQ_SIC_START
; i
<= IRQ_SIC_END
; i
++) {
129 if ((PIC_MASK
& (1 << (i
- IRQ_SIC_START
))) == 0) {
130 set_irq_chip(i
, &sic_chip
);
131 set_irq_handler(i
, handle_level_irq
);
132 set_irq_flags(i
, IRQF_VALID
| IRQF_PROBE
);
137 * Interrupts on secondary controller from 0 to 8 are routed to
139 * Interrupts from 21 to 31 are routed directly to the VIC on
140 * the corresponding number on primary controller. This is controlled
141 * by setting PIC_ENABLEx.
143 writel(PIC_MASK
, VA_SIC_BASE
+ SIC_INT_PIC_ENABLE
);
146 static struct map_desc versatile_io_desc
[] __initdata
= {
148 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE
),
149 .pfn
= __phys_to_pfn(VERSATILE_SYS_BASE
),
153 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE
),
154 .pfn
= __phys_to_pfn(VERSATILE_SIC_BASE
),
158 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE
),
159 .pfn
= __phys_to_pfn(VERSATILE_VIC_BASE
),
163 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE
),
164 .pfn
= __phys_to_pfn(VERSATILE_SCTL_BASE
),
168 #ifdef CONFIG_MACH_VERSATILE_AB
170 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE
),
171 .pfn
= __phys_to_pfn(VERSATILE_GPIO0_BASE
),
175 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE
),
176 .pfn
= __phys_to_pfn(VERSATILE_IB2_BASE
),
181 #ifdef CONFIG_DEBUG_LL
183 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE
),
184 .pfn
= __phys_to_pfn(VERSATILE_UART0_BASE
),
191 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE
),
192 .pfn
= __phys_to_pfn(VERSATILE_PCI_CORE_BASE
),
196 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE
,
197 .pfn
= __phys_to_pfn(VERSATILE_PCI_BASE
),
198 .length
= VERSATILE_PCI_BASE_SIZE
,
201 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE
,
202 .pfn
= __phys_to_pfn(VERSATILE_PCI_CFG_BASE
),
203 .length
= VERSATILE_PCI_CFG_BASE_SIZE
,
208 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0
,
209 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE0
),
213 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1
,
214 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE1
),
218 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2
,
219 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE2
),
227 void __init
versatile_map_io(void)
229 iotable_init(versatile_io_desc
, ARRAY_SIZE(versatile_io_desc
));
232 #define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
235 * This is the Versatile sched_clock implementation. This has
236 * a resolution of 41.7ns, and a maximum value of about 35583 days.
238 * The return value is guaranteed to be monotonic in that range as
239 * long as there is always less than 89 seconds between successive
240 * calls to this function.
242 unsigned long long sched_clock(void)
244 unsigned long long v
= cnt32_to_63(readl(VERSATILE_REFCOUNTER
));
246 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
254 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
256 static int versatile_flash_init(void)
260 val
= __raw_readl(VERSATILE_FLASHCTRL
);
261 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
262 __raw_writel(val
, VERSATILE_FLASHCTRL
);
267 static void versatile_flash_exit(void)
271 val
= __raw_readl(VERSATILE_FLASHCTRL
);
272 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
273 __raw_writel(val
, VERSATILE_FLASHCTRL
);
276 static void versatile_flash_set_vpp(int on
)
280 val
= __raw_readl(VERSATILE_FLASHCTRL
);
282 val
|= VERSATILE_FLASHPROG_FLVPPEN
;
284 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
285 __raw_writel(val
, VERSATILE_FLASHCTRL
);
288 static struct flash_platform_data versatile_flash_data
= {
289 .map_name
= "cfi_probe",
291 .init
= versatile_flash_init
,
292 .exit
= versatile_flash_exit
,
293 .set_vpp
= versatile_flash_set_vpp
,
296 static struct resource versatile_flash_resource
= {
297 .start
= VERSATILE_FLASH_BASE
,
298 .end
= VERSATILE_FLASH_BASE
+ VERSATILE_FLASH_SIZE
- 1,
299 .flags
= IORESOURCE_MEM
,
302 static struct platform_device versatile_flash_device
= {
306 .platform_data
= &versatile_flash_data
,
309 .resource
= &versatile_flash_resource
,
312 static struct resource smc91x_resources
[] = {
314 .start
= VERSATILE_ETH_BASE
,
315 .end
= VERSATILE_ETH_BASE
+ SZ_64K
- 1,
316 .flags
= IORESOURCE_MEM
,
321 .flags
= IORESOURCE_IRQ
,
325 static struct platform_device smc91x_device
= {
328 .num_resources
= ARRAY_SIZE(smc91x_resources
),
329 .resource
= smc91x_resources
,
332 static struct resource versatile_i2c_resource
= {
333 .start
= VERSATILE_I2C_BASE
,
334 .end
= VERSATILE_I2C_BASE
+ SZ_4K
- 1,
335 .flags
= IORESOURCE_MEM
,
338 static struct platform_device versatile_i2c_device
= {
339 .name
= "versatile-i2c",
342 .resource
= &versatile_i2c_resource
,
345 static struct i2c_board_info versatile_i2c_board_info
[] = {
347 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
351 static int __init
versatile_i2c_init(void)
353 return i2c_register_board_info(0, versatile_i2c_board_info
,
354 ARRAY_SIZE(versatile_i2c_board_info
));
356 arch_initcall(versatile_i2c_init
);
358 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
360 unsigned int mmc_status(struct device
*dev
)
362 struct amba_device
*adev
= container_of(dev
, struct amba_device
, dev
);
365 if (adev
->res
.start
== VERSATILE_MMCI0_BASE
)
370 return readl(VERSATILE_SYSMCI
) & mask
;
373 static struct mmci_platform_data mmc0_plat_data
= {
374 .ocr_mask
= MMC_VDD_32_33
|MMC_VDD_33_34
,
375 .status
= mmc_status
,
383 static const struct icst307_params versatile_oscvco_params
= {
392 static void versatile_oscvco_set(struct clk
*clk
, struct icst307_vco vco
)
394 void __iomem
*sys
= __io_address(VERSATILE_SYS_BASE
);
395 void __iomem
*sys_lock
= sys
+ VERSATILE_SYS_LOCK_OFFSET
;
398 val
= readl(sys
+ clk
->oscoff
) & ~0x7ffff;
399 val
|= vco
.v
| (vco
.r
<< 9) | (vco
.s
<< 16);
401 writel(0xa05f, sys_lock
);
402 writel(val
, sys
+ clk
->oscoff
);
406 static struct clk osc4_clk
= {
407 .params
= &versatile_oscvco_params
,
408 .oscoff
= VERSATILE_SYS_OSCCLCD_OFFSET
,
409 .setvco
= versatile_oscvco_set
,
413 * These are fixed clocks.
415 static struct clk ref24_clk
= {
419 static struct clk_lookup lookups
[] = {
453 #define SYS_CLCD_MODE_MASK (3 << 0)
454 #define SYS_CLCD_MODE_888 (0 << 0)
455 #define SYS_CLCD_MODE_5551 (1 << 0)
456 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
457 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
458 #define SYS_CLCD_NLCDIOON (1 << 2)
459 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
460 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
461 #define SYS_CLCD_ID_MASK (0x1f << 8)
462 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
463 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
464 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
465 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
466 #define SYS_CLCD_ID_VGA (0x1f << 8)
468 static struct clcd_panel vga
= {
482 .vmode
= FB_VMODE_NONINTERLACED
,
486 .tim2
= TIM2_BCD
| TIM2_IPC
,
487 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
491 static struct clcd_panel sanyo_3_8_in
= {
493 .name
= "Sanyo QVGA",
505 .vmode
= FB_VMODE_NONINTERLACED
,
510 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
514 static struct clcd_panel sanyo_2_5_in
= {
516 .name
= "Sanyo QVGA Portrait",
527 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
528 .vmode
= FB_VMODE_NONINTERLACED
,
532 .tim2
= TIM2_IVS
| TIM2_IHS
| TIM2_IPC
,
533 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
537 static struct clcd_panel epson_2_2_in
= {
539 .name
= "Epson QCIF",
551 .vmode
= FB_VMODE_NONINTERLACED
,
555 .tim2
= TIM2_BCD
| TIM2_IPC
,
556 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
561 * Detect which LCD panel is connected, and return the appropriate
562 * clcd_panel structure. Note: we do not have any information on
563 * the required timings for the 8.4in panel, so we presently assume
566 static struct clcd_panel
*versatile_clcd_panel(void)
568 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
569 struct clcd_panel
*panel
= &vga
;
572 val
= readl(sys_clcd
) & SYS_CLCD_ID_MASK
;
573 if (val
== SYS_CLCD_ID_SANYO_3_8
)
574 panel
= &sanyo_3_8_in
;
575 else if (val
== SYS_CLCD_ID_SANYO_2_5
)
576 panel
= &sanyo_2_5_in
;
577 else if (val
== SYS_CLCD_ID_EPSON_2_2
)
578 panel
= &epson_2_2_in
;
579 else if (val
== SYS_CLCD_ID_VGA
)
582 printk(KERN_ERR
"CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
591 * Disable all display connectors on the interface module.
593 static void versatile_clcd_disable(struct clcd_fb
*fb
)
595 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
598 val
= readl(sys_clcd
);
599 val
&= ~SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
600 writel(val
, sys_clcd
);
602 #ifdef CONFIG_MACH_VERSATILE_AB
604 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
606 if (machine_is_versatile_ab() && fb
->panel
== &sanyo_2_5_in
) {
607 void __iomem
*versatile_ib2_ctrl
= __io_address(VERSATILE_IB2_CTRL
);
610 ctrl
= readl(versatile_ib2_ctrl
);
612 writel(ctrl
, versatile_ib2_ctrl
);
618 * Enable the relevant connector on the interface module.
620 static void versatile_clcd_enable(struct clcd_fb
*fb
)
622 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
625 val
= readl(sys_clcd
);
626 val
&= ~SYS_CLCD_MODE_MASK
;
628 switch (fb
->fb
.var
.green
.length
) {
630 val
|= SYS_CLCD_MODE_5551
;
633 val
|= SYS_CLCD_MODE_565_RLSB
;
636 val
|= SYS_CLCD_MODE_888
;
643 writel(val
, sys_clcd
);
646 * And now enable the PSUs
648 val
|= SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
649 writel(val
, sys_clcd
);
651 #ifdef CONFIG_MACH_VERSATILE_AB
653 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
655 if (machine_is_versatile_ab() && fb
->panel
== &sanyo_2_5_in
) {
656 void __iomem
*versatile_ib2_ctrl
= __io_address(VERSATILE_IB2_CTRL
);
659 ctrl
= readl(versatile_ib2_ctrl
);
661 writel(ctrl
, versatile_ib2_ctrl
);
666 static unsigned long framesize
= SZ_1M
;
668 static int versatile_clcd_setup(struct clcd_fb
*fb
)
672 fb
->panel
= versatile_clcd_panel();
674 fb
->fb
.screen_base
= dma_alloc_writecombine(&fb
->dev
->dev
, framesize
,
676 if (!fb
->fb
.screen_base
) {
677 printk(KERN_ERR
"CLCD: unable to map framebuffer\n");
681 fb
->fb
.fix
.smem_start
= dma
;
682 fb
->fb
.fix
.smem_len
= framesize
;
687 static int versatile_clcd_mmap(struct clcd_fb
*fb
, struct vm_area_struct
*vma
)
689 return dma_mmap_writecombine(&fb
->dev
->dev
, vma
,
691 fb
->fb
.fix
.smem_start
,
692 fb
->fb
.fix
.smem_len
);
695 static void versatile_clcd_remove(struct clcd_fb
*fb
)
697 dma_free_writecombine(&fb
->dev
->dev
, fb
->fb
.fix
.smem_len
,
698 fb
->fb
.screen_base
, fb
->fb
.fix
.smem_start
);
701 static struct clcd_board clcd_plat_data
= {
703 .check
= clcdfb_check
,
704 .decode
= clcdfb_decode
,
705 .disable
= versatile_clcd_disable
,
706 .enable
= versatile_clcd_enable
,
707 .setup
= versatile_clcd_setup
,
708 .mmap
= versatile_clcd_mmap
,
709 .remove
= versatile_clcd_remove
,
712 static struct pl061_platform_data gpio0_plat_data
= {
714 .irq_base
= IRQ_GPIO0_START
,
717 static struct pl061_platform_data gpio1_plat_data
= {
719 .irq_base
= IRQ_GPIO1_START
,
722 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
723 #define AACI_DMA { 0x80, 0x81 }
724 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
725 #define MMCI0_DMA { 0x84, 0 }
726 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
727 #define KMI0_DMA { 0, 0 }
728 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
729 #define KMI1_DMA { 0, 0 }
732 * These devices are connected directly to the multi-layer AHB switch
734 #define SMC_IRQ { NO_IRQ, NO_IRQ }
735 #define SMC_DMA { 0, 0 }
736 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
737 #define MPMC_DMA { 0, 0 }
738 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
739 #define CLCD_DMA { 0, 0 }
740 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
741 #define DMAC_DMA { 0, 0 }
744 * These devices are connected via the core APB bridge
746 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
747 #define SCTL_DMA { 0, 0 }
748 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
749 #define WATCHDOG_DMA { 0, 0 }
750 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
751 #define GPIO0_DMA { 0, 0 }
752 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
753 #define GPIO1_DMA { 0, 0 }
754 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
755 #define RTC_DMA { 0, 0 }
758 * These devices are connected via the DMA APB bridge
760 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
761 #define SCI_DMA { 7, 6 }
762 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
763 #define UART0_DMA { 15, 14 }
764 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
765 #define UART1_DMA { 13, 12 }
766 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
767 #define UART2_DMA { 11, 10 }
768 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
769 #define SSP_DMA { 9, 8 }
771 /* FPGA Primecells */
772 AMBA_DEVICE(aaci
, "fpga:04", AACI
, NULL
);
773 AMBA_DEVICE(mmc0
, "fpga:05", MMCI0
, &mmc0_plat_data
);
774 AMBA_DEVICE(kmi0
, "fpga:06", KMI0
, NULL
);
775 AMBA_DEVICE(kmi1
, "fpga:07", KMI1
, NULL
);
777 /* DevChip Primecells */
778 AMBA_DEVICE(smc
, "dev:00", SMC
, NULL
);
779 AMBA_DEVICE(mpmc
, "dev:10", MPMC
, NULL
);
780 AMBA_DEVICE(clcd
, "dev:20", CLCD
, &clcd_plat_data
);
781 AMBA_DEVICE(dmac
, "dev:30", DMAC
, NULL
);
782 AMBA_DEVICE(sctl
, "dev:e0", SCTL
, NULL
);
783 AMBA_DEVICE(wdog
, "dev:e1", WATCHDOG
, NULL
);
784 AMBA_DEVICE(gpio0
, "dev:e4", GPIO0
, &gpio0_plat_data
);
785 AMBA_DEVICE(gpio1
, "dev:e5", GPIO1
, &gpio1_plat_data
);
786 AMBA_DEVICE(rtc
, "dev:e8", RTC
, NULL
);
787 AMBA_DEVICE(sci0
, "dev:f0", SCI
, NULL
);
788 AMBA_DEVICE(uart0
, "dev:f1", UART0
, NULL
);
789 AMBA_DEVICE(uart1
, "dev:f2", UART1
, NULL
);
790 AMBA_DEVICE(uart2
, "dev:f3", UART2
, NULL
);
791 AMBA_DEVICE(ssp0
, "dev:f4", SSP
, NULL
);
793 static struct amba_device
*amba_devs
[] __initdata
= {
815 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
817 static void versatile_leds_event(led_event_t ledevt
)
822 local_irq_save(flags
);
823 val
= readl(VA_LEDS_BASE
);
827 val
= val
& ~VERSATILE_SYS_LED0
;
831 val
= val
| VERSATILE_SYS_LED0
;
835 val
= val
^ VERSATILE_SYS_LED1
;
846 writel(val
, VA_LEDS_BASE
);
847 local_irq_restore(flags
);
849 #endif /* CONFIG_LEDS */
851 void __init
versatile_init(void)
855 clkdev_add_table(lookups
, ARRAY_SIZE(lookups
));
857 platform_device_register(&versatile_flash_device
);
858 platform_device_register(&versatile_i2c_device
);
859 platform_device_register(&smc91x_device
);
861 for (i
= 0; i
< ARRAY_SIZE(amba_devs
); i
++) {
862 struct amba_device
*d
= amba_devs
[i
];
863 amba_device_register(d
, &iomem_resource
);
867 leds_event
= versatile_leds_event
;
872 * Where is the timer (VA)?
874 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
875 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
876 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
877 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
878 #define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
881 * How long is the timer interval?
883 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
884 #if TIMER_INTERVAL >= 0x100000
885 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
886 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
887 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
888 #elif TIMER_INTERVAL >= 0x10000
889 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
890 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
891 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
893 #define TIMER_RELOAD (TIMER_INTERVAL)
894 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
895 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
898 static void timer_set_mode(enum clock_event_mode mode
,
899 struct clock_event_device
*clk
)
904 case CLOCK_EVT_MODE_PERIODIC
:
905 writel(TIMER_RELOAD
, TIMER0_VA_BASE
+ TIMER_LOAD
);
907 ctrl
= TIMER_CTRL_PERIODIC
;
908 ctrl
|= TIMER_CTRL_32BIT
| TIMER_CTRL_IE
| TIMER_CTRL_ENABLE
;
910 case CLOCK_EVT_MODE_ONESHOT
:
911 /* period set, and timer enabled in 'next_event' hook */
912 ctrl
= TIMER_CTRL_ONESHOT
;
913 ctrl
|= TIMER_CTRL_32BIT
| TIMER_CTRL_IE
;
915 case CLOCK_EVT_MODE_UNUSED
:
916 case CLOCK_EVT_MODE_SHUTDOWN
:
921 writel(ctrl
, TIMER0_VA_BASE
+ TIMER_CTRL
);
924 static int timer_set_next_event(unsigned long evt
,
925 struct clock_event_device
*unused
)
927 unsigned long ctrl
= readl(TIMER0_VA_BASE
+ TIMER_CTRL
);
929 writel(evt
, TIMER0_VA_BASE
+ TIMER_LOAD
);
930 writel(ctrl
| TIMER_CTRL_ENABLE
, TIMER0_VA_BASE
+ TIMER_CTRL
);
935 static struct clock_event_device timer0_clockevent
= {
938 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
939 .set_mode
= timer_set_mode
,
940 .set_next_event
= timer_set_next_event
,
944 * IRQ handler for the timer
946 static irqreturn_t
versatile_timer_interrupt(int irq
, void *dev_id
)
948 struct clock_event_device
*evt
= &timer0_clockevent
;
950 writel(1, TIMER0_VA_BASE
+ TIMER_INTCLR
);
952 evt
->event_handler(evt
);
957 static struct irqaction versatile_timer_irq
= {
958 .name
= "Versatile Timer Tick",
959 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
960 .handler
= versatile_timer_interrupt
,
963 static cycle_t
versatile_get_cycles(struct clocksource
*cs
)
965 return ~readl(TIMER3_VA_BASE
+ TIMER_VALUE
);
968 static struct clocksource clocksource_versatile
= {
971 .read
= versatile_get_cycles
,
972 .mask
= CLOCKSOURCE_MASK(32),
974 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
977 static int __init
versatile_clocksource_init(void)
979 /* setup timer3 as free-running clocksource */
980 writel(0, TIMER3_VA_BASE
+ TIMER_CTRL
);
981 writel(0xffffffff, TIMER3_VA_BASE
+ TIMER_LOAD
);
982 writel(0xffffffff, TIMER3_VA_BASE
+ TIMER_VALUE
);
983 writel(TIMER_CTRL_32BIT
| TIMER_CTRL_ENABLE
| TIMER_CTRL_PERIODIC
,
984 TIMER3_VA_BASE
+ TIMER_CTRL
);
986 clocksource_versatile
.mult
=
987 clocksource_khz2mult(1000, clocksource_versatile
.shift
);
988 clocksource_register(&clocksource_versatile
);
994 * Set up timer interrupt, and return the current time in seconds.
996 static void __init
versatile_timer_init(void)
1001 * set clock frequency:
1002 * VERSATILE_REFCLK is 32KHz
1003 * VERSATILE_TIMCLK is 1MHz
1005 val
= readl(__io_address(VERSATILE_SCTL_BASE
));
1006 writel((VERSATILE_TIMCLK
<< VERSATILE_TIMER1_EnSel
) |
1007 (VERSATILE_TIMCLK
<< VERSATILE_TIMER2_EnSel
) |
1008 (VERSATILE_TIMCLK
<< VERSATILE_TIMER3_EnSel
) |
1009 (VERSATILE_TIMCLK
<< VERSATILE_TIMER4_EnSel
) | val
,
1010 __io_address(VERSATILE_SCTL_BASE
));
1013 * Initialise to a known state (all timers off)
1015 writel(0, TIMER0_VA_BASE
+ TIMER_CTRL
);
1016 writel(0, TIMER1_VA_BASE
+ TIMER_CTRL
);
1017 writel(0, TIMER2_VA_BASE
+ TIMER_CTRL
);
1018 writel(0, TIMER3_VA_BASE
+ TIMER_CTRL
);
1021 * Make irqs happen for the system timer
1023 setup_irq(IRQ_TIMERINT0_1
, &versatile_timer_irq
);
1025 versatile_clocksource_init();
1027 timer0_clockevent
.mult
=
1028 div_sc(1000000, NSEC_PER_SEC
, timer0_clockevent
.shift
);
1029 timer0_clockevent
.max_delta_ns
=
1030 clockevent_delta2ns(0xffffffff, &timer0_clockevent
);
1031 timer0_clockevent
.min_delta_ns
=
1032 clockevent_delta2ns(0xf, &timer0_clockevent
);
1034 timer0_clockevent
.cpumask
= cpumask_of(0);
1035 clockevents_register_device(&timer0_clockevent
);
1038 struct sys_timer versatile_timer
= {
1039 .init
= versatile_timer_init
,