arch/arm/mach-zynq/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
   4  * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
   5  */
   6 #include <common.h>
   7 #include <zynqpl.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/clk.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/ps7_init_gpl.h>
  12 #include <asm/arch/sys_proto.h>
  13
  14 #define ZYNQ_SILICON_VER_MASK   0xF0000000
  15 #define ZYNQ_SILICON_VER_SHIFT  28
  16
  17 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  18     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  19 xilinx_desc fpga = {
  20         .family = xilinx_zynq,
  21         .iface = devcfg,
  22         .operations = &zynq_op,
  23 };
  24 #endif
  25
  26 static const struct {
  27         u8 idcode;
  28 #if defined(CONFIG_FPGA)
  29         u32 fpga_size;
  30 #endif
  31         char *devicename;
  32 } zynq_fpga_descs[] = {
  33         ZYNQ_DESC(7Z007S),
  34         ZYNQ_DESC(7Z010),
  35         ZYNQ_DESC(7Z012S),
  36         ZYNQ_DESC(7Z014S),
  37         ZYNQ_DESC(7Z015),
  38         ZYNQ_DESC(7Z020),
  39         ZYNQ_DESC(7Z030),
  40         ZYNQ_DESC(7Z035),
  41         ZYNQ_DESC(7Z045),
  42         ZYNQ_DESC(7Z100),
  43         { /* Sentinel */ },
  44 };
  45
  46 int arch_cpu_init(void)
  47 {
  48         zynq_slcr_unlock();
  49 #ifndef CONFIG_SPL_BUILD
  50         /* Device config APB, unlock the PCAP */
  51         writel(0x757BDF0D, &devcfg_base->unlock);
  52         writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
  53
  54 #if (CONFIG_SYS_SDRAM_BASE == 0)
  55         /* remap DDR to zero, FILTERSTART */
  56         writel(0, &scu_base->filter_start);
  57
  58         /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
  59         writel(0x1F, &slcr_base->ocm_cfg);
  60         /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
  61         writel(0x0, &slcr_base->fpga_rst_ctrl);
  62         /* Set urgent bits with register */
  63         writel(0x0, &slcr_base->ddr_urgent_sel);
  64         /* Urgent write, ports S2/S3 */
  65         writel(0xC, &slcr_base->ddr_urgent);
  66 #endif
  67 #endif
  68         zynq_slcr_lock();
  69
  70         return 0;
  71 }
  72
  73 unsigned int zynq_get_silicon_version(void)
  74 {
  75         return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
  76                                                 >> ZYNQ_SILICON_VER_SHIFT;
  77 }
  78
  79 void reset_cpu(ulong addr)
  80 {
  81         zynq_slcr_cpu_reset();
  82         while (1)
  83                 ;
  84 }
  85
  86 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  87 void enable_caches(void)
  88 {
  89         /* Enable D-cache. I-cache is already enabled in start.S */
  90         dcache_enable();
  91 }
  92 #endif
  93
  94 static int __maybe_unused cpu_desc_id(void)
  95 {
  96         u32 idcode;
  97         u8 i;
  98
  99         idcode = zynq_slcr_get_idcode();
 100         for (i = 0; zynq_fpga_descs[i].idcode; i++) {
 101                 if (zynq_fpga_descs[i].idcode == idcode)
 102                         return i;
 103         }
 104
 105         return -ENODEV;
 106 }
 107
 108 #if defined(CONFIG_ARCH_EARLY_INIT_R)
 109 int arch_early_init_r(void)
 110 {
 111 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
 112     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
 113         int cpu_id = cpu_desc_id();
 114
 115         if (cpu_id < 0)
 116                 return 0;
 117
 118         fpga.size = zynq_fpga_descs[cpu_id].fpga_size;
 119         fpga.name = zynq_fpga_descs[cpu_id].devicename;
 120         fpga_init();
 121         fpga_add(fpga_xilinx, &fpga);
 122 #endif
 123         return 0;
 124 }
 125 #endif
 126
 127 #ifdef CONFIG_DISPLAY_CPUINFO
 128 int print_cpuinfo(void)
 129 {
 130         u32 version;
 131         int cpu_id = cpu_desc_id();
 132
 133         if (cpu_id < 0)
 134                 return 0;
 135
 136         version = zynq_get_silicon_version() << 1;
 137         if (version > (PCW_SILICON_VERSION_3 << 1))
 138                 version += 1;
 139
 140         printf("CPU:   Zynq %s\n", zynq_fpga_descs[cpu_id].devicename);
 141         printf("Silicon: v%d.%d\n", version >> 1, version & 1);
 142         return 0;
 143 }
 144 #endif