arch/arm/mach-zynq/include/mach/gpio.h

   1 /*
   2  * Copyright (c) 2013 Xilinx, Inc.
   3  * Copyright (c) 2015 DAVE Embedded Systems
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _ZYNQ_GPIO_H
   9 #define _ZYNQ_GPIO_H
  10
  11 /* Maximum banks */
  12 #define ZYNQ_GPIO_MAX_BANK      4
  13
  14 #define ZYNQ_GPIO_BANK0_NGPIO   32
  15 #define ZYNQ_GPIO_BANK1_NGPIO   22
  16 #define ZYNQ_GPIO_BANK2_NGPIO   32
  17 #define ZYNQ_GPIO_BANK3_NGPIO   32
  18
  19 #define ZYNQ_GPIO_NR_GPIOS      (ZYNQ_GPIO_BANK0_NGPIO + \
  20                                  ZYNQ_GPIO_BANK1_NGPIO + \
  21                                  ZYNQ_GPIO_BANK2_NGPIO + \
  22                                  ZYNQ_GPIO_BANK3_NGPIO)
  23
  24 #define ZYNQ_GPIO_BANK0_PIN_MIN 0
  25 #define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \
  26                                         ZYNQ_GPIO_BANK0_NGPIO - 1)
  27 #define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1)
  28 #define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \
  29                                         ZYNQ_GPIO_BANK1_NGPIO - 1)
  30 #define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1)
  31 #define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \
  32                                         ZYNQ_GPIO_BANK2_NGPIO - 1)
  33 #define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1)
  34 #define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \
  35                                         ZYNQ_GPIO_BANK3_NGPIO - 1)
  36
  37 /* Register offsets for the GPIO device */
  38 /* LSW Mask & Data -WO */
  39 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
  40 /* MSW Mask & Data -WO */
  41 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
  42 /* Data Register-RW */
  43 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)  (0x060 + (4 * BANK))
  44 /* Direction mode reg-RW */
  45 #define ZYNQ_GPIO_DIRM_OFFSET(BANK)     (0x204 + (0x40 * BANK))
  46 /* Output enable reg-RW */
  47 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK)    (0x208 + (0x40 * BANK))
  48 /* Interrupt mask reg-RO */
  49 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK)  (0x20C + (0x40 * BANK))
  50 /* Interrupt enable reg-WO */
  51 #define ZYNQ_GPIO_INTEN_OFFSET(BANK)    (0x210 + (0x40 * BANK))
  52 /* Interrupt disable reg-WO */
  53 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK)   (0x214 + (0x40 * BANK))
  54 /* Interrupt status reg-RO */
  55 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK)   (0x218 + (0x40 * BANK))
  56 /* Interrupt type reg-RW */
  57 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)  (0x21C + (0x40 * BANK))
  58 /* Interrupt polarity reg-RW */
  59 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK)   (0x220 + (0x40 * BANK))
  60 /* Interrupt on any, reg-RW */
  61 #define ZYNQ_GPIO_INTANY_OFFSET(BANK)   (0x224 + (0x40 * BANK))
  62
  63 /* Disable all interrupts mask */
  64 #define ZYNQ_GPIO_IXR_DISABLE_ALL       0xFFFFFFFF
  65
  66 /* Mid pin number of a bank */
  67 #define ZYNQ_GPIO_MID_PIN_NUM 16
  68
  69 /* GPIO upper 16 bit mask */
  70 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
  71
  72 #endif /* _ZYNQ_GPIO_H */