arch/arm/mach-zynq/include/mach/hardware.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (c) 2013 Xilinx Inc.
   4  */
   5
   6 #ifndef _ASM_ARCH_HARDWARE_H
   7 #define _ASM_ARCH_HARDWARE_H
   8
   9 #define ZYNQ_SYS_CTRL_BASEADDR          0xF8000000
  10 #define ZYNQ_DEV_CFG_APB_BASEADDR       0xF8007000
  11 #define ZYNQ_SCU_BASEADDR               0xF8F00000
  12 #define ZYNQ_GEM_BASEADDR0              0xE000B000
  13 #define ZYNQ_GEM_BASEADDR1              0xE000C000
  14 #define ZYNQ_I2C_BASEADDR0              0xE0004000
  15 #define ZYNQ_I2C_BASEADDR1              0xE0005000
  16 #define ZYNQ_QSPI_BASEADDR              0xE000D000
  17 #define ZYNQ_SMC_BASEADDR               0xE000E000
  18 #define ZYNQ_NAND_BASEADDR              0xE1000000
  19 #define ZYNQ_DDRC_BASEADDR              0xF8006000
  20 #define ZYNQ_EFUSE_BASEADDR             0xF800D000
  21 #define ZYNQ_USB_BASEADDR0              0xE0002000
  22 #define ZYNQ_USB_BASEADDR1              0xE0003000
  23
  24 /* Bootmode setting values */
  25 #define ZYNQ_BM_MASK            0x7
  26 #define ZYNQ_BM_QSPI            0x1
  27 #define ZYNQ_BM_NOR             0x2
  28 #define ZYNQ_BM_NAND            0x4
  29 #define ZYNQ_BM_SD              0x5
  30 #define ZYNQ_BM_JTAG            0x0
  31
  32 /* Reflect slcr offsets */
  33 struct slcr_regs {
  34         u32 scl; /* 0x0 */
  35         u32 slcr_lock; /* 0x4 */
  36         u32 slcr_unlock; /* 0x8 */
  37         u32 reserved0_1[61];
  38         u32 arm_pll_ctrl; /* 0x100 */
  39         u32 ddr_pll_ctrl; /* 0x104 */
  40         u32 io_pll_ctrl; /* 0x108 */
  41         u32 reserved0_2[5];
  42         u32 arm_clk_ctrl; /* 0x120 */
  43         u32 ddr_clk_ctrl; /* 0x124 */
  44         u32 dci_clk_ctrl; /* 0x128 */
  45         u32 aper_clk_ctrl; /* 0x12c */
  46         u32 reserved0_3[2];
  47         u32 gem0_rclk_ctrl; /* 0x138 */
  48         u32 gem1_rclk_ctrl; /* 0x13c */
  49         u32 gem0_clk_ctrl; /* 0x140 */
  50         u32 gem1_clk_ctrl; /* 0x144 */
  51         u32 smc_clk_ctrl; /* 0x148 */
  52         u32 lqspi_clk_ctrl; /* 0x14c */
  53         u32 sdio_clk_ctrl; /* 0x150 */
  54         u32 uart_clk_ctrl; /* 0x154 */
  55         u32 spi_clk_ctrl; /* 0x158 */
  56         u32 can_clk_ctrl; /* 0x15c */
  57         u32 can_mioclk_ctrl; /* 0x160 */
  58         u32 dbg_clk_ctrl; /* 0x164 */
  59         u32 pcap_clk_ctrl; /* 0x168 */
  60         u32 reserved0_4[1];
  61         u32 fpga0_clk_ctrl; /* 0x170 */
  62         u32 reserved0_5[3];
  63         u32 fpga1_clk_ctrl; /* 0x180 */
  64         u32 reserved0_6[3];
  65         u32 fpga2_clk_ctrl; /* 0x190 */
  66         u32 reserved0_7[3];
  67         u32 fpga3_clk_ctrl; /* 0x1a0 */
  68         u32 reserved0_8[8];
  69         u32 clk_621_true; /* 0x1c4 */
  70         u32 reserved1[14];
  71         u32 pss_rst_ctrl; /* 0x200 */
  72         u32 reserved2[15];
  73         u32 fpga_rst_ctrl; /* 0x240 */
  74         u32 reserved3[5];
  75         u32 reboot_status; /* 0x258 */
  76         u32 boot_mode; /* 0x25c */
  77         u32 reserved4[116];
  78         u32 trust_zone; /* 0x430 */ /* FIXME */
  79         u32 reserved5_1[63];
  80         u32 pss_idcode; /* 0x530 */
  81         u32 reserved5_2[51];
  82         u32 ddr_urgent; /* 0x600 */
  83         u32 reserved6[6];
  84         u32 ddr_urgent_sel; /* 0x61c */
  85         u32 reserved7[56];
  86         u32 mio_pin[54]; /* 0x700 - 0x7D4 */
  87         u32 reserved8[74];
  88         u32 lvl_shftr_en; /* 0x900 */
  89         u32 reserved9[3];
  90         u32 ocm_cfg; /* 0x910 */
  91 };
  92
  93 #define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
  94
  95 struct devcfg_regs {
  96         u32 ctrl; /* 0x0 */
  97         u32 lock; /* 0x4 */
  98         u32 cfg; /* 0x8 */
  99         u32 int_sts; /* 0xc */
 100         u32 int_mask; /* 0x10 */
 101         u32 status; /* 0x14 */
 102         u32 dma_src_addr; /* 0x18 */
 103         u32 dma_dst_addr; /* 0x1c */
 104         u32 dma_src_len; /* 0x20 */
 105         u32 dma_dst_len; /* 0x24 */
 106         u32 rom_shadow; /* 0x28 */
 107         u32 reserved1[2];
 108         u32 unlock; /* 0x34 */
 109         u32 reserved2[18];
 110         u32 mctrl; /* 0x80 */
 111         u32 reserved3;
 112         u32 write_count; /* 0x88 */
 113         u32 read_count; /* 0x8c */
 114 };
 115
 116 #define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
 117
 118 struct scu_regs {
 119         u32 reserved1[16];
 120         u32 filter_start; /* 0x40 */
 121         u32 filter_end; /* 0x44 */
 122 };
 123
 124 #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
 125
 126 struct ddrc_regs {
 127         u32 ddrc_ctrl; /* 0x0 */
 128         u32 reserved[60];
 129         u32 ecc_scrub; /* 0xF4 */
 130 };
 131 #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
 132
 133 struct efuse_reg {
 134         u32 reserved1[4];
 135         u32 status;
 136         u32 reserved2[3];
 137 };
 138
 139 #define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR)
 140
 141 #endif /* _ASM_ARCH_HARDWARE_H */