arch/arm/mm/proc-v7.S

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *  linux/arch/arm/mm/proc-v7.S
   4  *
   5  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   6  *
   7  *  This is the "shell" of the ARMv7 processor support.
   8  */
   9 #include <linux/arm-smccc.h>
  10 #include <linux/init.h>
  11 #include <linux/linkage.h>
  12 #include <asm/assembler.h>
  13 #include <asm/asm-offsets.h>
  14 #include <asm/hwcap.h>
  15 #include <asm/pgtable-hwdef.h>
  16 #include <asm/pgtable.h>
  17 #include <asm/memory.h>
  18
  19 #include "proc-macros.S"
  20
  21 #ifdef CONFIG_ARM_LPAE
  22 #include "proc-v7-3level.S"
  23 #else
  24 #include "proc-v7-2level.S"
  25 #endif
  26
  27 ENTRY(cpu_v7_proc_init)
  28         ret     lr
  29 ENDPROC(cpu_v7_proc_init)
  30
  31 ENTRY(cpu_v7_proc_fin)
  32         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  33         bic     r0, r0, #0x1000                 @ ...i............
  34         bic     r0, r0, #0x0006                 @ .............ca.
  35         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  36         ret     lr
  37 ENDPROC(cpu_v7_proc_fin)
  38
  39 /*
  40  *      cpu_v7_reset(loc, hyp)
  41  *
  42  *      Perform a soft reset of the system.  Put the CPU into the
  43  *      same state as it would be if it had been reset, and branch
  44  *      to what would be the reset vector.
  45  *
  46  *      - loc   - location to jump to for soft reset
  47  *      - hyp   - indicate if restart occurs in HYP mode
  48  *
  49  *      This code must be executed using a flat identity mapping with
  50  *      caches disabled.
  51  */
  52         .align  5
  53         .pushsection    .idmap.text, "ax"
  54 ENTRY(cpu_v7_reset)
  55         mrc     p15, 0, r2, c1, c0, 0           @ ctrl register
  56         bic     r2, r2, #0x1                    @ ...............m
  57  THUMB( bic     r2, r2, #1 << 30 )              @ SCTLR.TE (Thumb exceptions)
  58         mcr     p15, 0, r2, c1, c0, 0           @ disable MMU
  59         isb
  60 #ifdef CONFIG_ARM_VIRT_EXT
  61         teq     r1, #0
  62         bne     __hyp_soft_restart
  63 #endif
  64         bx      r0
  65 ENDPROC(cpu_v7_reset)
  66         .popsection
  67
  68 /*
  69  *      cpu_v7_do_idle()
  70  *
  71  *      Idle the processor (eg, wait for interrupt).
  72  *
  73  *      IRQs are already disabled.
  74  */
  75 ENTRY(cpu_v7_do_idle)
  76         dsb                                     @ WFI may enter a low-power mode
  77         wfi
  78         ret     lr
  79 ENDPROC(cpu_v7_do_idle)
  80
  81 ENTRY(cpu_v7_dcache_clean_area)
  82         ALT_SMP(W(nop))                 @ MP extensions imply L1 PTW
  83         ALT_UP_B(1f)
  84         ret     lr
  85 1:      dcache_line_size r2, r3
  86 2:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  87         add     r0, r0, r2
  88         subs    r1, r1, r2
  89         bhi     2b
  90         dsb     ishst
  91         ret     lr
  92 ENDPROC(cpu_v7_dcache_clean_area)
  93
  94 #ifdef CONFIG_ARM_PSCI
  95         .arch_extension sec
  96 ENTRY(cpu_v7_smc_switch_mm)
  97         stmfd   sp!, {r0 - r3}
  98         movw    r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
  99         movt    r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
 100         smc     #0
 101         ldmfd   sp!, {r0 - r3}
 102         b       cpu_v7_switch_mm
 103 ENDPROC(cpu_v7_smc_switch_mm)
 104         .arch_extension virt
 105 ENTRY(cpu_v7_hvc_switch_mm)
 106         stmfd   sp!, {r0 - r3}
 107         movw    r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
 108         movt    r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
 109         hvc     #0
 110         ldmfd   sp!, {r0 - r3}
 111         b       cpu_v7_switch_mm
 112 ENDPROC(cpu_v7_hvc_switch_mm)
 113 #endif
 114 ENTRY(cpu_v7_iciallu_switch_mm)
 115         mov     r3, #0
 116         mcr     p15, 0, r3, c7, c5, 0           @ ICIALLU
 117         b       cpu_v7_switch_mm
 118 ENDPROC(cpu_v7_iciallu_switch_mm)
 119 ENTRY(cpu_v7_bpiall_switch_mm)
 120         mov     r3, #0
 121         mcr     p15, 0, r3, c7, c5, 6           @ flush BTAC/BTB
 122         b       cpu_v7_switch_mm
 123 ENDPROC(cpu_v7_bpiall_switch_mm)
 124
 125         string  cpu_v7_name, "ARMv7 Processor"
 126         .align
 127
 128 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
 129 .globl  cpu_v7_suspend_size
 130 .equ    cpu_v7_suspend_size, 4 * 9
 131 #ifdef CONFIG_ARM_CPU_SUSPEND
 132 ENTRY(cpu_v7_do_suspend)
 133         stmfd   sp!, {r4 - r11, lr}
 134         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 135         mrc     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
 136         stmia   r0!, {r4 - r5}
 137 #ifdef CONFIG_MMU
 138         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
 139 #ifdef CONFIG_ARM_LPAE
 140         mrrc    p15, 1, r5, r7, c2      @ TTB 1
 141 #else
 142         mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
 143 #endif
 144         mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
 145 #endif
 146         mrc     p15, 0, r8, c1, c0, 0   @ Control register
 147         mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
 148         mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
 149         stmia   r0, {r5 - r11}
 150         ldmfd   sp!, {r4 - r11, pc}
 151 ENDPROC(cpu_v7_do_suspend)
 152
 153 ENTRY(cpu_v7_do_resume)
 154         mov     ip, #0
 155         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
 156         mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
 157         ldmia   r0!, {r4 - r5}
 158         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 159         mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
 160         ldmia   r0, {r5 - r11}
 161 #ifdef CONFIG_MMU
 162         mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
 163         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
 164 #ifdef CONFIG_ARM_LPAE
 165         mcrr    p15, 0, r1, ip, c2      @ TTB 0
 166         mcrr    p15, 1, r5, r7, c2      @ TTB 1
 167 #else
 168         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
 169         ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
 170         mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
 171         mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
 172 #endif
 173         mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
 174         ldr     r4, =PRRR               @ PRRR
 175         ldr     r5, =NMRR               @ NMRR
 176         mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
 177         mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
 178 #endif  /* CONFIG_MMU */
 179         mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
 180         teq     r4, r9                  @ Is it already set?
 181         mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
 182         mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
 183         isb
 184         dsb
 185         mov     r0, r8                  @ control register
 186         b       cpu_resume_mmu
 187 ENDPROC(cpu_v7_do_resume)
 188 #endif
 189
 190 .globl  cpu_ca9mp_suspend_size
 191 .equ    cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
 192 #ifdef CONFIG_ARM_CPU_SUSPEND
 193 ENTRY(cpu_ca9mp_do_suspend)
 194         stmfd   sp!, {r4 - r5}
 195         mrc     p15, 0, r4, c15, c0, 1          @ Diagnostic register
 196         mrc     p15, 0, r5, c15, c0, 0          @ Power register
 197         stmia   r0!, {r4 - r5}
 198         ldmfd   sp!, {r4 - r5}
 199         b       cpu_v7_do_suspend
 200 ENDPROC(cpu_ca9mp_do_suspend)
 201
 202 ENTRY(cpu_ca9mp_do_resume)
 203         ldmia   r0!, {r4 - r5}
 204         mrc     p15, 0, r10, c15, c0, 1         @ Read Diagnostic register
 205         teq     r4, r10                         @ Already restored?
 206         mcrne   p15, 0, r4, c15, c0, 1          @ No, so restore it
 207         mrc     p15, 0, r10, c15, c0, 0         @ Read Power register
 208         teq     r5, r10                         @ Already restored?
 209         mcrne   p15, 0, r5, c15, c0, 0          @ No, so restore it
 210         b       cpu_v7_do_resume
 211 ENDPROC(cpu_ca9mp_do_resume)
 212 #endif
 213
 214 #ifdef CONFIG_CPU_PJ4B
 215         globl_equ       cpu_pj4b_switch_mm,     cpu_v7_switch_mm
 216         globl_equ       cpu_pj4b_set_pte_ext,   cpu_v7_set_pte_ext
 217         globl_equ       cpu_pj4b_proc_init,     cpu_v7_proc_init
 218         globl_equ       cpu_pj4b_proc_fin,      cpu_v7_proc_fin
 219         globl_equ       cpu_pj4b_reset,         cpu_v7_reset
 220 #ifdef CONFIG_PJ4B_ERRATA_4742
 221 ENTRY(cpu_pj4b_do_idle)
 222         dsb                                     @ WFI may enter a low-power mode
 223         wfi
 224         dsb                                     @barrier
 225         ret     lr
 226 ENDPROC(cpu_pj4b_do_idle)
 227 #else
 228         globl_equ       cpu_pj4b_do_idle,       cpu_v7_do_idle
 229 #endif
 230         globl_equ       cpu_pj4b_dcache_clean_area,     cpu_v7_dcache_clean_area
 231 #ifdef CONFIG_ARM_CPU_SUSPEND
 232 ENTRY(cpu_pj4b_do_suspend)
 233         stmfd   sp!, {r6 - r10}
 234         mrc     p15, 1, r6, c15, c1, 0  @ save CP15 - extra features
 235         mrc     p15, 1, r7, c15, c2, 0  @ save CP15 - Aux Func Modes Ctrl 0
 236         mrc     p15, 1, r8, c15, c1, 2  @ save CP15 - Aux Debug Modes Ctrl 2
 237         mrc     p15, 1, r9, c15, c1, 1  @ save CP15 - Aux Debug Modes Ctrl 1
 238         mrc     p15, 0, r10, c9, c14, 0  @ save CP15 - PMC
 239         stmia   r0!, {r6 - r10}
 240         ldmfd   sp!, {r6 - r10}
 241         b cpu_v7_do_suspend
 242 ENDPROC(cpu_pj4b_do_suspend)
 243
 244 ENTRY(cpu_pj4b_do_resume)
 245         ldmia   r0!, {r6 - r10}
 246         mcr     p15, 1, r6, c15, c1, 0  @ restore CP15 - extra features
 247         mcr     p15, 1, r7, c15, c2, 0  @ restore CP15 - Aux Func Modes Ctrl 0
 248         mcr     p15, 1, r8, c15, c1, 2  @ restore CP15 - Aux Debug Modes Ctrl 2
 249         mcr     p15, 1, r9, c15, c1, 1  @ restore CP15 - Aux Debug Modes Ctrl 1
 250         mcr     p15, 0, r10, c9, c14, 0  @ restore CP15 - PMC
 251         b cpu_v7_do_resume
 252 ENDPROC(cpu_pj4b_do_resume)
 253 #endif
 254 .globl  cpu_pj4b_suspend_size
 255 .equ    cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
 256
 257 #endif
 258
 259 /*
 260  *      __v7_setup
 261  *
 262  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
 263  *      on.  Return in r0 the new CP15 C1 control register setting.
 264  *
 265  *      r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack
 266  *      r4: TTBR0 (low word)
 267  *      r5: TTBR0 (high word if LPAE)
 268  *      r8: TTBR1
 269  *      r9: Main ID register
 270  *
 271  *      This should be able to cover all ARMv7 cores.
 272  *
 273  *      It is assumed that:
 274  *      - cache type register is implemented
 275  */
 276 __v7_ca5mp_setup:
 277 __v7_ca9mp_setup:
 278 __v7_cr7mp_setup:
 279 __v7_cr8mp_setup:
 280         mov     r10, #(1 << 0)                  @ Cache/TLB ops broadcasting
 281         b       1f
 282 __v7_ca7mp_setup:
 283 __v7_ca12mp_setup:
 284 __v7_ca15mp_setup:
 285 __v7_b15mp_setup:
 286 __v7_ca17mp_setup:
 287         mov     r10, #0
 288 1:      adr     r0, __v7_setup_stack_ptr
 289         ldr     r12, [r0]
 290         add     r12, r12, r0                    @ the local stack
 291         stmia   r12, {r1-r6, lr}                @ v7_invalidate_l1 touches r0-r6
 292         bl      v7_invalidate_l1
 293         ldmia   r12, {r1-r6, lr}
 294 #ifdef CONFIG_SMP
 295         orr     r10, r10, #(1 << 6)             @ Enable SMP/nAMP mode
 296         ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
 297         ALT_UP(mov      r0, r10)                @ fake it for UP
 298         orr     r10, r10, r0                    @ Set required bits
 299         teq     r10, r0                         @ Were they already set?
 300         mcrne   p15, 0, r10, c1, c0, 1          @ No, update register
 301 #endif
 302         b       __v7_setup_cont
 303
 304 /*
 305  * Errata:
 306  *  r0, r10 available for use
 307  *  r1, r2, r4, r5, r9, r13: must be preserved
 308  *  r3: contains MIDR rX number in bits 23-20
 309  *  r6: contains MIDR rXpY as 8-bit XY number
 310  *  r9: MIDR
 311  */
 312 __ca8_errata:
 313 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
 314         teq     r3, #0x00100000                 @ only present in r1p*
 315         mrceq   p15, 0, r0, c1, c0, 1           @ read aux control register
 316         orreq   r0, r0, #(1 << 6)               @ set IBE to 1
 317         mcreq   p15, 0, r0, c1, c0, 1           @ write aux control register
 318 #endif
 319 #ifdef CONFIG_ARM_ERRATA_458693
 320         teq     r6, #0x20                       @ only present in r2p0
 321         mrceq   p15, 0, r0, c1, c0, 1           @ read aux control register
 322         orreq   r0, r0, #(1 << 5)               @ set L1NEON to 1
 323         orreq   r0, r0, #(1 << 9)               @ set PLDNOP to 1
 324         mcreq   p15, 0, r0, c1, c0, 1           @ write aux control register
 325 #endif
 326 #ifdef CONFIG_ARM_ERRATA_460075
 327         teq     r6, #0x20                       @ only present in r2p0
 328         mrceq   p15, 1, r0, c9, c0, 2           @ read L2 cache aux ctrl register
 329         tsteq   r0, #1 << 22
 330         orreq   r0, r0, #(1 << 22)              @ set the Write Allocate disable bit
 331         mcreq   p15, 1, r0, c9, c0, 2           @ write the L2 cache aux ctrl register
 332 #endif
 333         b       __errata_finish
 334
 335 __ca9_errata:
 336 #ifdef CONFIG_ARM_ERRATA_742230
 337         cmp     r6, #0x22                       @ only present up to r2p2
 338         mrcle   p15, 0, r0, c15, c0, 1          @ read diagnostic register
 339         orrle   r0, r0, #1 << 4                 @ set bit #4
 340         mcrle   p15, 0, r0, c15, c0, 1          @ write diagnostic register
 341 #endif
 342 #ifdef CONFIG_ARM_ERRATA_742231
 343         teq     r6, #0x20                       @ present in r2p0
 344         teqne   r6, #0x21                       @ present in r2p1
 345         teqne   r6, #0x22                       @ present in r2p2
 346         mrceq   p15, 0, r0, c15, c0, 1          @ read diagnostic register
 347         orreq   r0, r0, #1 << 12                @ set bit #12
 348         orreq   r0, r0, #1 << 22                @ set bit #22
 349         mcreq   p15, 0, r0, c15, c0, 1          @ write diagnostic register
 350 #endif
 351 #ifdef CONFIG_ARM_ERRATA_743622
 352         teq     r3, #0x00200000                 @ only present in r2p*
 353         mrceq   p15, 0, r0, c15, c0, 1          @ read diagnostic register
 354         orreq   r0, r0, #1 << 6                 @ set bit #6
 355         mcreq   p15, 0, r0, c15, c0, 1          @ write diagnostic register
 356 #endif
 357 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
 358         ALT_SMP(cmp r6, #0x30)                  @ present prior to r3p0
 359         ALT_UP_B(1f)
 360         mrclt   p15, 0, r0, c15, c0, 1          @ read diagnostic register
 361         orrlt   r0, r0, #1 << 11                @ set bit #11
 362         mcrlt   p15, 0, r0, c15, c0, 1          @ write diagnostic register
 363 1:
 364 #endif
 365         b       __errata_finish
 366
 367 __ca15_errata:
 368 #ifdef CONFIG_ARM_ERRATA_773022
 369         cmp     r6, #0x4                        @ only present up to r0p4
 370         mrcle   p15, 0, r0, c1, c0, 1           @ read aux control register
 371         orrle   r0, r0, #1 << 1                 @ disable loop buffer
 372         mcrle   p15, 0, r0, c1, c0, 1           @ write aux control register
 373 #endif
 374         b       __errata_finish
 375
 376 __ca12_errata:
 377 #ifdef CONFIG_ARM_ERRATA_818325_852422
 378         mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
 379         orr     r10, r10, #1 << 12              @ set bit #12
 380         mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
 381 #endif
 382 #ifdef CONFIG_ARM_ERRATA_821420
 383         mrc     p15, 0, r10, c15, c0, 2         @ read internal feature reg
 384         orr     r10, r10, #1 << 1               @ set bit #1
 385         mcr     p15, 0, r10, c15, c0, 2         @ write internal feature reg
 386 #endif
 387 #ifdef CONFIG_ARM_ERRATA_825619
 388         mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
 389         orr     r10, r10, #1 << 24              @ set bit #24
 390         mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
 391 #endif
 392         b       __errata_finish
 393
 394 __ca17_errata:
 395 #ifdef CONFIG_ARM_ERRATA_852421
 396         cmp     r6, #0x12                       @ only present up to r1p2
 397         mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 398         orrle   r10, r10, #1 << 24              @ set bit #24
 399         mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 400 #endif
 401 #ifdef CONFIG_ARM_ERRATA_852423
 402         cmp     r6, #0x12                       @ only present up to r1p2
 403         mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 404         orrle   r10, r10, #1 << 12              @ set bit #12
 405         mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 406 #endif
 407         b       __errata_finish
 408
 409 __v7_pj4b_setup:
 410 #ifdef CONFIG_CPU_PJ4B
 411
 412 /* Auxiliary Debug Modes Control 1 Register */
 413 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
 414 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
 415 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
 416
 417 /* Auxiliary Debug Modes Control 2 Register */
 418 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
 419 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
 420 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
 421 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
 422 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
 423 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
 424                             PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
 425
 426 /* Auxiliary Functional Modes Control Register 0 */
 427 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
 428 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
 429 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
 430
 431 /* Auxiliary Debug Modes Control 0 Register */
 432 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
 433
 434         /* Auxiliary Debug Modes Control 1 Register */
 435         mrc     p15, 1, r0, c15, c1, 1
 436         orr     r0, r0, #PJ4B_CLEAN_LINE
 437         orr     r0, r0, #PJ4B_INTER_PARITY
 438         bic     r0, r0, #PJ4B_STATIC_BP
 439         mcr     p15, 1, r0, c15, c1, 1
 440
 441         /* Auxiliary Debug Modes Control 2 Register */
 442         mrc     p15, 1, r0, c15, c1, 2
 443         bic     r0, r0, #PJ4B_FAST_LDR
 444         orr     r0, r0, #PJ4B_AUX_DBG_CTRL2
 445         mcr     p15, 1, r0, c15, c1, 2
 446
 447         /* Auxiliary Functional Modes Control Register 0 */
 448         mrc     p15, 1, r0, c15, c2, 0
 449 #ifdef CONFIG_SMP
 450         orr     r0, r0, #PJ4B_SMP_CFB
 451 #endif
 452         orr     r0, r0, #PJ4B_L1_PAR_CHK
 453         orr     r0, r0, #PJ4B_BROADCAST_CACHE
 454         mcr     p15, 1, r0, c15, c2, 0
 455
 456         /* Auxiliary Debug Modes Control 0 Register */
 457         mrc     p15, 1, r0, c15, c1, 0
 458         orr     r0, r0, #PJ4B_WFI_WFE
 459         mcr     p15, 1, r0, c15, c1, 0
 460
 461 #endif /* CONFIG_CPU_PJ4B */
 462
 463 __v7_setup:
 464         adr     r0, __v7_setup_stack_ptr
 465         ldr     r12, [r0]
 466         add     r12, r12, r0                    @ the local stack
 467         stmia   r12, {r1-r6, lr}                @ v7_invalidate_l1 touches r0-r6
 468         bl      v7_invalidate_l1
 469         ldmia   r12, {r1-r6, lr}
 470
 471 __v7_setup_cont:
 472         and     r0, r9, #0xff000000             @ ARM?
 473         teq     r0, #0x41000000
 474         bne     __errata_finish
 475         and     r3, r9, #0x00f00000             @ variant
 476         and     r6, r9, #0x0000000f             @ revision
 477         orr     r6, r6, r3, lsr #20-4           @ combine variant and revision
 478         ubfx    r0, r9, #4, #12                 @ primary part number
 479
 480         /* Cortex-A8 Errata */
 481         ldr     r10, =0x00000c08                @ Cortex-A8 primary part number
 482         teq     r0, r10
 483         beq     __ca8_errata
 484
 485         /* Cortex-A9 Errata */
 486         ldr     r10, =0x00000c09                @ Cortex-A9 primary part number
 487         teq     r0, r10
 488         beq     __ca9_errata
 489
 490         /* Cortex-A12 Errata */
 491         ldr     r10, =0x00000c0d                @ Cortex-A12 primary part number
 492         teq     r0, r10
 493         beq     __ca12_errata
 494
 495         /* Cortex-A17 Errata */
 496         ldr     r10, =0x00000c0e                @ Cortex-A17 primary part number
 497         teq     r0, r10
 498         beq     __ca17_errata
 499
 500         /* Cortex-A15 Errata */
 501         ldr     r10, =0x00000c0f                @ Cortex-A15 primary part number
 502         teq     r0, r10
 503         beq     __ca15_errata
 504
 505 __errata_finish:
 506         mov     r10, #0
 507         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
 508 #ifdef CONFIG_MMU
 509         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
 510         v7_ttb_setup r10, r4, r5, r8, r3        @ TTBCR, TTBRx setup
 511         ldr     r3, =PRRR                       @ PRRR
 512         ldr     r6, =NMRR                       @ NMRR
 513         mcr     p15, 0, r3, c10, c2, 0          @ write PRRR
 514         mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
 515 #endif
 516         dsb                                     @ Complete invalidations
 517 #ifndef CONFIG_ARM_THUMBEE
 518         mrc     p15, 0, r0, c0, c1, 0           @ read ID_PFR0 for ThumbEE
 519         and     r0, r0, #(0xf << 12)            @ ThumbEE enabled field
 520         teq     r0, #(1 << 12)                  @ check if ThumbEE is present
 521         bne     1f
 522         mov     r3, #0
 523         mcr     p14, 6, r3, c1, c0, 0           @ Initialize TEEHBR to 0
 524         mrc     p14, 6, r0, c0, c0, 0           @ load TEECR
 525         orr     r0, r0, #1                      @ set the 1st bit in order to
 526         mcr     p14, 6, r0, c0, c0, 0           @ stop userspace TEEHBR access
 527 1:
 528 #endif
 529         adr     r3, v7_crval
 530         ldmia   r3, {r3, r6}
 531  ARM_BE8(orr    r6, r6, #1 << 25)               @ big-endian page tables
 532 #ifdef CONFIG_SWP_EMULATE
 533         orr     r3, r3, #(1 << 10)              @ set SW bit in "clear"
 534         bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
 535 #endif
 536         mrc     p15, 0, r0, c1, c0, 0           @ read control register
 537         bic     r0, r0, r3                      @ clear bits them
 538         orr     r0, r0, r6                      @ set them
 539  THUMB( orr     r0, r0, #1 << 30        )       @ Thumb exceptions
 540         ret     lr                              @ return to head.S:__ret
 541
 542         .align  2
 543 __v7_setup_stack_ptr:
 544         .word   PHYS_RELATIVE(__v7_setup_stack, .)
 545 ENDPROC(__v7_setup)
 546
 547         .bss
 548         .align  2
 549 __v7_setup_stack:
 550         .space  4 * 7                           @ 7 registers
 551
 552         __INITDATA
 553
 554         .weak cpu_v7_bugs_init
 555
 556         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
 557         define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
 558
 559 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 560         @ generic v7 bpiall on context switch
 561         globl_equ       cpu_v7_bpiall_proc_init,        cpu_v7_proc_init
 562         globl_equ       cpu_v7_bpiall_proc_fin,         cpu_v7_proc_fin
 563         globl_equ       cpu_v7_bpiall_reset,            cpu_v7_reset
 564         globl_equ       cpu_v7_bpiall_do_idle,          cpu_v7_do_idle
 565         globl_equ       cpu_v7_bpiall_dcache_clean_area, cpu_v7_dcache_clean_area
 566         globl_equ       cpu_v7_bpiall_set_pte_ext,      cpu_v7_set_pte_ext
 567         globl_equ       cpu_v7_bpiall_suspend_size,     cpu_v7_suspend_size
 568 #ifdef CONFIG_ARM_CPU_SUSPEND
 569         globl_equ       cpu_v7_bpiall_do_suspend,       cpu_v7_do_suspend
 570         globl_equ       cpu_v7_bpiall_do_resume,        cpu_v7_do_resume
 571 #endif
 572         define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
 573
 574 #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_bpiall_processor_functions
 575 #else
 576 #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_processor_functions
 577 #endif
 578
 579 #ifndef CONFIG_ARM_LPAE
 580         @ Cortex-A8 - always needs bpiall switch_mm implementation
 581         globl_equ       cpu_ca8_proc_init,      cpu_v7_proc_init
 582         globl_equ       cpu_ca8_proc_fin,       cpu_v7_proc_fin
 583         globl_equ       cpu_ca8_reset,          cpu_v7_reset
 584         globl_equ       cpu_ca8_do_idle,        cpu_v7_do_idle
 585         globl_equ       cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
 586         globl_equ       cpu_ca8_set_pte_ext,    cpu_v7_set_pte_ext
 587         globl_equ       cpu_ca8_switch_mm,      cpu_v7_bpiall_switch_mm
 588         globl_equ       cpu_ca8_suspend_size,   cpu_v7_suspend_size
 589 #ifdef CONFIG_ARM_CPU_SUSPEND
 590         globl_equ       cpu_ca8_do_suspend,     cpu_v7_do_suspend
 591         globl_equ       cpu_ca8_do_resume,      cpu_v7_do_resume
 592 #endif
 593         define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca8_ibe
 594
 595         @ Cortex-A9 - needs more registers preserved across suspend/resume
 596         @ and bpiall switch_mm for hardening
 597         globl_equ       cpu_ca9mp_proc_init,    cpu_v7_proc_init
 598         globl_equ       cpu_ca9mp_proc_fin,     cpu_v7_proc_fin
 599         globl_equ       cpu_ca9mp_reset,        cpu_v7_reset
 600         globl_equ       cpu_ca9mp_do_idle,      cpu_v7_do_idle
 601         globl_equ       cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
 602 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 603         globl_equ       cpu_ca9mp_switch_mm,    cpu_v7_bpiall_switch_mm
 604 #else
 605         globl_equ       cpu_ca9mp_switch_mm,    cpu_v7_switch_mm
 606 #endif
 607         globl_equ       cpu_ca9mp_set_pte_ext,  cpu_v7_set_pte_ext
 608         define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
 609 #endif
 610
 611         @ Cortex-A15 - needs iciallu switch_mm for hardening
 612         globl_equ       cpu_ca15_proc_init,     cpu_v7_proc_init
 613         globl_equ       cpu_ca15_proc_fin,      cpu_v7_proc_fin
 614         globl_equ       cpu_ca15_reset,         cpu_v7_reset
 615         globl_equ       cpu_ca15_do_idle,       cpu_v7_do_idle
 616         globl_equ       cpu_ca15_dcache_clean_area, cpu_v7_dcache_clean_area
 617 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 618         globl_equ       cpu_ca15_switch_mm,     cpu_v7_iciallu_switch_mm
 619 #else
 620         globl_equ       cpu_ca15_switch_mm,     cpu_v7_switch_mm
 621 #endif
 622         globl_equ       cpu_ca15_set_pte_ext,   cpu_v7_set_pte_ext
 623         globl_equ       cpu_ca15_suspend_size,  cpu_v7_suspend_size
 624         globl_equ       cpu_ca15_do_suspend,    cpu_v7_do_suspend
 625         globl_equ       cpu_ca15_do_resume,     cpu_v7_do_resume
 626         define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca15_ibe
 627 #ifdef CONFIG_CPU_PJ4B
 628         define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
 629 #endif
 630
 631         .section ".rodata"
 632
 633         string  cpu_arch_name, "armv7"
 634         string  cpu_elf_name, "v7"
 635         .align
 636
 637         .section ".proc.info.init", #alloc
 638
 639         /*
 640          * Standard v7 proc info content
 641          */
 642 .macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions, cache_fns = v7_cache_fns
 643         ALT_SMP(.long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 644                         PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
 645         ALT_UP(.long    PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 646                         PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
 647         .long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
 648                 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
 649         initfn  \initfunc, \name
 650         .long   cpu_arch_name
 651         .long   cpu_elf_name
 652         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
 653                 HWCAP_EDSP | HWCAP_TLS | \hwcaps
 654         .long   cpu_v7_name
 655         .long   \proc_fns
 656         .long   v7wbi_tlb_fns
 657         .long   v6_user_fns
 658         .long   \cache_fns
 659 .endm
 660
 661 #ifndef CONFIG_ARM_LPAE
 662         /*
 663          * ARM Ltd. Cortex A5 processor.
 664          */
 665         .type   __v7_ca5mp_proc_info, #object
 666 __v7_ca5mp_proc_info:
 667         .long   0x410fc050
 668         .long   0xff0ffff0
 669         __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
 670         .size   __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
 671
 672         /*
 673          * ARM Ltd. Cortex A9 processor.
 674          */
 675         .type   __v7_ca9mp_proc_info, #object
 676 __v7_ca9mp_proc_info:
 677         .long   0x410fc090
 678         .long   0xff0ffff0
 679         __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
 680         .size   __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
 681
 682         /*
 683          * ARM Ltd. Cortex A8 processor.
 684          */
 685         .type   __v7_ca8_proc_info, #object
 686 __v7_ca8_proc_info:
 687         .long   0x410fc080
 688         .long   0xff0ffff0
 689         __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
 690         .size   __v7_ca8_proc_info, . - __v7_ca8_proc_info
 691
 692 #endif  /* CONFIG_ARM_LPAE */
 693
 694         /*
 695          * Marvell PJ4B processor.
 696          */
 697 #ifdef CONFIG_CPU_PJ4B
 698         .type   __v7_pj4b_proc_info, #object
 699 __v7_pj4b_proc_info:
 700         .long   0x560f5800
 701         .long   0xff0fff00
 702         __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
 703         .size   __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
 704 #endif
 705
 706         /*
 707          * ARM Ltd. Cortex R7 processor.
 708          */
 709         .type   __v7_cr7mp_proc_info, #object
 710 __v7_cr7mp_proc_info:
 711         .long   0x410fc170
 712         .long   0xff0ffff0
 713         __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
 714         .size   __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
 715
 716         /*
 717          * ARM Ltd. Cortex R8 processor.
 718          */
 719         .type   __v7_cr8mp_proc_info, #object
 720 __v7_cr8mp_proc_info:
 721         .long   0x410fc180
 722         .long   0xff0ffff0
 723         __v7_proc __v7_cr8mp_proc_info, __v7_cr8mp_setup
 724         .size   __v7_cr8mp_proc_info, . - __v7_cr8mp_proc_info
 725
 726         /*
 727          * ARM Ltd. Cortex A7 processor.
 728          */
 729         .type   __v7_ca7mp_proc_info, #object
 730 __v7_ca7mp_proc_info:
 731         .long   0x410fc070
 732         .long   0xff0ffff0
 733         __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
 734         .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
 735
 736         /*
 737          * ARM Ltd. Cortex A12 processor.
 738          */
 739         .type   __v7_ca12mp_proc_info, #object
 740 __v7_ca12mp_proc_info:
 741         .long   0x410fc0d0
 742         .long   0xff0ffff0
 743         __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
 744         .size   __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
 745
 746         /*
 747          * ARM Ltd. Cortex A15 processor.
 748          */
 749         .type   __v7_ca15mp_proc_info, #object
 750 __v7_ca15mp_proc_info:
 751         .long   0x410fc0f0
 752         .long   0xff0ffff0
 753         __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup, proc_fns = ca15_processor_functions
 754         .size   __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
 755
 756         /*
 757          * Broadcom Corporation Brahma-B15 processor.
 758          */
 759         .type   __v7_b15mp_proc_info, #object
 760 __v7_b15mp_proc_info:
 761         .long   0x420f00f0
 762         .long   0xff0ffff0
 763         __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup, proc_fns = ca15_processor_functions, cache_fns = b15_cache_fns
 764         .size   __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
 765
 766         /*
 767          * ARM Ltd. Cortex A17 processor.
 768          */
 769         .type   __v7_ca17mp_proc_info, #object
 770 __v7_ca17mp_proc_info:
 771         .long   0x410fc0e0
 772         .long   0xff0ffff0
 773         __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
 774         .size   __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
 775
 776         /* ARM Ltd. Cortex A73 processor */
 777         .type   __v7_ca73_proc_info, #object
 778 __v7_ca73_proc_info:
 779         .long   0x410fd090
 780         .long   0xff0ffff0
 781         __v7_proc __v7_ca73_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
 782         .size   __v7_ca73_proc_info, . - __v7_ca73_proc_info
 783
 784         /* ARM Ltd. Cortex A75 processor */
 785         .type   __v7_ca75_proc_info, #object
 786 __v7_ca75_proc_info:
 787         .long   0x410fd0a0
 788         .long   0xff0ffff0
 789         __v7_proc __v7_ca75_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
 790         .size   __v7_ca75_proc_info, . - __v7_ca75_proc_info
 791
 792         /*
 793          * Qualcomm Inc. Krait processors.
 794          */
 795         .type   __krait_proc_info, #object
 796 __krait_proc_info:
 797         .long   0x510f0400              @ Required ID value
 798         .long   0xff0ffc00              @ Mask for ID
 799         /*
 800          * Some Krait processors don't indicate support for SDIV and UDIV
 801          * instructions in the ARM instruction set, even though they actually
 802          * do support them. They also don't indicate support for fused multiply
 803          * instructions even though they actually do support them.
 804          */
 805         __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
 806         .size   __krait_proc_info, . - __krait_proc_info
 807
 808         /*
 809          * Match any ARMv7 processor core.
 810          */
 811         .type   __v7_proc_info, #object
 812 __v7_proc_info:
 813         .long   0x000f0000              @ Required ID value
 814         .long   0x000f0000              @ Mask for ID
 815         __v7_proc __v7_proc_info, __v7_setup
 816         .size   __v7_proc_info, . - __v7_proc_info