arch/arm/mm/tlb-v4wb.S

   1 /*
   2  *  linux/arch/arm/mm/tlbv4wb.S
   3  *
   4  *  Copyright (C) 1997-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  ARM architecture version 4 TLB handling functions.
  11  *  These assume a split I/D TLBs w/o I TLB entry, with a write buffer.
  12  *
  13  *  Processors: SA110 SA1100 SA1110
  14  */
  15 #include <linux/linkage.h>
  16 #include <linux/init.h>
  17 #include <asm/constants.h>
  18 #include <asm/tlbflush.h>
  19 #include "proc-macros.S"
  20
  21         .align  5
  22 /*
  23  *      v4wb_flush_user_tlb_range(start, end, mm)
  24  *
  25  *      Invalidate a range of TLB entries in the specified address space.
  26  *
  27  *      - start - range start address
  28  *      - end   - range end address
  29  *      - mm    - mm_struct describing address space
  30  */
  31         .align  5
  32 ENTRY(v4wb_flush_user_tlb_range)
  33         vma_vm_mm ip, r2
  34         act_mm  r3                              @ get current->active_mm
  35         eors    r3, ip, r3                              @ == mm ?
  36         movne   pc, lr                          @ no, we dont do anything
  37         vma_vm_flags r2, r2
  38         mcr     p15, 0, r3, c7, c10, 4          @ drain WB
  39         tst     r2, #VM_EXEC
  40         mcrne   p15, 0, r3, c8, c5, 0           @ invalidate I TLB
  41         bic     r0, r0, #0x0ff
  42         bic     r0, r0, #0xf00
  43 1:      mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
  44         add     r0, r0, #PAGE_SZ
  45         cmp     r0, r1
  46         blo     1b
  47         mov     pc, lr
  48
  49 /*
  50  *      v4_flush_kern_tlb_range(start, end)
  51  *
  52  *      Invalidate a range of TLB entries in the specified kernel
  53  *      address range.
  54  *
  55  *      - start - virtual address (may not be aligned)
  56  *      - end   - virtual address (may not be aligned)
  57  */
  58 ENTRY(v4wb_flush_kern_tlb_range)
  59         mov     r3, #0
  60         mcr     p15, 0, r3, c7, c10, 4          @ drain WB
  61         bic     r0, r0, #0x0ff
  62         bic     r0, r0, #0xf00
  63         mcr     p15, 0, r3, c8, c5, 0           @ invalidate I TLB
  64 1:      mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
  65         add     r0, r0, #PAGE_SZ
  66         cmp     r0, r1
  67         blo     1b
  68         mov     pc, lr
  69
  70         __INITDATA
  71
  72         .type   v4wb_tlb_fns, #object
  73 ENTRY(v4wb_tlb_fns)
  74         .long   v4wb_flush_user_tlb_range
  75         .long   v4wb_flush_kern_tlb_range
  76         .long   v4wb_tlb_flags
  77         .size   v4wb_tlb_fns, . - v4wb_tlb_fns