arch/arm/plat-pxa/include/plat/dma.h

   1 #ifndef __PLAT_DMA_H
   2 #define __PLAT_DMA_H
   3
   4 #define DMAC_REG(x)     (*((volatile u32 *)(DMAC_REGS_VIRT + (x))))
   5
   6 #define DCSR(n)         DMAC_REG((n) << 2)
   7 #define DALGN           DMAC_REG(0x00a0)  /* DMA Alignment Register */
   8 #define DINT            DMAC_REG(0x00f0)  /* DMA Interrupt Register */
   9 #define DDADR(n)        DMAC_REG(0x0200 + ((n) << 4))
  10 #define DSADR(n)        DMAC_REG(0x0204 + ((n) << 4))
  11 #define DTADR(n)        DMAC_REG(0x0208 + ((n) << 4))
  12 #define DCMD(n)         DMAC_REG(0x020c + ((n) << 4))
  13 #define DRCMR(n)        DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \
  14                                  (((n) & 0x3f) << 2))
  15
  16 #define DCSR_RUN        (1 << 31)       /* Run Bit (read / write) */
  17 #define DCSR_NODESC     (1 << 30)       /* No-Descriptor Fetch (read / write) */
  18 #define DCSR_STOPIRQEN  (1 << 29)       /* Stop Interrupt Enable (read / write) */
  19 #define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
  20 #define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
  21 #define DCSR_ENDINTR    (1 << 2)        /* End Interrupt (read / write) */
  22 #define DCSR_STARTINTR  (1 << 1)        /* Start Interrupt (read / write) */
  23 #define DCSR_BUSERR     (1 << 0)        /* Bus Error Interrupt (read / write) */
  24
  25 #define DCSR_EORIRQEN   (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
  26 #define DCSR_EORJMPEN   (1 << 27)       /* Jump to next descriptor on EOR */
  27 #define DCSR_EORSTOPEN  (1 << 26)       /* STOP on an EOR */
  28 #define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
  29 #define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
  30 #define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
  31 #define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
  32
  33 #define DRCMR_MAPVLD    (1 << 7)        /* Map Valid (read / write) */
  34 #define DRCMR_CHLNUM    0x1f            /* mask for Channel Number (read / write) */
  35
  36 #define DDADR_DESCADDR  0xfffffff0      /* Address of next descriptor (mask) */
  37 #define DDADR_STOP      (1 << 0)        /* Stop (read / write) */
  38
  39 #define DCMD_INCSRCADDR (1 << 31)       /* Source Address Increment Setting. */
  40 #define DCMD_INCTRGADDR (1 << 30)       /* Target Address Increment Setting. */
  41 #define DCMD_FLOWSRC    (1 << 29)       /* Flow Control by the source. */
  42 #define DCMD_FLOWTRG    (1 << 28)       /* Flow Control by the target. */
  43 #define DCMD_STARTIRQEN (1 << 22)       /* Start Interrupt Enable */
  44 #define DCMD_ENDIRQEN   (1 << 21)       /* End Interrupt Enable */
  45 #define DCMD_ENDIAN     (1 << 18)       /* Device Endian-ness. */
  46 #define DCMD_BURST8     (1 << 16)       /* 8 byte burst */
  47 #define DCMD_BURST16    (2 << 16)       /* 16 byte burst */
  48 #define DCMD_BURST32    (3 << 16)       /* 32 byte burst */
  49 #define DCMD_WIDTH1     (1 << 14)       /* 1 byte width */
  50 #define DCMD_WIDTH2     (2 << 14)       /* 2 byte width (HalfWord) */
  51 #define DCMD_WIDTH4     (3 << 14)       /* 4 byte width (Word) */
  52 #define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
  53
  54 /*
  55  * Descriptor structure for PXA's DMA engine
  56  * Note: this structure must always be aligned to a 16-byte boundary.
  57  */
  58
  59 typedef struct pxa_dma_desc {
  60         volatile u32 ddadr;     /* Points to the next descriptor + flags */
  61         volatile u32 dsadr;     /* DSADR value for the current transfer */
  62         volatile u32 dtadr;     /* DTADR value for the current transfer */
  63         volatile u32 dcmd;      /* DCMD value for the current transfer */
  64 } pxa_dma_desc;
  65
  66 typedef enum {
  67         DMA_PRIO_HIGH = 0,
  68         DMA_PRIO_MEDIUM = 1,
  69         DMA_PRIO_LOW = 2
  70 } pxa_dma_prio;
  71
  72 /*
  73  * DMA registration
  74  */
  75
  76 int __init pxa_init_dma(int irq, int num_ch);
  77
  78 int pxa_request_dma (char *name,
  79                          pxa_dma_prio prio,
  80                          void (*irq_handler)(int, void *),
  81                          void *data);
  82
  83 void pxa_free_dma (int dma_ch);
  84
  85 /*
  86  * Cooperation with pxa_dma + dmaengine while there remains at least one pxa
  87  * driver not converted to dmaengine.
  88  */
  89 #if defined(CONFIG_PXA_DMA)
  90 extern int pxad_toggle_reserved_channel(int legacy_channel);
  91 #else
  92 static inline int pxad_toggle_reserved_channel(int legacy_channel)
  93 {
  94         return 0;
  95 }
  96 #endif
  97
  98 extern void __init pxa2xx_set_dmac_info(int nb_channels);
  99
 100 #endif /* __PLAT_DMA_H */