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io_uring: reset -EBUSY error when io sq thread is waken up
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1 # SPDX-License-Identifier: GPL-2.0-only
2 config ARM64
3 def_bool y
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_DMA_PREP_COHERENT
15 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
16 select ARCH_HAS_FAST_MULTIPLIER
17 select ARCH_HAS_FORTIFY_SOURCE
18 select ARCH_HAS_GCOV_PROFILE_ALL
19 select ARCH_HAS_GIGANTIC_PAGE
20 select ARCH_HAS_KCOV
21 select ARCH_HAS_KEEPINITRD
22 select ARCH_HAS_MEMBARRIER_SYNC_CORE
23 select ARCH_HAS_PTE_DEVMAP
24 select ARCH_HAS_PTE_SPECIAL
25 select ARCH_HAS_SETUP_DMA_OPS
26 select ARCH_HAS_SET_DIRECT_MAP
27 select ARCH_HAS_SET_MEMORY
28 select ARCH_HAS_STRICT_KERNEL_RWX
29 select ARCH_HAS_STRICT_MODULE_RWX
30 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
31 select ARCH_HAS_SYNC_DMA_FOR_CPU
32 select ARCH_HAS_SYSCALL_WRAPPER
33 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
34 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
35 select ARCH_HAVE_NMI_SAFE_CMPXCHG
36 select ARCH_INLINE_READ_LOCK if !PREEMPTION
37 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
38 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
39 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
40 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
41 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
42 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
43 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
44 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
45 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
46 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
47 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
48 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
49 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
50 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
51 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
52 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
53 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
54 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
55 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
56 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
58 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
59 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
61 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
62 select ARCH_KEEP_MEMBLOCK
63 select ARCH_USE_CMPXCHG_LOCKREF
64 select ARCH_USE_QUEUED_RWLOCKS
65 select ARCH_USE_QUEUED_SPINLOCKS
66 select ARCH_SUPPORTS_MEMORY_FAILURE
67 select ARCH_SUPPORTS_ATOMIC_RMW
68 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
69 select ARCH_SUPPORTS_NUMA_BALANCING
70 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
71 select ARCH_WANT_DEFAULT_BPF_JIT
72 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
73 select ARCH_WANT_FRAME_POINTERS
74 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
75 select ARCH_HAS_UBSAN_SANITIZE_ALL
76 select ARM_AMBA
77 select ARM_ARCH_TIMER
78 select ARM_GIC
79 select AUDIT_ARCH_COMPAT_GENERIC
80 select ARM_GIC_V2M if PCI
81 select ARM_GIC_V3
82 select ARM_GIC_V3_ITS if PCI
83 select ARM_PSCI_FW
84 select BUILDTIME_TABLE_SORT
85 select CLONE_BACKWARDS
86 select COMMON_CLK
87 select CPU_PM if (SUSPEND || CPU_IDLE)
88 select CRC32
89 select DCACHE_WORD_ACCESS
90 select DMA_DIRECT_REMAP
91 select EDAC_SUPPORT
92 select FRAME_POINTER
93 select GENERIC_ALLOCATOR
94 select GENERIC_ARCH_TOPOLOGY
95 select GENERIC_CLOCKEVENTS
96 select GENERIC_CLOCKEVENTS_BROADCAST
97 select GENERIC_CPU_AUTOPROBE
98 select GENERIC_CPU_VULNERABILITIES
99 select GENERIC_EARLY_IOREMAP
100 select GENERIC_IDLE_POLL_SETUP
101 select GENERIC_IRQ_MULTI_HANDLER
102 select GENERIC_IRQ_PROBE
103 select GENERIC_IRQ_SHOW
104 select GENERIC_IRQ_SHOW_LEVEL
105 select GENERIC_PCI_IOMAP
106 select GENERIC_PTDUMP
107 select GENERIC_SCHED_CLOCK
108 select GENERIC_SMP_IDLE_THREAD
109 select GENERIC_STRNCPY_FROM_USER
110 select GENERIC_STRNLEN_USER
111 select GENERIC_TIME_VSYSCALL
112 select GENERIC_GETTIMEOFDAY
113 select HANDLE_DOMAIN_IRQ
114 select HARDIRQS_SW_RESEND
115 select HAVE_PCI
116 select HAVE_ACPI_APEI if (ACPI && EFI)
117 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
118 select HAVE_ARCH_AUDITSYSCALL
119 select HAVE_ARCH_BITREVERSE
120 select HAVE_ARCH_COMPILER_H
121 select HAVE_ARCH_HUGE_VMAP
122 select HAVE_ARCH_JUMP_LABEL
123 select HAVE_ARCH_JUMP_LABEL_RELATIVE
124 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
125 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
126 select HAVE_ARCH_KGDB
127 select HAVE_ARCH_MMAP_RND_BITS
128 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
129 select HAVE_ARCH_PREL32_RELOCATIONS
130 select HAVE_ARCH_SECCOMP_FILTER
131 select HAVE_ARCH_STACKLEAK
132 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
133 select HAVE_ARCH_TRACEHOOK
134 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
135 select HAVE_ARCH_VMAP_STACK
136 select HAVE_ARM_SMCCC
137 select HAVE_ASM_MODVERSIONS
138 select HAVE_EBPF_JIT
139 select HAVE_C_RECORDMCOUNT
140 select HAVE_CMPXCHG_DOUBLE
141 select HAVE_CMPXCHG_LOCAL
142 select HAVE_CONTEXT_TRACKING
143 select HAVE_COPY_THREAD_TLS
144 select HAVE_DEBUG_BUGVERBOSE
145 select HAVE_DEBUG_KMEMLEAK
146 select HAVE_DMA_CONTIGUOUS
147 select HAVE_DYNAMIC_FTRACE
148 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
149 if $(cc-option,-fpatchable-function-entry=2)
150 select HAVE_EFFICIENT_UNALIGNED_ACCESS
151 select HAVE_FAST_GUP
152 select HAVE_FTRACE_MCOUNT_RECORD
153 select HAVE_FUNCTION_TRACER
154 select HAVE_FUNCTION_ERROR_INJECTION
155 select HAVE_FUNCTION_GRAPH_TRACER
156 select HAVE_GCC_PLUGINS
157 select HAVE_HW_BREAKPOINT if PERF_EVENTS
158 select HAVE_IRQ_TIME_ACCOUNTING
159 select HAVE_MEMBLOCK_NODE_MAP if NUMA
160 select HAVE_NMI
161 select HAVE_PATA_PLATFORM
162 select HAVE_PERF_EVENTS
163 select HAVE_PERF_REGS
164 select HAVE_PERF_USER_STACK_DUMP
165 select HAVE_REGS_AND_STACK_ACCESS_API
166 select HAVE_FUNCTION_ARG_ACCESS_API
167 select HAVE_FUTEX_CMPXCHG if FUTEX
168 select MMU_GATHER_RCU_TABLE_FREE
169 select HAVE_RSEQ
170 select HAVE_STACKPROTECTOR
171 select HAVE_SYSCALL_TRACEPOINTS
172 select HAVE_KPROBES
173 select HAVE_KRETPROBES
174 select HAVE_GENERIC_VDSO
175 select IOMMU_DMA if IOMMU_SUPPORT
176 select IRQ_DOMAIN
177 select IRQ_FORCED_THREADING
178 select MODULES_USE_ELF_RELA
179 select NEED_DMA_MAP_STATE
180 select NEED_SG_DMA_LENGTH
181 select OF
182 select OF_EARLY_FLATTREE
183 select PCI_DOMAINS_GENERIC if PCI
184 select PCI_ECAM if (ACPI && PCI)
185 select PCI_SYSCALL if PCI
186 select POWER_RESET
187 select POWER_SUPPLY
188 select SPARSE_IRQ
189 select SWIOTLB
190 select SYSCTL_EXCEPTION_TRACE
191 select THREAD_INFO_IN_TASK
192 help
193 ARM 64-bit (AArch64) Linux support.
194
195 config 64BIT
196 def_bool y
197
198 config MMU
199 def_bool y
200
201 config ARM64_PAGE_SHIFT
202 int
203 default 16 if ARM64_64K_PAGES
204 default 14 if ARM64_16K_PAGES
205 default 12
206
207 config ARM64_CONT_SHIFT
208 int
209 default 5 if ARM64_64K_PAGES
210 default 7 if ARM64_16K_PAGES
211 default 4
212
213 config ARCH_MMAP_RND_BITS_MIN
214 default 14 if ARM64_64K_PAGES
215 default 16 if ARM64_16K_PAGES
216 default 18
217
218 # max bits determined by the following formula:
219 # VA_BITS - PAGE_SHIFT - 3
220 config ARCH_MMAP_RND_BITS_MAX
221 default 19 if ARM64_VA_BITS=36
222 default 24 if ARM64_VA_BITS=39
223 default 27 if ARM64_VA_BITS=42
224 default 30 if ARM64_VA_BITS=47
225 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
226 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
227 default 33 if ARM64_VA_BITS=48
228 default 14 if ARM64_64K_PAGES
229 default 16 if ARM64_16K_PAGES
230 default 18
231
232 config ARCH_MMAP_RND_COMPAT_BITS_MIN
233 default 7 if ARM64_64K_PAGES
234 default 9 if ARM64_16K_PAGES
235 default 11
236
237 config ARCH_MMAP_RND_COMPAT_BITS_MAX
238 default 16
239
240 config NO_IOPORT_MAP
241 def_bool y if !PCI
242
243 config STACKTRACE_SUPPORT
244 def_bool y
245
246 config ILLEGAL_POINTER_VALUE
247 hex
248 default 0xdead000000000000
249
250 config LOCKDEP_SUPPORT
251 def_bool y
252
253 config TRACE_IRQFLAGS_SUPPORT
254 def_bool y
255
256 config GENERIC_BUG
257 def_bool y
258 depends on BUG
259
260 config GENERIC_BUG_RELATIVE_POINTERS
261 def_bool y
262 depends on GENERIC_BUG
263
264 config GENERIC_HWEIGHT
265 def_bool y
266
267 config GENERIC_CSUM
268 def_bool y
269
270 config GENERIC_CALIBRATE_DELAY
271 def_bool y
272
273 config ZONE_DMA
274 bool "Support DMA zone" if EXPERT
275 default y
276
277 config ZONE_DMA32
278 bool "Support DMA32 zone" if EXPERT
279 default y
280
281 config ARCH_ENABLE_MEMORY_HOTPLUG
282 def_bool y
283
284 config ARCH_ENABLE_MEMORY_HOTREMOVE
285 def_bool y
286
287 config SMP
288 def_bool y
289
290 config KERNEL_MODE_NEON
291 def_bool y
292
293 config FIX_EARLYCON_MEM
294 def_bool y
295
296 config PGTABLE_LEVELS
297 int
298 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
299 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
300 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
301 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
302 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
303 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
304
305 config ARCH_SUPPORTS_UPROBES
306 def_bool y
307
308 config ARCH_PROC_KCORE_TEXT
309 def_bool y
310
311 config BROKEN_GAS_INST
312 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
313
314 config KASAN_SHADOW_OFFSET
315 hex
316 depends on KASAN
317 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
318 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
319 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
320 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
321 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
322 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
323 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
324 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
325 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
326 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
327 default 0xffffffffffffffff
328
329 source "arch/arm64/Kconfig.platforms"
330
331 menu "Kernel Features"
332
333 menu "ARM errata workarounds via the alternatives framework"
334
335 config ARM64_WORKAROUND_CLEAN_CACHE
336 bool
337
338 config ARM64_ERRATUM_826319
339 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
340 default y
341 select ARM64_WORKAROUND_CLEAN_CACHE
342 help
343 This option adds an alternative code sequence to work around ARM
344 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
345 AXI master interface and an L2 cache.
346
347 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
348 and is unable to accept a certain write via this interface, it will
349 not progress on read data presented on the read data channel and the
350 system can deadlock.
351
352 The workaround promotes data cache clean instructions to
353 data cache clean-and-invalidate.
354 Please note that this does not necessarily enable the workaround,
355 as it depends on the alternative framework, which will only patch
356 the kernel if an affected CPU is detected.
357
358 If unsure, say Y.
359
360 config ARM64_ERRATUM_827319
361 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
362 default y
363 select ARM64_WORKAROUND_CLEAN_CACHE
364 help
365 This option adds an alternative code sequence to work around ARM
366 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
367 master interface and an L2 cache.
368
369 Under certain conditions this erratum can cause a clean line eviction
370 to occur at the same time as another transaction to the same address
371 on the AMBA 5 CHI interface, which can cause data corruption if the
372 interconnect reorders the two transactions.
373
374 The workaround promotes data cache clean instructions to
375 data cache clean-and-invalidate.
376 Please note that this does not necessarily enable the workaround,
377 as it depends on the alternative framework, which will only patch
378 the kernel if an affected CPU is detected.
379
380 If unsure, say Y.
381
382 config ARM64_ERRATUM_824069
383 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
384 default y
385 select ARM64_WORKAROUND_CLEAN_CACHE
386 help
387 This option adds an alternative code sequence to work around ARM
388 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
389 to a coherent interconnect.
390
391 If a Cortex-A53 processor is executing a store or prefetch for
392 write instruction at the same time as a processor in another
393 cluster is executing a cache maintenance operation to the same
394 address, then this erratum might cause a clean cache line to be
395 incorrectly marked as dirty.
396
397 The workaround promotes data cache clean instructions to
398 data cache clean-and-invalidate.
399 Please note that this option does not necessarily enable the
400 workaround, as it depends on the alternative framework, which will
401 only patch the kernel if an affected CPU is detected.
402
403 If unsure, say Y.
404
405 config ARM64_ERRATUM_819472
406 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
407 default y
408 select ARM64_WORKAROUND_CLEAN_CACHE
409 help
410 This option adds an alternative code sequence to work around ARM
411 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
412 present when it is connected to a coherent interconnect.
413
414 If the processor is executing a load and store exclusive sequence at
415 the same time as a processor in another cluster is executing a cache
416 maintenance operation to the same address, then this erratum might
417 cause data corruption.
418
419 The workaround promotes data cache clean instructions to
420 data cache clean-and-invalidate.
421 Please note that this does not necessarily enable the workaround,
422 as it depends on the alternative framework, which will only patch
423 the kernel if an affected CPU is detected.
424
425 If unsure, say Y.
426
427 config ARM64_ERRATUM_832075
428 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
429 default y
430 help
431 This option adds an alternative code sequence to work around ARM
432 erratum 832075 on Cortex-A57 parts up to r1p2.
433
434 Affected Cortex-A57 parts might deadlock when exclusive load/store
435 instructions to Write-Back memory are mixed with Device loads.
436
437 The workaround is to promote device loads to use Load-Acquire
438 semantics.
439 Please note that this does not necessarily enable the workaround,
440 as it depends on the alternative framework, which will only patch
441 the kernel if an affected CPU is detected.
442
443 If unsure, say Y.
444
445 config ARM64_ERRATUM_834220
446 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
447 depends on KVM
448 default y
449 help
450 This option adds an alternative code sequence to work around ARM
451 erratum 834220 on Cortex-A57 parts up to r1p2.
452
453 Affected Cortex-A57 parts might report a Stage 2 translation
454 fault as the result of a Stage 1 fault for load crossing a
455 page boundary when there is a permission or device memory
456 alignment fault at Stage 1 and a translation fault at Stage 2.
457
458 The workaround is to verify that the Stage 1 translation
459 doesn't generate a fault before handling the Stage 2 fault.
460 Please note that this does not necessarily enable the workaround,
461 as it depends on the alternative framework, which will only patch
462 the kernel if an affected CPU is detected.
463
464 If unsure, say Y.
465
466 config ARM64_ERRATUM_845719
467 bool "Cortex-A53: 845719: a load might read incorrect data"
468 depends on COMPAT
469 default y
470 help
471 This option adds an alternative code sequence to work around ARM
472 erratum 845719 on Cortex-A53 parts up to r0p4.
473
474 When running a compat (AArch32) userspace on an affected Cortex-A53
475 part, a load at EL0 from a virtual address that matches the bottom 32
476 bits of the virtual address used by a recent load at (AArch64) EL1
477 might return incorrect data.
478
479 The workaround is to write the contextidr_el1 register on exception
480 return to a 32-bit task.
481 Please note that this does not necessarily enable the workaround,
482 as it depends on the alternative framework, which will only patch
483 the kernel if an affected CPU is detected.
484
485 If unsure, say Y.
486
487 config ARM64_ERRATUM_843419
488 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
489 default y
490 select ARM64_MODULE_PLTS if MODULES
491 help
492 This option links the kernel with '--fix-cortex-a53-843419' and
493 enables PLT support to replace certain ADRP instructions, which can
494 cause subsequent memory accesses to use an incorrect address on
495 Cortex-A53 parts up to r0p4.
496
497 If unsure, say Y.
498
499 config ARM64_ERRATUM_1024718
500 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
501 default y
502 help
503 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
504
505 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
506 update of the hardware dirty bit when the DBM/AP bits are updated
507 without a break-before-make. The workaround is to disable the usage
508 of hardware DBM locally on the affected cores. CPUs not affected by
509 this erratum will continue to use the feature.
510
511 If unsure, say Y.
512
513 config ARM64_ERRATUM_1418040
514 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
515 default y
516 depends on COMPAT
517 help
518 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
519 errata 1188873 and 1418040.
520
521 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
522 cause register corruption when accessing the timer registers
523 from AArch32 userspace.
524
525 If unsure, say Y.
526
527 config ARM64_WORKAROUND_SPECULATIVE_AT_VHE
528 bool
529
530 config ARM64_ERRATUM_1165522
531 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
532 default y
533 select ARM64_WORKAROUND_SPECULATIVE_AT_VHE
534 help
535 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
536
537 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
538 corrupted TLBs by speculating an AT instruction during a guest
539 context switch.
540
541 If unsure, say Y.
542
543 config ARM64_ERRATUM_1530923
544 bool "Cortex-A55: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
545 default y
546 select ARM64_WORKAROUND_SPECULATIVE_AT_VHE
547 help
548 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
549
550 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
551 corrupted TLBs by speculating an AT instruction during a guest
552 context switch.
553
554 If unsure, say Y.
555
556 config ARM64_ERRATUM_1286807
557 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
558 default y
559 select ARM64_WORKAROUND_REPEAT_TLBI
560 help
561 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
562
563 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
564 address for a cacheable mapping of a location is being
565 accessed by a core while another core is remapping the virtual
566 address to a new physical page using the recommended
567 break-before-make sequence, then under very rare circumstances
568 TLBI+DSB completes before a read using the translation being
569 invalidated has been observed by other observers. The
570 workaround repeats the TLBI+DSB operation.
571
572 config ARM64_WORKAROUND_SPECULATIVE_AT_NVHE
573 bool
574
575 config ARM64_ERRATUM_1319367
576 bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
577 default y
578 select ARM64_WORKAROUND_SPECULATIVE_AT_NVHE
579 help
580 This option adds work arounds for ARM Cortex-A57 erratum 1319537
581 and A72 erratum 1319367
582
583 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
584 speculating an AT instruction during a guest context switch.
585
586 If unsure, say Y.
587
588 config ARM64_ERRATUM_1463225
589 bool "Cortex-A76: Software Step might prevent interrupt recognition"
590 default y
591 help
592 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
593
594 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
595 of a system call instruction (SVC) can prevent recognition of
596 subsequent interrupts when software stepping is disabled in the
597 exception handler of the system call and either kernel debugging
598 is enabled or VHE is in use.
599
600 Work around the erratum by triggering a dummy step exception
601 when handling a system call from a task that is being stepped
602 in a VHE configuration of the kernel.
603
604 If unsure, say Y.
605
606 config ARM64_ERRATUM_1542419
607 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
608 default y
609 help
610 This option adds a workaround for ARM Neoverse-N1 erratum
611 1542419.
612
613 Affected Neoverse-N1 cores could execute a stale instruction when
614 modified by another CPU. The workaround depends on a firmware
615 counterpart.
616
617 Workaround the issue by hiding the DIC feature from EL0. This
618 forces user-space to perform cache maintenance.
619
620 If unsure, say Y.
621
622 config CAVIUM_ERRATUM_22375
623 bool "Cavium erratum 22375, 24313"
624 default y
625 help
626 Enable workaround for errata 22375 and 24313.
627
628 This implements two gicv3-its errata workarounds for ThunderX. Both
629 with a small impact affecting only ITS table allocation.
630
631 erratum 22375: only alloc 8MB table size
632 erratum 24313: ignore memory access type
633
634 The fixes are in ITS initialization and basically ignore memory access
635 type and table size provided by the TYPER and BASER registers.
636
637 If unsure, say Y.
638
639 config CAVIUM_ERRATUM_23144
640 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
641 depends on NUMA
642 default y
643 help
644 ITS SYNC command hang for cross node io and collections/cpu mapping.
645
646 If unsure, say Y.
647
648 config CAVIUM_ERRATUM_23154
649 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
650 default y
651 help
652 The gicv3 of ThunderX requires a modified version for
653 reading the IAR status to ensure data synchronization
654 (access to icc_iar1_el1 is not sync'ed before and after).
655
656 If unsure, say Y.
657
658 config CAVIUM_ERRATUM_27456
659 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
660 default y
661 help
662 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
663 instructions may cause the icache to become corrupted if it
664 contains data for a non-current ASID. The fix is to
665 invalidate the icache when changing the mm context.
666
667 If unsure, say Y.
668
669 config CAVIUM_ERRATUM_30115
670 bool "Cavium erratum 30115: Guest may disable interrupts in host"
671 default y
672 help
673 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
674 1.2, and T83 Pass 1.0, KVM guest execution may disable
675 interrupts in host. Trapping both GICv3 group-0 and group-1
676 accesses sidesteps the issue.
677
678 If unsure, say Y.
679
680 config CAVIUM_TX2_ERRATUM_219
681 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
682 default y
683 help
684 On Cavium ThunderX2, a load, store or prefetch instruction between a
685 TTBR update and the corresponding context synchronizing operation can
686 cause a spurious Data Abort to be delivered to any hardware thread in
687 the CPU core.
688
689 Work around the issue by avoiding the problematic code sequence and
690 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
691 trap handler performs the corresponding register access, skips the
692 instruction and ensures context synchronization by virtue of the
693 exception return.
694
695 If unsure, say Y.
696
697 config QCOM_FALKOR_ERRATUM_1003
698 bool "Falkor E1003: Incorrect translation due to ASID change"
699 default y
700 help
701 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
702 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
703 in TTBR1_EL1, this situation only occurs in the entry trampoline and
704 then only for entries in the walk cache, since the leaf translation
705 is unchanged. Work around the erratum by invalidating the walk cache
706 entries for the trampoline before entering the kernel proper.
707
708 config ARM64_WORKAROUND_REPEAT_TLBI
709 bool
710
711 config QCOM_FALKOR_ERRATUM_1009
712 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
713 default y
714 select ARM64_WORKAROUND_REPEAT_TLBI
715 help
716 On Falkor v1, the CPU may prematurely complete a DSB following a
717 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
718 one more time to fix the issue.
719
720 If unsure, say Y.
721
722 config QCOM_QDF2400_ERRATUM_0065
723 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
724 default y
725 help
726 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
727 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
728 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
729
730 If unsure, say Y.
731
732 config SOCIONEXT_SYNQUACER_PREITS
733 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
734 default y
735 help
736 Socionext Synquacer SoCs implement a separate h/w block to generate
737 MSI doorbell writes with non-zero values for the device ID.
738
739 If unsure, say Y.
740
741 config HISILICON_ERRATUM_161600802
742 bool "Hip07 161600802: Erroneous redistributor VLPI base"
743 default y
744 help
745 The HiSilicon Hip07 SoC uses the wrong redistributor base
746 when issued ITS commands such as VMOVP and VMAPP, and requires
747 a 128kB offset to be applied to the target address in this commands.
748
749 If unsure, say Y.
750
751 config QCOM_FALKOR_ERRATUM_E1041
752 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
753 default y
754 help
755 Falkor CPU may speculatively fetch instructions from an improper
756 memory location when MMU translation is changed from SCTLR_ELn[M]=1
757 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
758
759 If unsure, say Y.
760
761 config FUJITSU_ERRATUM_010001
762 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
763 default y
764 help
765 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
766 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
767 accesses may cause undefined fault (Data abort, DFSC=0b111111).
768 This fault occurs under a specific hardware condition when a
769 load/store instruction performs an address translation using:
770 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
771 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
772 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
773 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
774
775 The workaround is to ensure these bits are clear in TCR_ELx.
776 The workaround only affects the Fujitsu-A64FX.
777
778 If unsure, say Y.
779
780 endmenu
781
782
783 choice
784 prompt "Page size"
785 default ARM64_4K_PAGES
786 help
787 Page size (translation granule) configuration.
788
789 config ARM64_4K_PAGES
790 bool "4KB"
791 help
792 This feature enables 4KB pages support.
793
794 config ARM64_16K_PAGES
795 bool "16KB"
796 help
797 The system will use 16KB pages support. AArch32 emulation
798 requires applications compiled with 16K (or a multiple of 16K)
799 aligned segments.
800
801 config ARM64_64K_PAGES
802 bool "64KB"
803 help
804 This feature enables 64KB pages support (4KB by default)
805 allowing only two levels of page tables and faster TLB
806 look-up. AArch32 emulation requires applications compiled
807 with 64K aligned segments.
808
809 endchoice
810
811 choice
812 prompt "Virtual address space size"
813 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
814 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
815 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
816 help
817 Allows choosing one of multiple possible virtual address
818 space sizes. The level of translation table is determined by
819 a combination of page size and virtual address space size.
820
821 config ARM64_VA_BITS_36
822 bool "36-bit" if EXPERT
823 depends on ARM64_16K_PAGES
824
825 config ARM64_VA_BITS_39
826 bool "39-bit"
827 depends on ARM64_4K_PAGES
828
829 config ARM64_VA_BITS_42
830 bool "42-bit"
831 depends on ARM64_64K_PAGES
832
833 config ARM64_VA_BITS_47
834 bool "47-bit"
835 depends on ARM64_16K_PAGES
836
837 config ARM64_VA_BITS_48
838 bool "48-bit"
839
840 config ARM64_VA_BITS_52
841 bool "52-bit"
842 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
843 help
844 Enable 52-bit virtual addressing for userspace when explicitly
845 requested via a hint to mmap(). The kernel will also use 52-bit
846 virtual addresses for its own mappings (provided HW support for
847 this feature is available, otherwise it reverts to 48-bit).
848
849 NOTE: Enabling 52-bit virtual addressing in conjunction with
850 ARMv8.3 Pointer Authentication will result in the PAC being
851 reduced from 7 bits to 3 bits, which may have a significant
852 impact on its susceptibility to brute-force attacks.
853
854 If unsure, select 48-bit virtual addressing instead.
855
856 endchoice
857
858 config ARM64_FORCE_52BIT
859 bool "Force 52-bit virtual addresses for userspace"
860 depends on ARM64_VA_BITS_52 && EXPERT
861 help
862 For systems with 52-bit userspace VAs enabled, the kernel will attempt
863 to maintain compatibility with older software by providing 48-bit VAs
864 unless a hint is supplied to mmap.
865
866 This configuration option disables the 48-bit compatibility logic, and
867 forces all userspace addresses to be 52-bit on HW that supports it. One
868 should only enable this configuration option for stress testing userspace
869 memory management code. If unsure say N here.
870
871 config ARM64_VA_BITS
872 int
873 default 36 if ARM64_VA_BITS_36
874 default 39 if ARM64_VA_BITS_39
875 default 42 if ARM64_VA_BITS_42
876 default 47 if ARM64_VA_BITS_47
877 default 48 if ARM64_VA_BITS_48
878 default 52 if ARM64_VA_BITS_52
879
880 choice
881 prompt "Physical address space size"
882 default ARM64_PA_BITS_48
883 help
884 Choose the maximum physical address range that the kernel will
885 support.
886
887 config ARM64_PA_BITS_48
888 bool "48-bit"
889
890 config ARM64_PA_BITS_52
891 bool "52-bit (ARMv8.2)"
892 depends on ARM64_64K_PAGES
893 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
894 help
895 Enable support for a 52-bit physical address space, introduced as
896 part of the ARMv8.2-LPA extension.
897
898 With this enabled, the kernel will also continue to work on CPUs that
899 do not support ARMv8.2-LPA, but with some added memory overhead (and
900 minor performance overhead).
901
902 endchoice
903
904 config ARM64_PA_BITS
905 int
906 default 48 if ARM64_PA_BITS_48
907 default 52 if ARM64_PA_BITS_52
908
909 choice
910 prompt "Endianness"
911 default CPU_LITTLE_ENDIAN
912 help
913 Select the endianness of data accesses performed by the CPU. Userspace
914 applications will need to be compiled and linked for the endianness
915 that is selected here.
916
917 config CPU_BIG_ENDIAN
918 bool "Build big-endian kernel"
919 help
920 Say Y if you plan on running a kernel with a big-endian userspace.
921
922 config CPU_LITTLE_ENDIAN
923 bool "Build little-endian kernel"
924 help
925 Say Y if you plan on running a kernel with a little-endian userspace.
926 This is usually the case for distributions targeting arm64.
927
928 endchoice
929
930 config SCHED_MC
931 bool "Multi-core scheduler support"
932 help
933 Multi-core scheduler support improves the CPU scheduler's decision
934 making when dealing with multi-core CPU chips at a cost of slightly
935 increased overhead in some places. If unsure say N here.
936
937 config SCHED_SMT
938 bool "SMT scheduler support"
939 help
940 Improves the CPU scheduler's decision making when dealing with
941 MultiThreading at a cost of slightly increased overhead in some
942 places. If unsure say N here.
943
944 config NR_CPUS
945 int "Maximum number of CPUs (2-4096)"
946 range 2 4096
947 default "256"
948
949 config HOTPLUG_CPU
950 bool "Support for hot-pluggable CPUs"
951 select GENERIC_IRQ_MIGRATION
952 help
953 Say Y here to experiment with turning CPUs off and on. CPUs
954 can be controlled through /sys/devices/system/cpu.
955
956 # Common NUMA Features
957 config NUMA
958 bool "NUMA Memory Allocation and Scheduler Support"
959 select ACPI_NUMA if ACPI
960 select OF_NUMA
961 help
962 Enable NUMA (Non-Uniform Memory Access) support.
963
964 The kernel will try to allocate memory used by a CPU on the
965 local memory of the CPU and add some more
966 NUMA awareness to the kernel.
967
968 config NODES_SHIFT
969 int "Maximum NUMA Nodes (as a power of 2)"
970 range 1 10
971 default "2"
972 depends on NEED_MULTIPLE_NODES
973 help
974 Specify the maximum number of NUMA Nodes available on the target
975 system. Increases memory reserved to accommodate various tables.
976
977 config USE_PERCPU_NUMA_NODE_ID
978 def_bool y
979 depends on NUMA
980
981 config HAVE_SETUP_PER_CPU_AREA
982 def_bool y
983 depends on NUMA
984
985 config NEED_PER_CPU_EMBED_FIRST_CHUNK
986 def_bool y
987 depends on NUMA
988
989 config HOLES_IN_ZONE
990 def_bool y
991
992 source "kernel/Kconfig.hz"
993
994 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
995 def_bool y
996
997 config ARCH_SPARSEMEM_ENABLE
998 def_bool y
999 select SPARSEMEM_VMEMMAP_ENABLE
1000
1001 config ARCH_SPARSEMEM_DEFAULT
1002 def_bool ARCH_SPARSEMEM_ENABLE
1003
1004 config ARCH_SELECT_MEMORY_MODEL
1005 def_bool ARCH_SPARSEMEM_ENABLE
1006
1007 config ARCH_FLATMEM_ENABLE
1008 def_bool !NUMA
1009
1010 config HAVE_ARCH_PFN_VALID
1011 def_bool y
1012
1013 config HW_PERF_EVENTS
1014 def_bool y
1015 depends on ARM_PMU
1016
1017 config SYS_SUPPORTS_HUGETLBFS
1018 def_bool y
1019
1020 config ARCH_WANT_HUGE_PMD_SHARE
1021
1022 config ARCH_HAS_CACHE_LINE_SIZE
1023 def_bool y
1024
1025 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1026 def_bool y if PGTABLE_LEVELS > 2
1027
1028 config SECCOMP
1029 bool "Enable seccomp to safely compute untrusted bytecode"
1030 ---help---
1031 This kernel feature is useful for number crunching applications
1032 that may need to compute untrusted bytecode during their
1033 execution. By using pipes or other transports made available to
1034 the process as file descriptors supporting the read/write
1035 syscalls, it's possible to isolate those applications in
1036 their own address space using seccomp. Once seccomp is
1037 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1038 and the task is only allowed to execute a few safe syscalls
1039 defined by each seccomp mode.
1040
1041 config PARAVIRT
1042 bool "Enable paravirtualization code"
1043 help
1044 This changes the kernel so it can modify itself when it is run
1045 under a hypervisor, potentially improving performance significantly
1046 over full virtualization.
1047
1048 config PARAVIRT_TIME_ACCOUNTING
1049 bool "Paravirtual steal time accounting"
1050 select PARAVIRT
1051 help
1052 Select this option to enable fine granularity task steal time
1053 accounting. Time spent executing other tasks in parallel with
1054 the current vCPU is discounted from the vCPU power. To account for
1055 that, there can be a small performance impact.
1056
1057 If in doubt, say N here.
1058
1059 config KEXEC
1060 depends on PM_SLEEP_SMP
1061 select KEXEC_CORE
1062 bool "kexec system call"
1063 ---help---
1064 kexec is a system call that implements the ability to shutdown your
1065 current kernel, and to start another kernel. It is like a reboot
1066 but it is independent of the system firmware. And like a reboot
1067 you can start any kernel with it, not just Linux.
1068
1069 config KEXEC_FILE
1070 bool "kexec file based system call"
1071 select KEXEC_CORE
1072 help
1073 This is new version of kexec system call. This system call is
1074 file based and takes file descriptors as system call argument
1075 for kernel and initramfs as opposed to list of segments as
1076 accepted by previous system call.
1077
1078 config KEXEC_SIG
1079 bool "Verify kernel signature during kexec_file_load() syscall"
1080 depends on KEXEC_FILE
1081 help
1082 Select this option to verify a signature with loaded kernel
1083 image. If configured, any attempt of loading a image without
1084 valid signature will fail.
1085
1086 In addition to that option, you need to enable signature
1087 verification for the corresponding kernel image type being
1088 loaded in order for this to work.
1089
1090 config KEXEC_IMAGE_VERIFY_SIG
1091 bool "Enable Image signature verification support"
1092 default y
1093 depends on KEXEC_SIG
1094 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1095 help
1096 Enable Image signature verification support.
1097
1098 comment "Support for PE file signature verification disabled"
1099 depends on KEXEC_SIG
1100 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1101
1102 config CRASH_DUMP
1103 bool "Build kdump crash kernel"
1104 help
1105 Generate crash dump after being started by kexec. This should
1106 be normally only set in special crash dump kernels which are
1107 loaded in the main kernel with kexec-tools into a specially
1108 reserved region and then later executed after a crash by
1109 kdump/kexec.
1110
1111 For more details see Documentation/admin-guide/kdump/kdump.rst
1112
1113 config XEN_DOM0
1114 def_bool y
1115 depends on XEN
1116
1117 config XEN
1118 bool "Xen guest support on ARM64"
1119 depends on ARM64 && OF
1120 select SWIOTLB_XEN
1121 select PARAVIRT
1122 help
1123 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1124
1125 config FORCE_MAX_ZONEORDER
1126 int
1127 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1128 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1129 default "11"
1130 help
1131 The kernel memory allocator divides physically contiguous memory
1132 blocks into "zones", where each zone is a power of two number of
1133 pages. This option selects the largest power of two that the kernel
1134 keeps in the memory allocator. If you need to allocate very large
1135 blocks of physically contiguous memory, then you may need to
1136 increase this value.
1137
1138 This config option is actually maximum order plus one. For example,
1139 a value of 11 means that the largest free memory block is 2^10 pages.
1140
1141 We make sure that we can allocate upto a HugePage size for each configuration.
1142 Hence we have :
1143 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1144
1145 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1146 4M allocations matching the default size used by generic code.
1147
1148 config UNMAP_KERNEL_AT_EL0
1149 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1150 default y
1151 help
1152 Speculation attacks against some high-performance processors can
1153 be used to bypass MMU permission checks and leak kernel data to
1154 userspace. This can be defended against by unmapping the kernel
1155 when running in userspace, mapping it back in on exception entry
1156 via a trampoline page in the vector table.
1157
1158 If unsure, say Y.
1159
1160 config HARDEN_BRANCH_PREDICTOR
1161 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1162 default y
1163 help
1164 Speculation attacks against some high-performance processors rely on
1165 being able to manipulate the branch predictor for a victim context by
1166 executing aliasing branches in the attacker context. Such attacks
1167 can be partially mitigated against by clearing internal branch
1168 predictor state and limiting the prediction logic in some situations.
1169
1170 This config option will take CPU-specific actions to harden the
1171 branch predictor against aliasing attacks and may rely on specific
1172 instruction sequences or control bits being set by the system
1173 firmware.
1174
1175 If unsure, say Y.
1176
1177 config HARDEN_EL2_VECTORS
1178 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1179 default y
1180 help
1181 Speculation attacks against some high-performance processors can
1182 be used to leak privileged information such as the vector base
1183 register, resulting in a potential defeat of the EL2 layout
1184 randomization.
1185
1186 This config option will map the vectors to a fixed location,
1187 independent of the EL2 code mapping, so that revealing VBAR_EL2
1188 to an attacker does not give away any extra information. This
1189 only gets enabled on affected CPUs.
1190
1191 If unsure, say Y.
1192
1193 config ARM64_SSBD
1194 bool "Speculative Store Bypass Disable" if EXPERT
1195 default y
1196 help
1197 This enables mitigation of the bypassing of previous stores
1198 by speculative loads.
1199
1200 If unsure, say Y.
1201
1202 config RODATA_FULL_DEFAULT_ENABLED
1203 bool "Apply r/o permissions of VM areas also to their linear aliases"
1204 default y
1205 help
1206 Apply read-only attributes of VM areas to the linear alias of
1207 the backing pages as well. This prevents code or read-only data
1208 from being modified (inadvertently or intentionally) via another
1209 mapping of the same memory page. This additional enhancement can
1210 be turned off at runtime by passing rodata=[off|on] (and turned on
1211 with rodata=full if this option is set to 'n')
1212
1213 This requires the linear region to be mapped down to pages,
1214 which may adversely affect performance in some cases.
1215
1216 config ARM64_SW_TTBR0_PAN
1217 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1218 help
1219 Enabling this option prevents the kernel from accessing
1220 user-space memory directly by pointing TTBR0_EL1 to a reserved
1221 zeroed area and reserved ASID. The user access routines
1222 restore the valid TTBR0_EL1 temporarily.
1223
1224 config ARM64_TAGGED_ADDR_ABI
1225 bool "Enable the tagged user addresses syscall ABI"
1226 default y
1227 help
1228 When this option is enabled, user applications can opt in to a
1229 relaxed ABI via prctl() allowing tagged addresses to be passed
1230 to system calls as pointer arguments. For details, see
1231 Documentation/arm64/tagged-address-abi.rst.
1232
1233 menuconfig COMPAT
1234 bool "Kernel support for 32-bit EL0"
1235 depends on ARM64_4K_PAGES || EXPERT
1236 select COMPAT_BINFMT_ELF if BINFMT_ELF
1237 select HAVE_UID16
1238 select OLD_SIGSUSPEND3
1239 select COMPAT_OLD_SIGACTION
1240 help
1241 This option enables support for a 32-bit EL0 running under a 64-bit
1242 kernel at EL1. AArch32-specific components such as system calls,
1243 the user helper functions, VFP support and the ptrace interface are
1244 handled appropriately by the kernel.
1245
1246 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1247 that you will only be able to execute AArch32 binaries that were compiled
1248 with page size aligned segments.
1249
1250 If you want to execute 32-bit userspace applications, say Y.
1251
1252 if COMPAT
1253
1254 config KUSER_HELPERS
1255 bool "Enable kuser helpers page for 32-bit applications"
1256 default y
1257 help
1258 Warning: disabling this option may break 32-bit user programs.
1259
1260 Provide kuser helpers to compat tasks. The kernel provides
1261 helper code to userspace in read only form at a fixed location
1262 to allow userspace to be independent of the CPU type fitted to
1263 the system. This permits binaries to be run on ARMv4 through
1264 to ARMv8 without modification.
1265
1266 See Documentation/arm/kernel_user_helpers.rst for details.
1267
1268 However, the fixed address nature of these helpers can be used
1269 by ROP (return orientated programming) authors when creating
1270 exploits.
1271
1272 If all of the binaries and libraries which run on your platform
1273 are built specifically for your platform, and make no use of
1274 these helpers, then you can turn this option off to hinder
1275 such exploits. However, in that case, if a binary or library
1276 relying on those helpers is run, it will not function correctly.
1277
1278 Say N here only if you are absolutely certain that you do not
1279 need these helpers; otherwise, the safe option is to say Y.
1280
1281 config COMPAT_VDSO
1282 bool "Enable vDSO for 32-bit applications"
1283 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1284 select GENERIC_COMPAT_VDSO
1285 default y
1286 help
1287 Place in the process address space of 32-bit applications an
1288 ELF shared object providing fast implementations of gettimeofday
1289 and clock_gettime.
1290
1291 You must have a 32-bit build of glibc 2.22 or later for programs
1292 to seamlessly take advantage of this.
1293
1294 menuconfig ARMV8_DEPRECATED
1295 bool "Emulate deprecated/obsolete ARMv8 instructions"
1296 depends on SYSCTL
1297 help
1298 Legacy software support may require certain instructions
1299 that have been deprecated or obsoleted in the architecture.
1300
1301 Enable this config to enable selective emulation of these
1302 features.
1303
1304 If unsure, say Y
1305
1306 if ARMV8_DEPRECATED
1307
1308 config SWP_EMULATION
1309 bool "Emulate SWP/SWPB instructions"
1310 help
1311 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1312 they are always undefined. Say Y here to enable software
1313 emulation of these instructions for userspace using LDXR/STXR.
1314
1315 In some older versions of glibc [<=2.8] SWP is used during futex
1316 trylock() operations with the assumption that the code will not
1317 be preempted. This invalid assumption may be more likely to fail
1318 with SWP emulation enabled, leading to deadlock of the user
1319 application.
1320
1321 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1322 on an external transaction monitoring block called a global
1323 monitor to maintain update atomicity. If your system does not
1324 implement a global monitor, this option can cause programs that
1325 perform SWP operations to uncached memory to deadlock.
1326
1327 If unsure, say Y
1328
1329 config CP15_BARRIER_EMULATION
1330 bool "Emulate CP15 Barrier instructions"
1331 help
1332 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1333 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1334 strongly recommended to use the ISB, DSB, and DMB
1335 instructions instead.
1336
1337 Say Y here to enable software emulation of these
1338 instructions for AArch32 userspace code. When this option is
1339 enabled, CP15 barrier usage is traced which can help
1340 identify software that needs updating.
1341
1342 If unsure, say Y
1343
1344 config SETEND_EMULATION
1345 bool "Emulate SETEND instruction"
1346 help
1347 The SETEND instruction alters the data-endianness of the
1348 AArch32 EL0, and is deprecated in ARMv8.
1349
1350 Say Y here to enable software emulation of the instruction
1351 for AArch32 userspace code.
1352
1353 Note: All the cpus on the system must have mixed endian support at EL0
1354 for this feature to be enabled. If a new CPU - which doesn't support mixed
1355 endian - is hotplugged in after this feature has been enabled, there could
1356 be unexpected results in the applications.
1357
1358 If unsure, say Y
1359 endif
1360
1361 endif
1362
1363 menu "ARMv8.1 architectural features"
1364
1365 config ARM64_HW_AFDBM
1366 bool "Support for hardware updates of the Access and Dirty page flags"
1367 default y
1368 help
1369 The ARMv8.1 architecture extensions introduce support for
1370 hardware updates of the access and dirty information in page
1371 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1372 capable processors, accesses to pages with PTE_AF cleared will
1373 set this bit instead of raising an access flag fault.
1374 Similarly, writes to read-only pages with the DBM bit set will
1375 clear the read-only bit (AP[2]) instead of raising a
1376 permission fault.
1377
1378 Kernels built with this configuration option enabled continue
1379 to work on pre-ARMv8.1 hardware and the performance impact is
1380 minimal. If unsure, say Y.
1381
1382 config ARM64_PAN
1383 bool "Enable support for Privileged Access Never (PAN)"
1384 default y
1385 help
1386 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1387 prevents the kernel or hypervisor from accessing user-space (EL0)
1388 memory directly.
1389
1390 Choosing this option will cause any unprotected (not using
1391 copy_to_user et al) memory access to fail with a permission fault.
1392
1393 The feature is detected at runtime, and will remain as a 'nop'
1394 instruction if the cpu does not implement the feature.
1395
1396 config ARM64_LSE_ATOMICS
1397 bool
1398 default ARM64_USE_LSE_ATOMICS
1399 depends on $(as-instr,.arch_extension lse)
1400
1401 config ARM64_USE_LSE_ATOMICS
1402 bool "Atomic instructions"
1403 depends on JUMP_LABEL
1404 default y
1405 help
1406 As part of the Large System Extensions, ARMv8.1 introduces new
1407 atomic instructions that are designed specifically to scale in
1408 very large systems.
1409
1410 Say Y here to make use of these instructions for the in-kernel
1411 atomic routines. This incurs a small overhead on CPUs that do
1412 not support these instructions and requires the kernel to be
1413 built with binutils >= 2.25 in order for the new instructions
1414 to be used.
1415
1416 config ARM64_VHE
1417 bool "Enable support for Virtualization Host Extensions (VHE)"
1418 default y
1419 help
1420 Virtualization Host Extensions (VHE) allow the kernel to run
1421 directly at EL2 (instead of EL1) on processors that support
1422 it. This leads to better performance for KVM, as they reduce
1423 the cost of the world switch.
1424
1425 Selecting this option allows the VHE feature to be detected
1426 at runtime, and does not affect processors that do not
1427 implement this feature.
1428
1429 endmenu
1430
1431 menu "ARMv8.2 architectural features"
1432
1433 config ARM64_UAO
1434 bool "Enable support for User Access Override (UAO)"
1435 default y
1436 help
1437 User Access Override (UAO; part of the ARMv8.2 Extensions)
1438 causes the 'unprivileged' variant of the load/store instructions to
1439 be overridden to be privileged.
1440
1441 This option changes get_user() and friends to use the 'unprivileged'
1442 variant of the load/store instructions. This ensures that user-space
1443 really did have access to the supplied memory. When addr_limit is
1444 set to kernel memory the UAO bit will be set, allowing privileged
1445 access to kernel memory.
1446
1447 Choosing this option will cause copy_to_user() et al to use user-space
1448 memory permissions.
1449
1450 The feature is detected at runtime, the kernel will use the
1451 regular load/store instructions if the cpu does not implement the
1452 feature.
1453
1454 config ARM64_PMEM
1455 bool "Enable support for persistent memory"
1456 select ARCH_HAS_PMEM_API
1457 select ARCH_HAS_UACCESS_FLUSHCACHE
1458 help
1459 Say Y to enable support for the persistent memory API based on the
1460 ARMv8.2 DCPoP feature.
1461
1462 The feature is detected at runtime, and the kernel will use DC CVAC
1463 operations if DC CVAP is not supported (following the behaviour of
1464 DC CVAP itself if the system does not define a point of persistence).
1465
1466 config ARM64_RAS_EXTN
1467 bool "Enable support for RAS CPU Extensions"
1468 default y
1469 help
1470 CPUs that support the Reliability, Availability and Serviceability
1471 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1472 errors, classify them and report them to software.
1473
1474 On CPUs with these extensions system software can use additional
1475 barriers to determine if faults are pending and read the
1476 classification from a new set of registers.
1477
1478 Selecting this feature will allow the kernel to use these barriers
1479 and access the new registers if the system supports the extension.
1480 Platform RAS features may additionally depend on firmware support.
1481
1482 config ARM64_CNP
1483 bool "Enable support for Common Not Private (CNP) translations"
1484 default y
1485 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1486 help
1487 Common Not Private (CNP) allows translation table entries to
1488 be shared between different PEs in the same inner shareable
1489 domain, so the hardware can use this fact to optimise the
1490 caching of such entries in the TLB.
1491
1492 Selecting this option allows the CNP feature to be detected
1493 at runtime, and does not affect PEs that do not implement
1494 this feature.
1495
1496 endmenu
1497
1498 menu "ARMv8.3 architectural features"
1499
1500 config ARM64_PTR_AUTH
1501 bool "Enable support for pointer authentication"
1502 default y
1503 depends on !KVM || ARM64_VHE
1504 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1505 # GCC 9.1 and later inserts a .note.gnu.property section note for PAC
1506 # which is only understood by binutils starting with version 2.33.1.
1507 depends on !CC_IS_GCC || GCC_VERSION < 90100 || LD_VERSION >= 233010000
1508 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1509 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1510 help
1511 Pointer authentication (part of the ARMv8.3 Extensions) provides
1512 instructions for signing and authenticating pointers against secret
1513 keys, which can be used to mitigate Return Oriented Programming (ROP)
1514 and other attacks.
1515
1516 This option enables these instructions at EL0 (i.e. for userspace).
1517 Choosing this option will cause the kernel to initialise secret keys
1518 for each process at exec() time, with these keys being
1519 context-switched along with the process.
1520
1521 If the compiler supports the -mbranch-protection or
1522 -msign-return-address flag (e.g. GCC 7 or later), then this option
1523 will also cause the kernel itself to be compiled with return address
1524 protection. In this case, and if the target hardware is known to
1525 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1526 disabled with minimal loss of protection.
1527
1528 The feature is detected at runtime. If the feature is not present in
1529 hardware it will not be advertised to userspace/KVM guest nor will it
1530 be enabled. However, KVM guest also require VHE mode and hence
1531 CONFIG_ARM64_VHE=y option to use this feature.
1532
1533 If the feature is present on the boot CPU but not on a late CPU, then
1534 the late CPU will be parked. Also, if the boot CPU does not have
1535 address auth and the late CPU has then the late CPU will still boot
1536 but with the feature disabled. On such a system, this option should
1537 not be selected.
1538
1539 This feature works with FUNCTION_GRAPH_TRACER option only if
1540 DYNAMIC_FTRACE_WITH_REGS is enabled.
1541
1542 config CC_HAS_BRANCH_PROT_PAC_RET
1543 # GCC 9 or later, clang 8 or later
1544 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1545
1546 config CC_HAS_SIGN_RETURN_ADDRESS
1547 # GCC 7, 8
1548 def_bool $(cc-option,-msign-return-address=all)
1549
1550 config AS_HAS_PAC
1551 def_bool $(as-option,-Wa$(comma)-march=armv8.3-a)
1552
1553 config AS_HAS_CFI_NEGATE_RA_STATE
1554 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1555
1556 endmenu
1557
1558 menu "ARMv8.4 architectural features"
1559
1560 config ARM64_AMU_EXTN
1561 bool "Enable support for the Activity Monitors Unit CPU extension"
1562 default y
1563 help
1564 The activity monitors extension is an optional extension introduced
1565 by the ARMv8.4 CPU architecture. This enables support for version 1
1566 of the activity monitors architecture, AMUv1.
1567
1568 To enable the use of this extension on CPUs that implement it, say Y.
1569
1570 Note that for architectural reasons, firmware _must_ implement AMU
1571 support when running on CPUs that present the activity monitors
1572 extension. The required support is present in:
1573 * Version 1.5 and later of the ARM Trusted Firmware
1574
1575 For kernels that have this configuration enabled but boot with broken
1576 firmware, you may need to say N here until the firmware is fixed.
1577 Otherwise you may experience firmware panics or lockups when
1578 accessing the counter registers. Even if you are not observing these
1579 symptoms, the values returned by the register reads might not
1580 correctly reflect reality. Most commonly, the value read will be 0,
1581 indicating that the counter is not enabled.
1582
1583 endmenu
1584
1585 menu "ARMv8.5 architectural features"
1586
1587 config ARM64_E0PD
1588 bool "Enable support for E0PD"
1589 default y
1590 help
1591 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1592 that EL0 accesses made via TTBR1 always fault in constant time,
1593 providing similar benefits to KASLR as those provided by KPTI, but
1594 with lower overhead and without disrupting legitimate access to
1595 kernel memory such as SPE.
1596
1597 This option enables E0PD for TTBR1 where available.
1598
1599 config ARCH_RANDOM
1600 bool "Enable support for random number generation"
1601 default y
1602 help
1603 Random number generation (part of the ARMv8.5 Extensions)
1604 provides a high bandwidth, cryptographically secure
1605 hardware random number generator.
1606
1607 endmenu
1608
1609 config ARM64_SVE
1610 bool "ARM Scalable Vector Extension support"
1611 default y
1612 depends on !KVM || ARM64_VHE
1613 help
1614 The Scalable Vector Extension (SVE) is an extension to the AArch64
1615 execution state which complements and extends the SIMD functionality
1616 of the base architecture to support much larger vectors and to enable
1617 additional vectorisation opportunities.
1618
1619 To enable use of this extension on CPUs that implement it, say Y.
1620
1621 On CPUs that support the SVE2 extensions, this option will enable
1622 those too.
1623
1624 Note that for architectural reasons, firmware _must_ implement SVE
1625 support when running on SVE capable hardware. The required support
1626 is present in:
1627
1628 * version 1.5 and later of the ARM Trusted Firmware
1629 * the AArch64 boot wrapper since commit 5e1261e08abf
1630 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1631
1632 For other firmware implementations, consult the firmware documentation
1633 or vendor.
1634
1635 If you need the kernel to boot on SVE-capable hardware with broken
1636 firmware, you may need to say N here until you get your firmware
1637 fixed. Otherwise, you may experience firmware panics or lockups when
1638 booting the kernel. If unsure and you are not observing these
1639 symptoms, you should assume that it is safe to say Y.
1640
1641 CPUs that support SVE are architecturally required to support the
1642 Virtualization Host Extensions (VHE), so the kernel makes no
1643 provision for supporting SVE alongside KVM without VHE enabled.
1644 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1645 KVM in the same kernel image.
1646
1647 config ARM64_MODULE_PLTS
1648 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1649 depends on MODULES
1650 select HAVE_MOD_ARCH_SPECIFIC
1651 help
1652 Allocate PLTs when loading modules so that jumps and calls whose
1653 targets are too far away for their relative offsets to be encoded
1654 in the instructions themselves can be bounced via veneers in the
1655 module's PLT. This allows modules to be allocated in the generic
1656 vmalloc area after the dedicated module memory area has been
1657 exhausted.
1658
1659 When running with address space randomization (KASLR), the module
1660 region itself may be too far away for ordinary relative jumps and
1661 calls, and so in that case, module PLTs are required and cannot be
1662 disabled.
1663
1664 Specific errata workaround(s) might also force module PLTs to be
1665 enabled (ARM64_ERRATUM_843419).
1666
1667 config ARM64_PSEUDO_NMI
1668 bool "Support for NMI-like interrupts"
1669 select ARM_GIC_V3
1670 help
1671 Adds support for mimicking Non-Maskable Interrupts through the use of
1672 GIC interrupt priority. This support requires version 3 or later of
1673 ARM GIC.
1674
1675 This high priority configuration for interrupts needs to be
1676 explicitly enabled by setting the kernel parameter
1677 "irqchip.gicv3_pseudo_nmi" to 1.
1678
1679 If unsure, say N
1680
1681 if ARM64_PSEUDO_NMI
1682 config ARM64_DEBUG_PRIORITY_MASKING
1683 bool "Debug interrupt priority masking"
1684 help
1685 This adds runtime checks to functions enabling/disabling
1686 interrupts when using priority masking. The additional checks verify
1687 the validity of ICC_PMR_EL1 when calling concerned functions.
1688
1689 If unsure, say N
1690 endif
1691
1692 config RELOCATABLE
1693 bool
1694 select ARCH_HAS_RELR
1695 help
1696 This builds the kernel as a Position Independent Executable (PIE),
1697 which retains all relocation metadata required to relocate the
1698 kernel binary at runtime to a different virtual address than the
1699 address it was linked at.
1700 Since AArch64 uses the RELA relocation format, this requires a
1701 relocation pass at runtime even if the kernel is loaded at the
1702 same address it was linked at.
1703
1704 config RANDOMIZE_BASE
1705 bool "Randomize the address of the kernel image"
1706 select ARM64_MODULE_PLTS if MODULES
1707 select RELOCATABLE
1708 help
1709 Randomizes the virtual address at which the kernel image is
1710 loaded, as a security feature that deters exploit attempts
1711 relying on knowledge of the location of kernel internals.
1712
1713 It is the bootloader's job to provide entropy, by passing a
1714 random u64 value in /chosen/kaslr-seed at kernel entry.
1715
1716 When booting via the UEFI stub, it will invoke the firmware's
1717 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1718 to the kernel proper. In addition, it will randomise the physical
1719 location of the kernel Image as well.
1720
1721 If unsure, say N.
1722
1723 config RANDOMIZE_MODULE_REGION_FULL
1724 bool "Randomize the module region over a 4 GB range"
1725 depends on RANDOMIZE_BASE
1726 default y
1727 help
1728 Randomizes the location of the module region inside a 4 GB window
1729 covering the core kernel. This way, it is less likely for modules
1730 to leak information about the location of core kernel data structures
1731 but it does imply that function calls between modules and the core
1732 kernel will need to be resolved via veneers in the module PLT.
1733
1734 When this option is not set, the module region will be randomized over
1735 a limited range that contains the [_stext, _etext] interval of the
1736 core kernel, so branch relocations are always in range.
1737
1738 config CC_HAVE_STACKPROTECTOR_SYSREG
1739 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1740
1741 config STACKPROTECTOR_PER_TASK
1742 def_bool y
1743 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1744
1745 endmenu
1746
1747 menu "Boot options"
1748
1749 config ARM64_ACPI_PARKING_PROTOCOL
1750 bool "Enable support for the ARM64 ACPI parking protocol"
1751 depends on ACPI
1752 help
1753 Enable support for the ARM64 ACPI parking protocol. If disabled
1754 the kernel will not allow booting through the ARM64 ACPI parking
1755 protocol even if the corresponding data is present in the ACPI
1756 MADT table.
1757
1758 config CMDLINE
1759 string "Default kernel command string"
1760 default ""
1761 help
1762 Provide a set of default command-line options at build time by
1763 entering them here. As a minimum, you should specify the the
1764 root device (e.g. root=/dev/nfs).
1765
1766 config CMDLINE_FORCE
1767 bool "Always use the default kernel command string"
1768 depends on CMDLINE != ""
1769 help
1770 Always use the default kernel command string, even if the boot
1771 loader passes other arguments to the kernel.
1772 This is useful if you cannot or don't want to change the
1773 command-line options your boot loader passes to the kernel.
1774
1775 config EFI_STUB
1776 bool
1777
1778 config EFI
1779 bool "UEFI runtime support"
1780 depends on OF && !CPU_BIG_ENDIAN
1781 depends on KERNEL_MODE_NEON
1782 select ARCH_SUPPORTS_ACPI
1783 select LIBFDT
1784 select UCS2_STRING
1785 select EFI_PARAMS_FROM_FDT
1786 select EFI_RUNTIME_WRAPPERS
1787 select EFI_STUB
1788 select EFI_ARMSTUB
1789 default y
1790 help
1791 This option provides support for runtime services provided
1792 by UEFI firmware (such as non-volatile variables, realtime
1793 clock, and platform reset). A UEFI stub is also provided to
1794 allow the kernel to be booted as an EFI application. This
1795 is only useful on systems that have UEFI firmware.
1796
1797 config DMI
1798 bool "Enable support for SMBIOS (DMI) tables"
1799 depends on EFI
1800 default y
1801 help
1802 This enables SMBIOS/DMI feature for systems.
1803
1804 This option is only useful on systems that have UEFI firmware.
1805 However, even with this option, the resultant kernel should
1806 continue to boot on existing non-UEFI platforms.
1807
1808 endmenu
1809
1810 config SYSVIPC_COMPAT
1811 def_bool y
1812 depends on COMPAT && SYSVIPC
1813
1814 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1815 def_bool y
1816 depends on HUGETLB_PAGE && MIGRATION
1817
1818 menu "Power management options"
1819
1820 source "kernel/power/Kconfig"
1821
1822 config ARCH_HIBERNATION_POSSIBLE
1823 def_bool y
1824 depends on CPU_PM
1825
1826 config ARCH_HIBERNATION_HEADER
1827 def_bool y
1828 depends on HIBERNATION
1829
1830 config ARCH_SUSPEND_POSSIBLE
1831 def_bool y
1832
1833 endmenu
1834
1835 menu "CPU Power Management"
1836
1837 source "drivers/cpuidle/Kconfig"
1838
1839 source "drivers/cpufreq/Kconfig"
1840
1841 endmenu
1842
1843 source "drivers/firmware/Kconfig"
1844
1845 source "drivers/acpi/Kconfig"
1846
1847 source "arch/arm64/kvm/Kconfig"
1848
1849 if CRYPTO
1850 source "arch/arm64/crypto/Kconfig"
1851 endif