1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_DMA_PREP_COHERENT
15 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
16 select ARCH_HAS_FAST_MULTIPLIER
17 select ARCH_HAS_FORTIFY_SOURCE
18 select ARCH_HAS_GCOV_PROFILE_ALL
19 select ARCH_HAS_GIGANTIC_PAGE
21 select ARCH_HAS_KEEPINITRD
22 select ARCH_HAS_MEMBARRIER_SYNC_CORE
23 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
24 select ARCH_HAS_PTE_DEVMAP
25 select ARCH_HAS_PTE_SPECIAL
26 select ARCH_HAS_SETUP_DMA_OPS
27 select ARCH_HAS_SET_DIRECT_MAP
28 select ARCH_HAS_SET_MEMORY
29 select ARCH_HAS_STRICT_KERNEL_RWX
30 select ARCH_HAS_STRICT_MODULE_RWX
31 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
32 select ARCH_HAS_SYNC_DMA_FOR_CPU
33 select ARCH_HAS_SYSCALL_WRAPPER
34 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
35 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
36 select ARCH_HAVE_NMI_SAFE_CMPXCHG
37 select ARCH_INLINE_READ_LOCK if !PREEMPTION
38 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
39 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
40 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
41 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
42 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
43 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
44 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
45 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
46 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
47 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
48 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
49 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
50 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
51 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
52 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
53 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
54 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
55 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
56 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
57 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
58 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
59 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
60 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
61 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
62 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
63 select ARCH_KEEP_MEMBLOCK
64 select ARCH_USE_CMPXCHG_LOCKREF
65 select ARCH_USE_QUEUED_RWLOCKS
66 select ARCH_USE_QUEUED_SPINLOCKS
67 select ARCH_SUPPORTS_MEMORY_FAILURE
68 select ARCH_SUPPORTS_ATOMIC_RMW
69 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
70 select ARCH_SUPPORTS_NUMA_BALANCING
71 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
72 select ARCH_WANT_DEFAULT_BPF_JIT
73 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
74 select ARCH_WANT_FRAME_POINTERS
75 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
76 select ARCH_HAS_UBSAN_SANITIZE_ALL
80 select AUDIT_ARCH_COMPAT_GENERIC
81 select ARM_GIC_V2M if PCI
83 select ARM_GIC_V3_ITS if PCI
85 select BUILDTIME_TABLE_SORT
86 select CLONE_BACKWARDS
88 select CPU_PM if (SUSPEND || CPU_IDLE)
90 select DCACHE_WORD_ACCESS
91 select DMA_DIRECT_REMAP
94 select GENERIC_ALLOCATOR
95 select GENERIC_ARCH_TOPOLOGY
96 select GENERIC_CLOCKEVENTS
97 select GENERIC_CLOCKEVENTS_BROADCAST
98 select GENERIC_CPU_AUTOPROBE
99 select GENERIC_CPU_VULNERABILITIES
100 select GENERIC_EARLY_IOREMAP
101 select GENERIC_IDLE_POLL_SETUP
102 select GENERIC_IRQ_MULTI_HANDLER
103 select GENERIC_IRQ_PROBE
104 select GENERIC_IRQ_SHOW
105 select GENERIC_IRQ_SHOW_LEVEL
106 select GENERIC_PCI_IOMAP
107 select GENERIC_PTDUMP
108 select GENERIC_SCHED_CLOCK
109 select GENERIC_SMP_IDLE_THREAD
110 select GENERIC_STRNCPY_FROM_USER
111 select GENERIC_STRNLEN_USER
112 select GENERIC_TIME_VSYSCALL
113 select GENERIC_GETTIMEOFDAY
114 select HANDLE_DOMAIN_IRQ
115 select HARDIRQS_SW_RESEND
117 select HAVE_ACPI_APEI if (ACPI && EFI)
118 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
119 select HAVE_ARCH_AUDITSYSCALL
120 select HAVE_ARCH_BITREVERSE
121 select HAVE_ARCH_COMPILER_H
122 select HAVE_ARCH_HUGE_VMAP
123 select HAVE_ARCH_JUMP_LABEL
124 select HAVE_ARCH_JUMP_LABEL_RELATIVE
125 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
126 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
127 select HAVE_ARCH_KGDB
128 select HAVE_ARCH_MMAP_RND_BITS
129 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
130 select HAVE_ARCH_PREL32_RELOCATIONS
131 select HAVE_ARCH_SECCOMP_FILTER
132 select HAVE_ARCH_STACKLEAK
133 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
134 select HAVE_ARCH_TRACEHOOK
135 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
136 select HAVE_ARCH_VMAP_STACK
137 select HAVE_ARM_SMCCC
138 select HAVE_ASM_MODVERSIONS
140 select HAVE_C_RECORDMCOUNT
141 select HAVE_CMPXCHG_DOUBLE
142 select HAVE_CMPXCHG_LOCAL
143 select HAVE_CONTEXT_TRACKING
144 select HAVE_COPY_THREAD_TLS
145 select HAVE_DEBUG_BUGVERBOSE
146 select HAVE_DEBUG_KMEMLEAK
147 select HAVE_DMA_CONTIGUOUS
148 select HAVE_DYNAMIC_FTRACE
149 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
150 if $(cc-option,-fpatchable-function-entry=2)
151 select HAVE_EFFICIENT_UNALIGNED_ACCESS
153 select HAVE_FTRACE_MCOUNT_RECORD
154 select HAVE_FUNCTION_TRACER
155 select HAVE_FUNCTION_ERROR_INJECTION
156 select HAVE_FUNCTION_GRAPH_TRACER
157 select HAVE_GCC_PLUGINS
158 select HAVE_HW_BREAKPOINT if PERF_EVENTS
159 select HAVE_IRQ_TIME_ACCOUNTING
160 select HAVE_MEMBLOCK_NODE_MAP if NUMA
162 select HAVE_PATA_PLATFORM
163 select HAVE_PERF_EVENTS
164 select HAVE_PERF_REGS
165 select HAVE_PERF_USER_STACK_DUMP
166 select HAVE_REGS_AND_STACK_ACCESS_API
167 select HAVE_FUNCTION_ARG_ACCESS_API
168 select HAVE_FUTEX_CMPXCHG if FUTEX
169 select MMU_GATHER_RCU_TABLE_FREE
171 select HAVE_STACKPROTECTOR
172 select HAVE_SYSCALL_TRACEPOINTS
174 select HAVE_KRETPROBES
175 select HAVE_GENERIC_VDSO
176 select IOMMU_DMA if IOMMU_SUPPORT
178 select IRQ_FORCED_THREADING
179 select MODULES_USE_ELF_RELA
180 select NEED_DMA_MAP_STATE
181 select NEED_SG_DMA_LENGTH
183 select OF_EARLY_FLATTREE
184 select PCI_DOMAINS_GENERIC if PCI
185 select PCI_ECAM if (ACPI && PCI)
186 select PCI_SYSCALL if PCI
191 select SYSCTL_EXCEPTION_TRACE
192 select THREAD_INFO_IN_TASK
194 ARM 64-bit (AArch64) Linux support.
202 config ARM64_PAGE_SHIFT
204 default 16 if ARM64_64K_PAGES
205 default 14 if ARM64_16K_PAGES
208 config ARM64_CONT_SHIFT
210 default 5 if ARM64_64K_PAGES
211 default 7 if ARM64_16K_PAGES
214 config ARCH_MMAP_RND_BITS_MIN
215 default 14 if ARM64_64K_PAGES
216 default 16 if ARM64_16K_PAGES
219 # max bits determined by the following formula:
220 # VA_BITS - PAGE_SHIFT - 3
221 config ARCH_MMAP_RND_BITS_MAX
222 default 19 if ARM64_VA_BITS=36
223 default 24 if ARM64_VA_BITS=39
224 default 27 if ARM64_VA_BITS=42
225 default 30 if ARM64_VA_BITS=47
226 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
227 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
228 default 33 if ARM64_VA_BITS=48
229 default 14 if ARM64_64K_PAGES
230 default 16 if ARM64_16K_PAGES
233 config ARCH_MMAP_RND_COMPAT_BITS_MIN
234 default 7 if ARM64_64K_PAGES
235 default 9 if ARM64_16K_PAGES
238 config ARCH_MMAP_RND_COMPAT_BITS_MAX
244 config STACKTRACE_SUPPORT
247 config ILLEGAL_POINTER_VALUE
249 default 0xdead000000000000
251 config LOCKDEP_SUPPORT
254 config TRACE_IRQFLAGS_SUPPORT
261 config GENERIC_BUG_RELATIVE_POINTERS
263 depends on GENERIC_BUG
265 config GENERIC_HWEIGHT
271 config GENERIC_CALIBRATE_DELAY
275 bool "Support DMA zone" if EXPERT
279 bool "Support DMA32 zone" if EXPERT
282 config ARCH_ENABLE_MEMORY_HOTPLUG
285 config ARCH_ENABLE_MEMORY_HOTREMOVE
291 config KERNEL_MODE_NEON
294 config FIX_EARLYCON_MEM
297 config PGTABLE_LEVELS
299 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
300 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
301 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
302 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
303 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
304 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
306 config ARCH_SUPPORTS_UPROBES
309 config ARCH_PROC_KCORE_TEXT
312 config BROKEN_GAS_INST
313 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
315 config KASAN_SHADOW_OFFSET
318 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
319 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
320 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
321 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
322 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
323 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
324 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
325 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
326 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
327 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
328 default 0xffffffffffffffff
330 source "arch/arm64/Kconfig.platforms"
332 menu "Kernel Features"
334 menu "ARM errata workarounds via the alternatives framework"
336 config ARM64_WORKAROUND_CLEAN_CACHE
339 config ARM64_ERRATUM_826319
340 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
342 select ARM64_WORKAROUND_CLEAN_CACHE
344 This option adds an alternative code sequence to work around ARM
345 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
346 AXI master interface and an L2 cache.
348 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
349 and is unable to accept a certain write via this interface, it will
350 not progress on read data presented on the read data channel and the
353 The workaround promotes data cache clean instructions to
354 data cache clean-and-invalidate.
355 Please note that this does not necessarily enable the workaround,
356 as it depends on the alternative framework, which will only patch
357 the kernel if an affected CPU is detected.
361 config ARM64_ERRATUM_827319
362 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
364 select ARM64_WORKAROUND_CLEAN_CACHE
366 This option adds an alternative code sequence to work around ARM
367 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
368 master interface and an L2 cache.
370 Under certain conditions this erratum can cause a clean line eviction
371 to occur at the same time as another transaction to the same address
372 on the AMBA 5 CHI interface, which can cause data corruption if the
373 interconnect reorders the two transactions.
375 The workaround promotes data cache clean instructions to
376 data cache clean-and-invalidate.
377 Please note that this does not necessarily enable the workaround,
378 as it depends on the alternative framework, which will only patch
379 the kernel if an affected CPU is detected.
383 config ARM64_ERRATUM_824069
384 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
386 select ARM64_WORKAROUND_CLEAN_CACHE
388 This option adds an alternative code sequence to work around ARM
389 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
390 to a coherent interconnect.
392 If a Cortex-A53 processor is executing a store or prefetch for
393 write instruction at the same time as a processor in another
394 cluster is executing a cache maintenance operation to the same
395 address, then this erratum might cause a clean cache line to be
396 incorrectly marked as dirty.
398 The workaround promotes data cache clean instructions to
399 data cache clean-and-invalidate.
400 Please note that this option does not necessarily enable the
401 workaround, as it depends on the alternative framework, which will
402 only patch the kernel if an affected CPU is detected.
406 config ARM64_ERRATUM_819472
407 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
409 select ARM64_WORKAROUND_CLEAN_CACHE
411 This option adds an alternative code sequence to work around ARM
412 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
413 present when it is connected to a coherent interconnect.
415 If the processor is executing a load and store exclusive sequence at
416 the same time as a processor in another cluster is executing a cache
417 maintenance operation to the same address, then this erratum might
418 cause data corruption.
420 The workaround promotes data cache clean instructions to
421 data cache clean-and-invalidate.
422 Please note that this does not necessarily enable the workaround,
423 as it depends on the alternative framework, which will only patch
424 the kernel if an affected CPU is detected.
428 config ARM64_ERRATUM_832075
429 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
432 This option adds an alternative code sequence to work around ARM
433 erratum 832075 on Cortex-A57 parts up to r1p2.
435 Affected Cortex-A57 parts might deadlock when exclusive load/store
436 instructions to Write-Back memory are mixed with Device loads.
438 The workaround is to promote device loads to use Load-Acquire
440 Please note that this does not necessarily enable the workaround,
441 as it depends on the alternative framework, which will only patch
442 the kernel if an affected CPU is detected.
446 config ARM64_ERRATUM_834220
447 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
451 This option adds an alternative code sequence to work around ARM
452 erratum 834220 on Cortex-A57 parts up to r1p2.
454 Affected Cortex-A57 parts might report a Stage 2 translation
455 fault as the result of a Stage 1 fault for load crossing a
456 page boundary when there is a permission or device memory
457 alignment fault at Stage 1 and a translation fault at Stage 2.
459 The workaround is to verify that the Stage 1 translation
460 doesn't generate a fault before handling the Stage 2 fault.
461 Please note that this does not necessarily enable the workaround,
462 as it depends on the alternative framework, which will only patch
463 the kernel if an affected CPU is detected.
467 config ARM64_ERRATUM_845719
468 bool "Cortex-A53: 845719: a load might read incorrect data"
472 This option adds an alternative code sequence to work around ARM
473 erratum 845719 on Cortex-A53 parts up to r0p4.
475 When running a compat (AArch32) userspace on an affected Cortex-A53
476 part, a load at EL0 from a virtual address that matches the bottom 32
477 bits of the virtual address used by a recent load at (AArch64) EL1
478 might return incorrect data.
480 The workaround is to write the contextidr_el1 register on exception
481 return to a 32-bit task.
482 Please note that this does not necessarily enable the workaround,
483 as it depends on the alternative framework, which will only patch
484 the kernel if an affected CPU is detected.
488 config ARM64_ERRATUM_843419
489 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
491 select ARM64_MODULE_PLTS if MODULES
493 This option links the kernel with '--fix-cortex-a53-843419' and
494 enables PLT support to replace certain ADRP instructions, which can
495 cause subsequent memory accesses to use an incorrect address on
496 Cortex-A53 parts up to r0p4.
500 config ARM64_ERRATUM_1024718
501 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
504 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
506 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
507 update of the hardware dirty bit when the DBM/AP bits are updated
508 without a break-before-make. The workaround is to disable the usage
509 of hardware DBM locally on the affected cores. CPUs not affected by
510 this erratum will continue to use the feature.
514 config ARM64_ERRATUM_1418040
515 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
519 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
520 errata 1188873 and 1418040.
522 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
523 cause register corruption when accessing the timer registers
524 from AArch32 userspace.
528 config ARM64_WORKAROUND_SPECULATIVE_AT_VHE
531 config ARM64_ERRATUM_1165522
532 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
534 select ARM64_WORKAROUND_SPECULATIVE_AT_VHE
536 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
538 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
539 corrupted TLBs by speculating an AT instruction during a guest
544 config ARM64_ERRATUM_1530923
545 bool "Cortex-A55: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
547 select ARM64_WORKAROUND_SPECULATIVE_AT_VHE
549 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
551 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
552 corrupted TLBs by speculating an AT instruction during a guest
557 config ARM64_ERRATUM_1286807
558 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
560 select ARM64_WORKAROUND_REPEAT_TLBI
562 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
564 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
565 address for a cacheable mapping of a location is being
566 accessed by a core while another core is remapping the virtual
567 address to a new physical page using the recommended
568 break-before-make sequence, then under very rare circumstances
569 TLBI+DSB completes before a read using the translation being
570 invalidated has been observed by other observers. The
571 workaround repeats the TLBI+DSB operation.
573 config ARM64_WORKAROUND_SPECULATIVE_AT_NVHE
576 config ARM64_ERRATUM_1319367
577 bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
579 select ARM64_WORKAROUND_SPECULATIVE_AT_NVHE
581 This option adds work arounds for ARM Cortex-A57 erratum 1319537
582 and A72 erratum 1319367
584 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
585 speculating an AT instruction during a guest context switch.
589 config ARM64_ERRATUM_1463225
590 bool "Cortex-A76: Software Step might prevent interrupt recognition"
593 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
595 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
596 of a system call instruction (SVC) can prevent recognition of
597 subsequent interrupts when software stepping is disabled in the
598 exception handler of the system call and either kernel debugging
599 is enabled or VHE is in use.
601 Work around the erratum by triggering a dummy step exception
602 when handling a system call from a task that is being stepped
603 in a VHE configuration of the kernel.
607 config ARM64_ERRATUM_1542419
608 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
611 This option adds a workaround for ARM Neoverse-N1 erratum
614 Affected Neoverse-N1 cores could execute a stale instruction when
615 modified by another CPU. The workaround depends on a firmware
618 Workaround the issue by hiding the DIC feature from EL0. This
619 forces user-space to perform cache maintenance.
623 config CAVIUM_ERRATUM_22375
624 bool "Cavium erratum 22375, 24313"
627 Enable workaround for errata 22375 and 24313.
629 This implements two gicv3-its errata workarounds for ThunderX. Both
630 with a small impact affecting only ITS table allocation.
632 erratum 22375: only alloc 8MB table size
633 erratum 24313: ignore memory access type
635 The fixes are in ITS initialization and basically ignore memory access
636 type and table size provided by the TYPER and BASER registers.
640 config CAVIUM_ERRATUM_23144
641 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
645 ITS SYNC command hang for cross node io and collections/cpu mapping.
649 config CAVIUM_ERRATUM_23154
650 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
653 The gicv3 of ThunderX requires a modified version for
654 reading the IAR status to ensure data synchronization
655 (access to icc_iar1_el1 is not sync'ed before and after).
659 config CAVIUM_ERRATUM_27456
660 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
663 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
664 instructions may cause the icache to become corrupted if it
665 contains data for a non-current ASID. The fix is to
666 invalidate the icache when changing the mm context.
670 config CAVIUM_ERRATUM_30115
671 bool "Cavium erratum 30115: Guest may disable interrupts in host"
674 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
675 1.2, and T83 Pass 1.0, KVM guest execution may disable
676 interrupts in host. Trapping both GICv3 group-0 and group-1
677 accesses sidesteps the issue.
681 config CAVIUM_TX2_ERRATUM_219
682 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
685 On Cavium ThunderX2, a load, store or prefetch instruction between a
686 TTBR update and the corresponding context synchronizing operation can
687 cause a spurious Data Abort to be delivered to any hardware thread in
690 Work around the issue by avoiding the problematic code sequence and
691 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
692 trap handler performs the corresponding register access, skips the
693 instruction and ensures context synchronization by virtue of the
698 config QCOM_FALKOR_ERRATUM_1003
699 bool "Falkor E1003: Incorrect translation due to ASID change"
702 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
703 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
704 in TTBR1_EL1, this situation only occurs in the entry trampoline and
705 then only for entries in the walk cache, since the leaf translation
706 is unchanged. Work around the erratum by invalidating the walk cache
707 entries for the trampoline before entering the kernel proper.
709 config ARM64_WORKAROUND_REPEAT_TLBI
712 config QCOM_FALKOR_ERRATUM_1009
713 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
715 select ARM64_WORKAROUND_REPEAT_TLBI
717 On Falkor v1, the CPU may prematurely complete a DSB following a
718 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
719 one more time to fix the issue.
723 config QCOM_QDF2400_ERRATUM_0065
724 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
727 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
728 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
729 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
733 config SOCIONEXT_SYNQUACER_PREITS
734 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
737 Socionext Synquacer SoCs implement a separate h/w block to generate
738 MSI doorbell writes with non-zero values for the device ID.
742 config HISILICON_ERRATUM_161600802
743 bool "Hip07 161600802: Erroneous redistributor VLPI base"
746 The HiSilicon Hip07 SoC uses the wrong redistributor base
747 when issued ITS commands such as VMOVP and VMAPP, and requires
748 a 128kB offset to be applied to the target address in this commands.
752 config QCOM_FALKOR_ERRATUM_E1041
753 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
756 Falkor CPU may speculatively fetch instructions from an improper
757 memory location when MMU translation is changed from SCTLR_ELn[M]=1
758 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
762 config FUJITSU_ERRATUM_010001
763 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
766 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
767 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
768 accesses may cause undefined fault (Data abort, DFSC=0b111111).
769 This fault occurs under a specific hardware condition when a
770 load/store instruction performs an address translation using:
771 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
772 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
773 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
774 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
776 The workaround is to ensure these bits are clear in TCR_ELx.
777 The workaround only affects the Fujitsu-A64FX.
786 default ARM64_4K_PAGES
788 Page size (translation granule) configuration.
790 config ARM64_4K_PAGES
793 This feature enables 4KB pages support.
795 config ARM64_16K_PAGES
798 The system will use 16KB pages support. AArch32 emulation
799 requires applications compiled with 16K (or a multiple of 16K)
802 config ARM64_64K_PAGES
805 This feature enables 64KB pages support (4KB by default)
806 allowing only two levels of page tables and faster TLB
807 look-up. AArch32 emulation requires applications compiled
808 with 64K aligned segments.
813 prompt "Virtual address space size"
814 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
815 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
816 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
818 Allows choosing one of multiple possible virtual address
819 space sizes. The level of translation table is determined by
820 a combination of page size and virtual address space size.
822 config ARM64_VA_BITS_36
823 bool "36-bit" if EXPERT
824 depends on ARM64_16K_PAGES
826 config ARM64_VA_BITS_39
828 depends on ARM64_4K_PAGES
830 config ARM64_VA_BITS_42
832 depends on ARM64_64K_PAGES
834 config ARM64_VA_BITS_47
836 depends on ARM64_16K_PAGES
838 config ARM64_VA_BITS_48
841 config ARM64_VA_BITS_52
843 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
845 Enable 52-bit virtual addressing for userspace when explicitly
846 requested via a hint to mmap(). The kernel will also use 52-bit
847 virtual addresses for its own mappings (provided HW support for
848 this feature is available, otherwise it reverts to 48-bit).
850 NOTE: Enabling 52-bit virtual addressing in conjunction with
851 ARMv8.3 Pointer Authentication will result in the PAC being
852 reduced from 7 bits to 3 bits, which may have a significant
853 impact on its susceptibility to brute-force attacks.
855 If unsure, select 48-bit virtual addressing instead.
859 config ARM64_FORCE_52BIT
860 bool "Force 52-bit virtual addresses for userspace"
861 depends on ARM64_VA_BITS_52 && EXPERT
863 For systems with 52-bit userspace VAs enabled, the kernel will attempt
864 to maintain compatibility with older software by providing 48-bit VAs
865 unless a hint is supplied to mmap.
867 This configuration option disables the 48-bit compatibility logic, and
868 forces all userspace addresses to be 52-bit on HW that supports it. One
869 should only enable this configuration option for stress testing userspace
870 memory management code. If unsure say N here.
874 default 36 if ARM64_VA_BITS_36
875 default 39 if ARM64_VA_BITS_39
876 default 42 if ARM64_VA_BITS_42
877 default 47 if ARM64_VA_BITS_47
878 default 48 if ARM64_VA_BITS_48
879 default 52 if ARM64_VA_BITS_52
882 prompt "Physical address space size"
883 default ARM64_PA_BITS_48
885 Choose the maximum physical address range that the kernel will
888 config ARM64_PA_BITS_48
891 config ARM64_PA_BITS_52
892 bool "52-bit (ARMv8.2)"
893 depends on ARM64_64K_PAGES
894 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
896 Enable support for a 52-bit physical address space, introduced as
897 part of the ARMv8.2-LPA extension.
899 With this enabled, the kernel will also continue to work on CPUs that
900 do not support ARMv8.2-LPA, but with some added memory overhead (and
901 minor performance overhead).
907 default 48 if ARM64_PA_BITS_48
908 default 52 if ARM64_PA_BITS_52
912 default CPU_LITTLE_ENDIAN
914 Select the endianness of data accesses performed by the CPU. Userspace
915 applications will need to be compiled and linked for the endianness
916 that is selected here.
918 config CPU_BIG_ENDIAN
919 bool "Build big-endian kernel"
921 Say Y if you plan on running a kernel with a big-endian userspace.
923 config CPU_LITTLE_ENDIAN
924 bool "Build little-endian kernel"
926 Say Y if you plan on running a kernel with a little-endian userspace.
927 This is usually the case for distributions targeting arm64.
932 bool "Multi-core scheduler support"
934 Multi-core scheduler support improves the CPU scheduler's decision
935 making when dealing with multi-core CPU chips at a cost of slightly
936 increased overhead in some places. If unsure say N here.
939 bool "SMT scheduler support"
941 Improves the CPU scheduler's decision making when dealing with
942 MultiThreading at a cost of slightly increased overhead in some
943 places. If unsure say N here.
946 int "Maximum number of CPUs (2-4096)"
951 bool "Support for hot-pluggable CPUs"
952 select GENERIC_IRQ_MIGRATION
954 Say Y here to experiment with turning CPUs off and on. CPUs
955 can be controlled through /sys/devices/system/cpu.
957 # Common NUMA Features
959 bool "NUMA Memory Allocation and Scheduler Support"
960 select ACPI_NUMA if ACPI
963 Enable NUMA (Non-Uniform Memory Access) support.
965 The kernel will try to allocate memory used by a CPU on the
966 local memory of the CPU and add some more
967 NUMA awareness to the kernel.
970 int "Maximum NUMA Nodes (as a power of 2)"
973 depends on NEED_MULTIPLE_NODES
975 Specify the maximum number of NUMA Nodes available on the target
976 system. Increases memory reserved to accommodate various tables.
978 config USE_PERCPU_NUMA_NODE_ID
982 config HAVE_SETUP_PER_CPU_AREA
986 config NEED_PER_CPU_EMBED_FIRST_CHUNK
993 source "kernel/Kconfig.hz"
995 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
998 config ARCH_SPARSEMEM_ENABLE
1000 select SPARSEMEM_VMEMMAP_ENABLE
1002 config ARCH_SPARSEMEM_DEFAULT
1003 def_bool ARCH_SPARSEMEM_ENABLE
1005 config ARCH_SELECT_MEMORY_MODEL
1006 def_bool ARCH_SPARSEMEM_ENABLE
1008 config ARCH_FLATMEM_ENABLE
1011 config HAVE_ARCH_PFN_VALID
1014 config HW_PERF_EVENTS
1018 config SYS_SUPPORTS_HUGETLBFS
1021 config ARCH_WANT_HUGE_PMD_SHARE
1023 config ARCH_HAS_CACHE_LINE_SIZE
1026 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1027 def_bool y if PGTABLE_LEVELS > 2
1030 bool "Enable seccomp to safely compute untrusted bytecode"
1032 This kernel feature is useful for number crunching applications
1033 that may need to compute untrusted bytecode during their
1034 execution. By using pipes or other transports made available to
1035 the process as file descriptors supporting the read/write
1036 syscalls, it's possible to isolate those applications in
1037 their own address space using seccomp. Once seccomp is
1038 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1039 and the task is only allowed to execute a few safe syscalls
1040 defined by each seccomp mode.
1043 bool "Enable paravirtualization code"
1045 This changes the kernel so it can modify itself when it is run
1046 under a hypervisor, potentially improving performance significantly
1047 over full virtualization.
1049 config PARAVIRT_TIME_ACCOUNTING
1050 bool "Paravirtual steal time accounting"
1053 Select this option to enable fine granularity task steal time
1054 accounting. Time spent executing other tasks in parallel with
1055 the current vCPU is discounted from the vCPU power. To account for
1056 that, there can be a small performance impact.
1058 If in doubt, say N here.
1061 depends on PM_SLEEP_SMP
1063 bool "kexec system call"
1065 kexec is a system call that implements the ability to shutdown your
1066 current kernel, and to start another kernel. It is like a reboot
1067 but it is independent of the system firmware. And like a reboot
1068 you can start any kernel with it, not just Linux.
1071 bool "kexec file based system call"
1074 This is new version of kexec system call. This system call is
1075 file based and takes file descriptors as system call argument
1076 for kernel and initramfs as opposed to list of segments as
1077 accepted by previous system call.
1080 bool "Verify kernel signature during kexec_file_load() syscall"
1081 depends on KEXEC_FILE
1083 Select this option to verify a signature with loaded kernel
1084 image. If configured, any attempt of loading a image without
1085 valid signature will fail.
1087 In addition to that option, you need to enable signature
1088 verification for the corresponding kernel image type being
1089 loaded in order for this to work.
1091 config KEXEC_IMAGE_VERIFY_SIG
1092 bool "Enable Image signature verification support"
1094 depends on KEXEC_SIG
1095 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1097 Enable Image signature verification support.
1099 comment "Support for PE file signature verification disabled"
1100 depends on KEXEC_SIG
1101 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1104 bool "Build kdump crash kernel"
1106 Generate crash dump after being started by kexec. This should
1107 be normally only set in special crash dump kernels which are
1108 loaded in the main kernel with kexec-tools into a specially
1109 reserved region and then later executed after a crash by
1112 For more details see Documentation/admin-guide/kdump/kdump.rst
1119 bool "Xen guest support on ARM64"
1120 depends on ARM64 && OF
1124 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1126 config FORCE_MAX_ZONEORDER
1128 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1129 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1132 The kernel memory allocator divides physically contiguous memory
1133 blocks into "zones", where each zone is a power of two number of
1134 pages. This option selects the largest power of two that the kernel
1135 keeps in the memory allocator. If you need to allocate very large
1136 blocks of physically contiguous memory, then you may need to
1137 increase this value.
1139 This config option is actually maximum order plus one. For example,
1140 a value of 11 means that the largest free memory block is 2^10 pages.
1142 We make sure that we can allocate upto a HugePage size for each configuration.
1144 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1146 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1147 4M allocations matching the default size used by generic code.
1149 config UNMAP_KERNEL_AT_EL0
1150 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1153 Speculation attacks against some high-performance processors can
1154 be used to bypass MMU permission checks and leak kernel data to
1155 userspace. This can be defended against by unmapping the kernel
1156 when running in userspace, mapping it back in on exception entry
1157 via a trampoline page in the vector table.
1161 config HARDEN_BRANCH_PREDICTOR
1162 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1165 Speculation attacks against some high-performance processors rely on
1166 being able to manipulate the branch predictor for a victim context by
1167 executing aliasing branches in the attacker context. Such attacks
1168 can be partially mitigated against by clearing internal branch
1169 predictor state and limiting the prediction logic in some situations.
1171 This config option will take CPU-specific actions to harden the
1172 branch predictor against aliasing attacks and may rely on specific
1173 instruction sequences or control bits being set by the system
1178 config HARDEN_EL2_VECTORS
1179 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1182 Speculation attacks against some high-performance processors can
1183 be used to leak privileged information such as the vector base
1184 register, resulting in a potential defeat of the EL2 layout
1187 This config option will map the vectors to a fixed location,
1188 independent of the EL2 code mapping, so that revealing VBAR_EL2
1189 to an attacker does not give away any extra information. This
1190 only gets enabled on affected CPUs.
1195 bool "Speculative Store Bypass Disable" if EXPERT
1198 This enables mitigation of the bypassing of previous stores
1199 by speculative loads.
1203 config RODATA_FULL_DEFAULT_ENABLED
1204 bool "Apply r/o permissions of VM areas also to their linear aliases"
1207 Apply read-only attributes of VM areas to the linear alias of
1208 the backing pages as well. This prevents code or read-only data
1209 from being modified (inadvertently or intentionally) via another
1210 mapping of the same memory page. This additional enhancement can
1211 be turned off at runtime by passing rodata=[off|on] (and turned on
1212 with rodata=full if this option is set to 'n')
1214 This requires the linear region to be mapped down to pages,
1215 which may adversely affect performance in some cases.
1217 config ARM64_SW_TTBR0_PAN
1218 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1220 Enabling this option prevents the kernel from accessing
1221 user-space memory directly by pointing TTBR0_EL1 to a reserved
1222 zeroed area and reserved ASID. The user access routines
1223 restore the valid TTBR0_EL1 temporarily.
1225 config ARM64_TAGGED_ADDR_ABI
1226 bool "Enable the tagged user addresses syscall ABI"
1229 When this option is enabled, user applications can opt in to a
1230 relaxed ABI via prctl() allowing tagged addresses to be passed
1231 to system calls as pointer arguments. For details, see
1232 Documentation/arm64/tagged-address-abi.rst.
1235 bool "Kernel support for 32-bit EL0"
1236 depends on ARM64_4K_PAGES || EXPERT
1237 select COMPAT_BINFMT_ELF if BINFMT_ELF
1239 select OLD_SIGSUSPEND3
1240 select COMPAT_OLD_SIGACTION
1242 This option enables support for a 32-bit EL0 running under a 64-bit
1243 kernel at EL1. AArch32-specific components such as system calls,
1244 the user helper functions, VFP support and the ptrace interface are
1245 handled appropriately by the kernel.
1247 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1248 that you will only be able to execute AArch32 binaries that were compiled
1249 with page size aligned segments.
1251 If you want to execute 32-bit userspace applications, say Y.
1255 config KUSER_HELPERS
1256 bool "Enable kuser helpers page for 32-bit applications"
1259 Warning: disabling this option may break 32-bit user programs.
1261 Provide kuser helpers to compat tasks. The kernel provides
1262 helper code to userspace in read only form at a fixed location
1263 to allow userspace to be independent of the CPU type fitted to
1264 the system. This permits binaries to be run on ARMv4 through
1265 to ARMv8 without modification.
1267 See Documentation/arm/kernel_user_helpers.rst for details.
1269 However, the fixed address nature of these helpers can be used
1270 by ROP (return orientated programming) authors when creating
1273 If all of the binaries and libraries which run on your platform
1274 are built specifically for your platform, and make no use of
1275 these helpers, then you can turn this option off to hinder
1276 such exploits. However, in that case, if a binary or library
1277 relying on those helpers is run, it will not function correctly.
1279 Say N here only if you are absolutely certain that you do not
1280 need these helpers; otherwise, the safe option is to say Y.
1283 bool "Enable vDSO for 32-bit applications"
1284 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1285 select GENERIC_COMPAT_VDSO
1288 Place in the process address space of 32-bit applications an
1289 ELF shared object providing fast implementations of gettimeofday
1292 You must have a 32-bit build of glibc 2.22 or later for programs
1293 to seamlessly take advantage of this.
1295 menuconfig ARMV8_DEPRECATED
1296 bool "Emulate deprecated/obsolete ARMv8 instructions"
1299 Legacy software support may require certain instructions
1300 that have been deprecated or obsoleted in the architecture.
1302 Enable this config to enable selective emulation of these
1309 config SWP_EMULATION
1310 bool "Emulate SWP/SWPB instructions"
1312 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1313 they are always undefined. Say Y here to enable software
1314 emulation of these instructions for userspace using LDXR/STXR.
1316 In some older versions of glibc [<=2.8] SWP is used during futex
1317 trylock() operations with the assumption that the code will not
1318 be preempted. This invalid assumption may be more likely to fail
1319 with SWP emulation enabled, leading to deadlock of the user
1322 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1323 on an external transaction monitoring block called a global
1324 monitor to maintain update atomicity. If your system does not
1325 implement a global monitor, this option can cause programs that
1326 perform SWP operations to uncached memory to deadlock.
1330 config CP15_BARRIER_EMULATION
1331 bool "Emulate CP15 Barrier instructions"
1333 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1334 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1335 strongly recommended to use the ISB, DSB, and DMB
1336 instructions instead.
1338 Say Y here to enable software emulation of these
1339 instructions for AArch32 userspace code. When this option is
1340 enabled, CP15 barrier usage is traced which can help
1341 identify software that needs updating.
1345 config SETEND_EMULATION
1346 bool "Emulate SETEND instruction"
1348 The SETEND instruction alters the data-endianness of the
1349 AArch32 EL0, and is deprecated in ARMv8.
1351 Say Y here to enable software emulation of the instruction
1352 for AArch32 userspace code.
1354 Note: All the cpus on the system must have mixed endian support at EL0
1355 for this feature to be enabled. If a new CPU - which doesn't support mixed
1356 endian - is hotplugged in after this feature has been enabled, there could
1357 be unexpected results in the applications.
1364 menu "ARMv8.1 architectural features"
1366 config ARM64_HW_AFDBM
1367 bool "Support for hardware updates of the Access and Dirty page flags"
1370 The ARMv8.1 architecture extensions introduce support for
1371 hardware updates of the access and dirty information in page
1372 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1373 capable processors, accesses to pages with PTE_AF cleared will
1374 set this bit instead of raising an access flag fault.
1375 Similarly, writes to read-only pages with the DBM bit set will
1376 clear the read-only bit (AP[2]) instead of raising a
1379 Kernels built with this configuration option enabled continue
1380 to work on pre-ARMv8.1 hardware and the performance impact is
1381 minimal. If unsure, say Y.
1384 bool "Enable support for Privileged Access Never (PAN)"
1387 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1388 prevents the kernel or hypervisor from accessing user-space (EL0)
1391 Choosing this option will cause any unprotected (not using
1392 copy_to_user et al) memory access to fail with a permission fault.
1394 The feature is detected at runtime, and will remain as a 'nop'
1395 instruction if the cpu does not implement the feature.
1397 config ARM64_LSE_ATOMICS
1399 default ARM64_USE_LSE_ATOMICS
1400 depends on $(as-instr,.arch_extension lse)
1402 config ARM64_USE_LSE_ATOMICS
1403 bool "Atomic instructions"
1404 depends on JUMP_LABEL
1407 As part of the Large System Extensions, ARMv8.1 introduces new
1408 atomic instructions that are designed specifically to scale in
1411 Say Y here to make use of these instructions for the in-kernel
1412 atomic routines. This incurs a small overhead on CPUs that do
1413 not support these instructions and requires the kernel to be
1414 built with binutils >= 2.25 in order for the new instructions
1418 bool "Enable support for Virtualization Host Extensions (VHE)"
1421 Virtualization Host Extensions (VHE) allow the kernel to run
1422 directly at EL2 (instead of EL1) on processors that support
1423 it. This leads to better performance for KVM, as they reduce
1424 the cost of the world switch.
1426 Selecting this option allows the VHE feature to be detected
1427 at runtime, and does not affect processors that do not
1428 implement this feature.
1432 menu "ARMv8.2 architectural features"
1435 bool "Enable support for User Access Override (UAO)"
1438 User Access Override (UAO; part of the ARMv8.2 Extensions)
1439 causes the 'unprivileged' variant of the load/store instructions to
1440 be overridden to be privileged.
1442 This option changes get_user() and friends to use the 'unprivileged'
1443 variant of the load/store instructions. This ensures that user-space
1444 really did have access to the supplied memory. When addr_limit is
1445 set to kernel memory the UAO bit will be set, allowing privileged
1446 access to kernel memory.
1448 Choosing this option will cause copy_to_user() et al to use user-space
1451 The feature is detected at runtime, the kernel will use the
1452 regular load/store instructions if the cpu does not implement the
1456 bool "Enable support for persistent memory"
1457 select ARCH_HAS_PMEM_API
1458 select ARCH_HAS_UACCESS_FLUSHCACHE
1460 Say Y to enable support for the persistent memory API based on the
1461 ARMv8.2 DCPoP feature.
1463 The feature is detected at runtime, and the kernel will use DC CVAC
1464 operations if DC CVAP is not supported (following the behaviour of
1465 DC CVAP itself if the system does not define a point of persistence).
1467 config ARM64_RAS_EXTN
1468 bool "Enable support for RAS CPU Extensions"
1471 CPUs that support the Reliability, Availability and Serviceability
1472 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1473 errors, classify them and report them to software.
1475 On CPUs with these extensions system software can use additional
1476 barriers to determine if faults are pending and read the
1477 classification from a new set of registers.
1479 Selecting this feature will allow the kernel to use these barriers
1480 and access the new registers if the system supports the extension.
1481 Platform RAS features may additionally depend on firmware support.
1484 bool "Enable support for Common Not Private (CNP) translations"
1486 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1488 Common Not Private (CNP) allows translation table entries to
1489 be shared between different PEs in the same inner shareable
1490 domain, so the hardware can use this fact to optimise the
1491 caching of such entries in the TLB.
1493 Selecting this option allows the CNP feature to be detected
1494 at runtime, and does not affect PEs that do not implement
1499 menu "ARMv8.3 architectural features"
1501 config ARM64_PTR_AUTH
1502 bool "Enable support for pointer authentication"
1504 depends on !KVM || ARM64_VHE
1505 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1506 # GCC 9.1 and later inserts a .note.gnu.property section note for PAC
1507 # which is only understood by binutils starting with version 2.33.1.
1508 depends on !CC_IS_GCC || GCC_VERSION < 90100 || LD_VERSION >= 233010000
1509 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1510 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1512 Pointer authentication (part of the ARMv8.3 Extensions) provides
1513 instructions for signing and authenticating pointers against secret
1514 keys, which can be used to mitigate Return Oriented Programming (ROP)
1517 This option enables these instructions at EL0 (i.e. for userspace).
1518 Choosing this option will cause the kernel to initialise secret keys
1519 for each process at exec() time, with these keys being
1520 context-switched along with the process.
1522 If the compiler supports the -mbranch-protection or
1523 -msign-return-address flag (e.g. GCC 7 or later), then this option
1524 will also cause the kernel itself to be compiled with return address
1525 protection. In this case, and if the target hardware is known to
1526 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1527 disabled with minimal loss of protection.
1529 The feature is detected at runtime. If the feature is not present in
1530 hardware it will not be advertised to userspace/KVM guest nor will it
1531 be enabled. However, KVM guest also require VHE mode and hence
1532 CONFIG_ARM64_VHE=y option to use this feature.
1534 If the feature is present on the boot CPU but not on a late CPU, then
1535 the late CPU will be parked. Also, if the boot CPU does not have
1536 address auth and the late CPU has then the late CPU will still boot
1537 but with the feature disabled. On such a system, this option should
1540 This feature works with FUNCTION_GRAPH_TRACER option only if
1541 DYNAMIC_FTRACE_WITH_REGS is enabled.
1543 config CC_HAS_BRANCH_PROT_PAC_RET
1544 # GCC 9 or later, clang 8 or later
1545 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1547 config CC_HAS_SIGN_RETURN_ADDRESS
1549 def_bool $(cc-option,-msign-return-address=all)
1552 def_bool $(as-option,-Wa$(comma)-march=armv8.3-a)
1554 config AS_HAS_CFI_NEGATE_RA_STATE
1555 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1559 menu "ARMv8.4 architectural features"
1561 config ARM64_AMU_EXTN
1562 bool "Enable support for the Activity Monitors Unit CPU extension"
1565 The activity monitors extension is an optional extension introduced
1566 by the ARMv8.4 CPU architecture. This enables support for version 1
1567 of the activity monitors architecture, AMUv1.
1569 To enable the use of this extension on CPUs that implement it, say Y.
1571 Note that for architectural reasons, firmware _must_ implement AMU
1572 support when running on CPUs that present the activity monitors
1573 extension. The required support is present in:
1574 * Version 1.5 and later of the ARM Trusted Firmware
1576 For kernels that have this configuration enabled but boot with broken
1577 firmware, you may need to say N here until the firmware is fixed.
1578 Otherwise you may experience firmware panics or lockups when
1579 accessing the counter registers. Even if you are not observing these
1580 symptoms, the values returned by the register reads might not
1581 correctly reflect reality. Most commonly, the value read will be 0,
1582 indicating that the counter is not enabled.
1586 menu "ARMv8.5 architectural features"
1589 bool "Enable support for E0PD"
1592 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1593 that EL0 accesses made via TTBR1 always fault in constant time,
1594 providing similar benefits to KASLR as those provided by KPTI, but
1595 with lower overhead and without disrupting legitimate access to
1596 kernel memory such as SPE.
1598 This option enables E0PD for TTBR1 where available.
1601 bool "Enable support for random number generation"
1604 Random number generation (part of the ARMv8.5 Extensions)
1605 provides a high bandwidth, cryptographically secure
1606 hardware random number generator.
1611 bool "ARM Scalable Vector Extension support"
1613 depends on !KVM || ARM64_VHE
1615 The Scalable Vector Extension (SVE) is an extension to the AArch64
1616 execution state which complements and extends the SIMD functionality
1617 of the base architecture to support much larger vectors and to enable
1618 additional vectorisation opportunities.
1620 To enable use of this extension on CPUs that implement it, say Y.
1622 On CPUs that support the SVE2 extensions, this option will enable
1625 Note that for architectural reasons, firmware _must_ implement SVE
1626 support when running on SVE capable hardware. The required support
1629 * version 1.5 and later of the ARM Trusted Firmware
1630 * the AArch64 boot wrapper since commit 5e1261e08abf
1631 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1633 For other firmware implementations, consult the firmware documentation
1636 If you need the kernel to boot on SVE-capable hardware with broken
1637 firmware, you may need to say N here until you get your firmware
1638 fixed. Otherwise, you may experience firmware panics or lockups when
1639 booting the kernel. If unsure and you are not observing these
1640 symptoms, you should assume that it is safe to say Y.
1642 CPUs that support SVE are architecturally required to support the
1643 Virtualization Host Extensions (VHE), so the kernel makes no
1644 provision for supporting SVE alongside KVM without VHE enabled.
1645 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1646 KVM in the same kernel image.
1648 config ARM64_MODULE_PLTS
1649 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1651 select HAVE_MOD_ARCH_SPECIFIC
1653 Allocate PLTs when loading modules so that jumps and calls whose
1654 targets are too far away for their relative offsets to be encoded
1655 in the instructions themselves can be bounced via veneers in the
1656 module's PLT. This allows modules to be allocated in the generic
1657 vmalloc area after the dedicated module memory area has been
1660 When running with address space randomization (KASLR), the module
1661 region itself may be too far away for ordinary relative jumps and
1662 calls, and so in that case, module PLTs are required and cannot be
1665 Specific errata workaround(s) might also force module PLTs to be
1666 enabled (ARM64_ERRATUM_843419).
1668 config ARM64_PSEUDO_NMI
1669 bool "Support for NMI-like interrupts"
1672 Adds support for mimicking Non-Maskable Interrupts through the use of
1673 GIC interrupt priority. This support requires version 3 or later of
1676 This high priority configuration for interrupts needs to be
1677 explicitly enabled by setting the kernel parameter
1678 "irqchip.gicv3_pseudo_nmi" to 1.
1683 config ARM64_DEBUG_PRIORITY_MASKING
1684 bool "Debug interrupt priority masking"
1686 This adds runtime checks to functions enabling/disabling
1687 interrupts when using priority masking. The additional checks verify
1688 the validity of ICC_PMR_EL1 when calling concerned functions.
1695 select ARCH_HAS_RELR
1697 This builds the kernel as a Position Independent Executable (PIE),
1698 which retains all relocation metadata required to relocate the
1699 kernel binary at runtime to a different virtual address than the
1700 address it was linked at.
1701 Since AArch64 uses the RELA relocation format, this requires a
1702 relocation pass at runtime even if the kernel is loaded at the
1703 same address it was linked at.
1705 config RANDOMIZE_BASE
1706 bool "Randomize the address of the kernel image"
1707 select ARM64_MODULE_PLTS if MODULES
1710 Randomizes the virtual address at which the kernel image is
1711 loaded, as a security feature that deters exploit attempts
1712 relying on knowledge of the location of kernel internals.
1714 It is the bootloader's job to provide entropy, by passing a
1715 random u64 value in /chosen/kaslr-seed at kernel entry.
1717 When booting via the UEFI stub, it will invoke the firmware's
1718 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1719 to the kernel proper. In addition, it will randomise the physical
1720 location of the kernel Image as well.
1724 config RANDOMIZE_MODULE_REGION_FULL
1725 bool "Randomize the module region over a 4 GB range"
1726 depends on RANDOMIZE_BASE
1729 Randomizes the location of the module region inside a 4 GB window
1730 covering the core kernel. This way, it is less likely for modules
1731 to leak information about the location of core kernel data structures
1732 but it does imply that function calls between modules and the core
1733 kernel will need to be resolved via veneers in the module PLT.
1735 When this option is not set, the module region will be randomized over
1736 a limited range that contains the [_stext, _etext] interval of the
1737 core kernel, so branch relocations are always in range.
1739 config CC_HAVE_STACKPROTECTOR_SYSREG
1740 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1742 config STACKPROTECTOR_PER_TASK
1744 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1750 config ARM64_ACPI_PARKING_PROTOCOL
1751 bool "Enable support for the ARM64 ACPI parking protocol"
1754 Enable support for the ARM64 ACPI parking protocol. If disabled
1755 the kernel will not allow booting through the ARM64 ACPI parking
1756 protocol even if the corresponding data is present in the ACPI
1760 string "Default kernel command string"
1763 Provide a set of default command-line options at build time by
1764 entering them here. As a minimum, you should specify the the
1765 root device (e.g. root=/dev/nfs).
1767 config CMDLINE_FORCE
1768 bool "Always use the default kernel command string"
1769 depends on CMDLINE != ""
1771 Always use the default kernel command string, even if the boot
1772 loader passes other arguments to the kernel.
1773 This is useful if you cannot or don't want to change the
1774 command-line options your boot loader passes to the kernel.
1780 bool "UEFI runtime support"
1781 depends on OF && !CPU_BIG_ENDIAN
1782 depends on KERNEL_MODE_NEON
1783 select ARCH_SUPPORTS_ACPI
1786 select EFI_PARAMS_FROM_FDT
1787 select EFI_RUNTIME_WRAPPERS
1792 This option provides support for runtime services provided
1793 by UEFI firmware (such as non-volatile variables, realtime
1794 clock, and platform reset). A UEFI stub is also provided to
1795 allow the kernel to be booted as an EFI application. This
1796 is only useful on systems that have UEFI firmware.
1799 bool "Enable support for SMBIOS (DMI) tables"
1803 This enables SMBIOS/DMI feature for systems.
1805 This option is only useful on systems that have UEFI firmware.
1806 However, even with this option, the resultant kernel should
1807 continue to boot on existing non-UEFI platforms.
1811 config SYSVIPC_COMPAT
1813 depends on COMPAT && SYSVIPC
1815 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1817 depends on HUGETLB_PAGE && MIGRATION
1819 menu "Power management options"
1821 source "kernel/power/Kconfig"
1823 config ARCH_HIBERNATION_POSSIBLE
1827 config ARCH_HIBERNATION_HEADER
1829 depends on HIBERNATION
1831 config ARCH_SUSPEND_POSSIBLE
1836 menu "CPU Power Management"
1838 source "drivers/cpuidle/Kconfig"
1840 source "drivers/cpufreq/Kconfig"
1844 source "drivers/firmware/Kconfig"
1846 source "drivers/acpi/Kconfig"
1848 source "arch/arm64/kvm/Kconfig"
1851 source "arch/arm64/crypto/Kconfig"