1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_IORT if ACPI
9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
10 select ACPI_MCFG if (ACPI && PCI)
11 select ACPI_SPCR_TABLE if ACPI
12 select ACPI_PPTT if ACPI
13 select ARCH_HAS_DEBUG_WX
14 select ARCH_BINFMT_ELF_EXTRA_PHDRS
15 select ARCH_BINFMT_ELF_STATE
16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18 select ARCH_ENABLE_MEMORY_HOTPLUG
19 select ARCH_ENABLE_MEMORY_HOTREMOVE
20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22 select ARCH_HAS_CACHE_LINE_SIZE
23 select ARCH_HAS_CURRENT_STACK_POINTER
24 select ARCH_HAS_DEBUG_VIRTUAL
25 select ARCH_HAS_DEBUG_VM_PGTABLE
26 select ARCH_HAS_DMA_PREP_COHERENT
27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
28 select ARCH_HAS_FAST_MULTIPLIER
29 select ARCH_HAS_FORTIFY_SOURCE
30 select ARCH_HAS_GCOV_PROFILE_ALL
31 select ARCH_HAS_GIGANTIC_PAGE
33 select ARCH_HAS_KEEPINITRD
34 select ARCH_HAS_MEMBARRIER_SYNC_CORE
35 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
36 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
37 select ARCH_HAS_PTE_DEVMAP
38 select ARCH_HAS_PTE_SPECIAL
39 select ARCH_HAS_HW_PTE_YOUNG
40 select ARCH_HAS_SETUP_DMA_OPS
41 select ARCH_HAS_SET_DIRECT_MAP
42 select ARCH_HAS_SET_MEMORY
44 select ARCH_HAS_STRICT_KERNEL_RWX
45 select ARCH_HAS_STRICT_MODULE_RWX
46 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
47 select ARCH_HAS_SYNC_DMA_FOR_CPU
48 select ARCH_HAS_SYSCALL_WRAPPER
49 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
50 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
51 select ARCH_HAS_ZONE_DMA_SET if EXPERT
52 select ARCH_HAVE_ELF_PROT
53 select ARCH_HAVE_NMI_SAFE_CMPXCHG
54 select ARCH_HAVE_TRACE_MMIO_ACCESS
55 select ARCH_INLINE_READ_LOCK if !PREEMPTION
56 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
57 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
58 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
60 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
61 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
62 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
64 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
65 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
66 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
68 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
69 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
70 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
71 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
72 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
74 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
75 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
76 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
78 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
79 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
80 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
81 select ARCH_KEEP_MEMBLOCK
82 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
83 select ARCH_USE_CMPXCHG_LOCKREF
84 select ARCH_USE_GNU_PROPERTY
85 select ARCH_USE_MEMTEST
86 select ARCH_USE_QUEUED_RWLOCKS
87 select ARCH_USE_QUEUED_SPINLOCKS
88 select ARCH_USE_SYM_ANNOTATIONS
89 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
90 select ARCH_SUPPORTS_HUGETLBFS
91 select ARCH_SUPPORTS_MEMORY_FAILURE
92 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
93 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
94 select ARCH_SUPPORTS_LTO_CLANG_THIN
95 select ARCH_SUPPORTS_CFI_CLANG
96 select ARCH_SUPPORTS_ATOMIC_RMW
97 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
98 select ARCH_SUPPORTS_NUMA_BALANCING
99 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
100 select ARCH_SUPPORTS_PER_VMA_LOCK
101 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH
102 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
103 select ARCH_WANT_DEFAULT_BPF_JIT
104 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
105 select ARCH_WANT_FRAME_POINTERS
106 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
107 select ARCH_WANT_LD_ORPHAN_WARN
108 select ARCH_WANTS_NO_INSTR
109 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
110 select ARCH_HAS_UBSAN_SANITIZE_ALL
112 select ARM_ARCH_TIMER
114 select AUDIT_ARCH_COMPAT_GENERIC
115 select ARM_GIC_V2M if PCI
117 select ARM_GIC_V3_ITS if PCI
119 select BUILDTIME_TABLE_SORT
120 select CLONE_BACKWARDS
122 select CPU_PM if (SUSPEND || CPU_IDLE)
124 select DCACHE_WORD_ACCESS
125 select DYNAMIC_FTRACE if FUNCTION_TRACER
126 select DMA_BOUNCE_UNALIGNED_KMALLOC
127 select DMA_DIRECT_REMAP
130 select FUNCTION_ALIGNMENT_4B
131 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS
132 select GENERIC_ALLOCATOR
133 select GENERIC_ARCH_TOPOLOGY
134 select GENERIC_CLOCKEVENTS_BROADCAST
135 select GENERIC_CPU_AUTOPROBE
136 select GENERIC_CPU_DEVICES
137 select GENERIC_CPU_VULNERABILITIES
138 select GENERIC_EARLY_IOREMAP
139 select GENERIC_IDLE_POLL_SETUP
140 select GENERIC_IOREMAP
141 select GENERIC_IRQ_IPI
142 select GENERIC_IRQ_PROBE
143 select GENERIC_IRQ_SHOW
144 select GENERIC_IRQ_SHOW_LEVEL
145 select GENERIC_LIB_DEVMEM_IS_ALLOWED
146 select GENERIC_PCI_IOMAP
147 select GENERIC_PTDUMP
148 select GENERIC_SCHED_CLOCK
149 select GENERIC_SMP_IDLE_THREAD
150 select GENERIC_TIME_VSYSCALL
151 select GENERIC_GETTIMEOFDAY
152 select GENERIC_VDSO_TIME_NS
153 select HARDIRQS_SW_RESEND
158 select HAVE_ACPI_APEI if (ACPI && EFI)
159 select HAVE_ALIGNED_STRUCT_PAGE
160 select HAVE_ARCH_AUDITSYSCALL
161 select HAVE_ARCH_BITREVERSE
162 select HAVE_ARCH_COMPILER_H
163 select HAVE_ARCH_HUGE_VMALLOC
164 select HAVE_ARCH_HUGE_VMAP
165 select HAVE_ARCH_JUMP_LABEL
166 select HAVE_ARCH_JUMP_LABEL_RELATIVE
167 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
168 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
169 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
170 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
171 # Some instrumentation may be unsound, hence EXPERT
172 select HAVE_ARCH_KCSAN if EXPERT
173 select HAVE_ARCH_KFENCE
174 select HAVE_ARCH_KGDB
175 select HAVE_ARCH_MMAP_RND_BITS
176 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
177 select HAVE_ARCH_PREL32_RELOCATIONS
178 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
179 select HAVE_ARCH_SECCOMP_FILTER
180 select HAVE_ARCH_STACKLEAK
181 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
182 select HAVE_ARCH_TRACEHOOK
183 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
184 select HAVE_ARCH_VMAP_STACK
185 select HAVE_ARM_SMCCC
186 select HAVE_ASM_MODVERSIONS
188 select HAVE_C_RECORDMCOUNT
189 select HAVE_CMPXCHG_DOUBLE
190 select HAVE_CMPXCHG_LOCAL
191 select HAVE_CONTEXT_TRACKING_USER
192 select HAVE_DEBUG_KMEMLEAK
193 select HAVE_DMA_CONTIGUOUS
194 select HAVE_DYNAMIC_FTRACE
195 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
196 if $(cc-option,-fpatchable-function-entry=2)
197 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \
198 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS
199 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \
200 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \
201 !CC_OPTIMIZE_FOR_SIZE)
202 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
203 if DYNAMIC_FTRACE_WITH_ARGS
204 select HAVE_SAMPLE_FTRACE_DIRECT
205 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI
206 select HAVE_EFFICIENT_UNALIGNED_ACCESS
208 select HAVE_FTRACE_MCOUNT_RECORD
209 select HAVE_FUNCTION_TRACER
210 select HAVE_FUNCTION_ERROR_INJECTION
211 select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER
212 select HAVE_FUNCTION_GRAPH_TRACER
213 select HAVE_GCC_PLUGINS
214 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \
215 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI
216 select HAVE_HW_BREAKPOINT if PERF_EVENTS
217 select HAVE_IOREMAP_PROT
218 select HAVE_IRQ_TIME_ACCOUNTING
220 select HAVE_MOD_ARCH_SPECIFIC
222 select HAVE_PERF_EVENTS
223 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI
224 select HAVE_PERF_REGS
225 select HAVE_PERF_USER_STACK_DUMP
226 select HAVE_PREEMPT_DYNAMIC_KEY
227 select HAVE_REGS_AND_STACK_ACCESS_API
228 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
229 select HAVE_FUNCTION_ARG_ACCESS_API
230 select MMU_GATHER_RCU_TABLE_FREE
232 select HAVE_STACKPROTECTOR
233 select HAVE_SYSCALL_TRACEPOINTS
235 select HAVE_KRETPROBES
236 select HAVE_GENERIC_VDSO
237 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
239 select IRQ_FORCED_THREADING
240 select KASAN_VMALLOC if KASAN
241 select LOCK_MM_AND_FIND_VMA
242 select MODULES_USE_ELF_RELA
243 select NEED_DMA_MAP_STATE
244 select NEED_SG_DMA_LENGTH
246 select OF_EARLY_FLATTREE
247 select PCI_DOMAINS_GENERIC if PCI
248 select PCI_ECAM if (ACPI && PCI)
249 select PCI_SYSCALL if PCI
254 select SYSCTL_EXCEPTION_TRACE
255 select THREAD_INFO_IN_TASK
256 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
257 select TRACE_IRQFLAGS_SUPPORT
258 select TRACE_IRQFLAGS_NMI_SUPPORT
259 select HAVE_SOFTIRQ_ON_OWN_STACK
261 ARM 64-bit (AArch64) Linux support.
263 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
265 # https://github.com/ClangBuiltLinux/linux/issues/1507
266 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
267 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
269 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
271 depends on $(cc-option,-fpatchable-function-entry=2)
272 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
280 config ARM64_PAGE_SHIFT
282 default 16 if ARM64_64K_PAGES
283 default 14 if ARM64_16K_PAGES
286 config ARM64_CONT_PTE_SHIFT
288 default 5 if ARM64_64K_PAGES
289 default 7 if ARM64_16K_PAGES
292 config ARM64_CONT_PMD_SHIFT
294 default 5 if ARM64_64K_PAGES
295 default 5 if ARM64_16K_PAGES
298 config ARCH_MMAP_RND_BITS_MIN
299 default 14 if ARM64_64K_PAGES
300 default 16 if ARM64_16K_PAGES
303 # max bits determined by the following formula:
304 # VA_BITS - PAGE_SHIFT - 3
305 config ARCH_MMAP_RND_BITS_MAX
306 default 19 if ARM64_VA_BITS=36
307 default 24 if ARM64_VA_BITS=39
308 default 27 if ARM64_VA_BITS=42
309 default 30 if ARM64_VA_BITS=47
310 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
311 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
312 default 33 if ARM64_VA_BITS=48
313 default 14 if ARM64_64K_PAGES
314 default 16 if ARM64_16K_PAGES
317 config ARCH_MMAP_RND_COMPAT_BITS_MIN
318 default 7 if ARM64_64K_PAGES
319 default 9 if ARM64_16K_PAGES
322 config ARCH_MMAP_RND_COMPAT_BITS_MAX
328 config STACKTRACE_SUPPORT
331 config ILLEGAL_POINTER_VALUE
333 default 0xdead000000000000
335 config LOCKDEP_SUPPORT
342 config GENERIC_BUG_RELATIVE_POINTERS
344 depends on GENERIC_BUG
346 config GENERIC_HWEIGHT
352 config GENERIC_CALIBRATE_DELAY
358 config KERNEL_MODE_NEON
361 config FIX_EARLYCON_MEM
364 config PGTABLE_LEVELS
366 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
367 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
368 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
369 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
370 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
371 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
373 config ARCH_SUPPORTS_UPROBES
376 config ARCH_PROC_KCORE_TEXT
379 config BROKEN_GAS_INST
380 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
382 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
384 # Clang's __builtin_return_adddress() strips the PAC since 12.0.0
385 # https://reviews.llvm.org/D75044
386 default y if CC_IS_CLANG && (CLANG_VERSION >= 120000)
387 # GCC's __builtin_return_address() strips the PAC since 11.1.0,
388 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
389 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891
390 default y if CC_IS_GCC && (GCC_VERSION >= 110100)
391 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000)
392 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000)
393 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000)
396 config KASAN_SHADOW_OFFSET
398 depends on KASAN_GENERIC || KASAN_SW_TAGS
399 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
400 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
401 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
402 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
403 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
404 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
405 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
406 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
407 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
408 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
409 default 0xffffffffffffffff
414 source "arch/arm64/Kconfig.platforms"
416 menu "Kernel Features"
418 menu "ARM errata workarounds via the alternatives framework"
420 config AMPERE_ERRATUM_AC03_CPU_38
421 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics"
424 This option adds an alternative code sequence to work around Ampere
425 erratum AC03_CPU_38 on AmpereOne.
427 The affected design reports FEAT_HAFDBS as not implemented in
428 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0
429 as required by the architecture. The unadvertised HAFDBS
430 implementation suffers from an additional erratum where hardware
431 A/D updates can occur after a PTE has been marked invalid.
433 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
434 which avoids enabling unadvertised hardware Access Flag management
439 config ARM64_WORKAROUND_CLEAN_CACHE
442 config ARM64_ERRATUM_826319
443 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
445 select ARM64_WORKAROUND_CLEAN_CACHE
447 This option adds an alternative code sequence to work around ARM
448 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
449 AXI master interface and an L2 cache.
451 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
452 and is unable to accept a certain write via this interface, it will
453 not progress on read data presented on the read data channel and the
456 The workaround promotes data cache clean instructions to
457 data cache clean-and-invalidate.
458 Please note that this does not necessarily enable the workaround,
459 as it depends on the alternative framework, which will only patch
460 the kernel if an affected CPU is detected.
464 config ARM64_ERRATUM_827319
465 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
467 select ARM64_WORKAROUND_CLEAN_CACHE
469 This option adds an alternative code sequence to work around ARM
470 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
471 master interface and an L2 cache.
473 Under certain conditions this erratum can cause a clean line eviction
474 to occur at the same time as another transaction to the same address
475 on the AMBA 5 CHI interface, which can cause data corruption if the
476 interconnect reorders the two transactions.
478 The workaround promotes data cache clean instructions to
479 data cache clean-and-invalidate.
480 Please note that this does not necessarily enable the workaround,
481 as it depends on the alternative framework, which will only patch
482 the kernel if an affected CPU is detected.
486 config ARM64_ERRATUM_824069
487 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
489 select ARM64_WORKAROUND_CLEAN_CACHE
491 This option adds an alternative code sequence to work around ARM
492 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
493 to a coherent interconnect.
495 If a Cortex-A53 processor is executing a store or prefetch for
496 write instruction at the same time as a processor in another
497 cluster is executing a cache maintenance operation to the same
498 address, then this erratum might cause a clean cache line to be
499 incorrectly marked as dirty.
501 The workaround promotes data cache clean instructions to
502 data cache clean-and-invalidate.
503 Please note that this option does not necessarily enable the
504 workaround, as it depends on the alternative framework, which will
505 only patch the kernel if an affected CPU is detected.
509 config ARM64_ERRATUM_819472
510 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
512 select ARM64_WORKAROUND_CLEAN_CACHE
514 This option adds an alternative code sequence to work around ARM
515 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
516 present when it is connected to a coherent interconnect.
518 If the processor is executing a load and store exclusive sequence at
519 the same time as a processor in another cluster is executing a cache
520 maintenance operation to the same address, then this erratum might
521 cause data corruption.
523 The workaround promotes data cache clean instructions to
524 data cache clean-and-invalidate.
525 Please note that this does not necessarily enable the workaround,
526 as it depends on the alternative framework, which will only patch
527 the kernel if an affected CPU is detected.
531 config ARM64_ERRATUM_832075
532 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
535 This option adds an alternative code sequence to work around ARM
536 erratum 832075 on Cortex-A57 parts up to r1p2.
538 Affected Cortex-A57 parts might deadlock when exclusive load/store
539 instructions to Write-Back memory are mixed with Device loads.
541 The workaround is to promote device loads to use Load-Acquire
543 Please note that this does not necessarily enable the workaround,
544 as it depends on the alternative framework, which will only patch
545 the kernel if an affected CPU is detected.
549 config ARM64_ERRATUM_834220
550 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
554 This option adds an alternative code sequence to work around ARM
555 erratum 834220 on Cortex-A57 parts up to r1p2.
557 Affected Cortex-A57 parts might report a Stage 2 translation
558 fault as the result of a Stage 1 fault for load crossing a
559 page boundary when there is a permission or device memory
560 alignment fault at Stage 1 and a translation fault at Stage 2.
562 The workaround is to verify that the Stage 1 translation
563 doesn't generate a fault before handling the Stage 2 fault.
564 Please note that this does not necessarily enable the workaround,
565 as it depends on the alternative framework, which will only patch
566 the kernel if an affected CPU is detected.
570 config ARM64_ERRATUM_1742098
571 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
575 This option removes the AES hwcap for aarch32 user-space to
576 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
578 Affected parts may corrupt the AES state if an interrupt is
579 taken between a pair of AES instructions. These instructions
580 are only present if the cryptography extensions are present.
581 All software should have a fallback implementation for CPUs
582 that don't implement the cryptography extensions.
586 config ARM64_ERRATUM_845719
587 bool "Cortex-A53: 845719: a load might read incorrect data"
591 This option adds an alternative code sequence to work around ARM
592 erratum 845719 on Cortex-A53 parts up to r0p4.
594 When running a compat (AArch32) userspace on an affected Cortex-A53
595 part, a load at EL0 from a virtual address that matches the bottom 32
596 bits of the virtual address used by a recent load at (AArch64) EL1
597 might return incorrect data.
599 The workaround is to write the contextidr_el1 register on exception
600 return to a 32-bit task.
601 Please note that this does not necessarily enable the workaround,
602 as it depends on the alternative framework, which will only patch
603 the kernel if an affected CPU is detected.
607 config ARM64_ERRATUM_843419
608 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
611 This option links the kernel with '--fix-cortex-a53-843419' and
612 enables PLT support to replace certain ADRP instructions, which can
613 cause subsequent memory accesses to use an incorrect address on
614 Cortex-A53 parts up to r0p4.
618 config ARM64_LD_HAS_FIX_ERRATUM_843419
619 def_bool $(ld-option,--fix-cortex-a53-843419)
621 config ARM64_ERRATUM_1024718
622 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
625 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
627 Affected Cortex-A55 cores (all revisions) could cause incorrect
628 update of the hardware dirty bit when the DBM/AP bits are updated
629 without a break-before-make. The workaround is to disable the usage
630 of hardware DBM locally on the affected cores. CPUs not affected by
631 this erratum will continue to use the feature.
635 config ARM64_ERRATUM_1418040
636 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
640 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
641 errata 1188873 and 1418040.
643 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
644 cause register corruption when accessing the timer registers
645 from AArch32 userspace.
649 config ARM64_WORKAROUND_SPECULATIVE_AT
652 config ARM64_ERRATUM_1165522
653 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
655 select ARM64_WORKAROUND_SPECULATIVE_AT
657 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
659 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
660 corrupted TLBs by speculating an AT instruction during a guest
665 config ARM64_ERRATUM_1319367
666 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
668 select ARM64_WORKAROUND_SPECULATIVE_AT
670 This option adds work arounds for ARM Cortex-A57 erratum 1319537
671 and A72 erratum 1319367
673 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
674 speculating an AT instruction during a guest context switch.
678 config ARM64_ERRATUM_1530923
679 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
681 select ARM64_WORKAROUND_SPECULATIVE_AT
683 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
685 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
686 corrupted TLBs by speculating an AT instruction during a guest
691 config ARM64_WORKAROUND_REPEAT_TLBI
694 config ARM64_ERRATUM_2441007
695 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
697 select ARM64_WORKAROUND_REPEAT_TLBI
699 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
701 Under very rare circumstances, affected Cortex-A55 CPUs
702 may not handle a race between a break-before-make sequence on one
703 CPU, and another CPU accessing the same page. This could allow a
704 store to a page that has been unmapped.
706 Work around this by adding the affected CPUs to the list that needs
707 TLB sequences to be done twice.
711 config ARM64_ERRATUM_1286807
712 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
714 select ARM64_WORKAROUND_REPEAT_TLBI
716 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
718 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
719 address for a cacheable mapping of a location is being
720 accessed by a core while another core is remapping the virtual
721 address to a new physical page using the recommended
722 break-before-make sequence, then under very rare circumstances
723 TLBI+DSB completes before a read using the translation being
724 invalidated has been observed by other observers. The
725 workaround repeats the TLBI+DSB operation.
727 config ARM64_ERRATUM_1463225
728 bool "Cortex-A76: Software Step might prevent interrupt recognition"
731 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
733 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
734 of a system call instruction (SVC) can prevent recognition of
735 subsequent interrupts when software stepping is disabled in the
736 exception handler of the system call and either kernel debugging
737 is enabled or VHE is in use.
739 Work around the erratum by triggering a dummy step exception
740 when handling a system call from a task that is being stepped
741 in a VHE configuration of the kernel.
745 config ARM64_ERRATUM_1542419
746 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
749 This option adds a workaround for ARM Neoverse-N1 erratum
752 Affected Neoverse-N1 cores could execute a stale instruction when
753 modified by another CPU. The workaround depends on a firmware
756 Workaround the issue by hiding the DIC feature from EL0. This
757 forces user-space to perform cache maintenance.
761 config ARM64_ERRATUM_1508412
762 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
765 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
767 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
768 of a store-exclusive or read of PAR_EL1 and a load with device or
769 non-cacheable memory attributes. The workaround depends on a firmware
772 KVM guests must also have the workaround implemented or they can
775 Work around the issue by inserting DMB SY barriers around PAR_EL1
776 register reads and warning KVM users. The DMB barrier is sufficient
777 to prevent a speculative PAR_EL1 read.
781 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
784 config ARM64_ERRATUM_2051678
785 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
788 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
789 Affected Cortex-A510 might not respect the ordering rules for
790 hardware update of the page table's dirty bit. The workaround
791 is to not enable the feature on affected CPUs.
795 config ARM64_ERRATUM_2077057
796 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
799 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
800 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
801 expected, but a Pointer Authentication trap is taken instead. The
802 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
803 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
805 This can only happen when EL2 is stepping EL1.
807 When these conditions occur, the SPSR_EL2 value is unchanged from the
808 previous guest entry, and can be restored from the in-memory copy.
812 config ARM64_ERRATUM_2658417
813 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
816 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
817 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
818 BFMMLA or VMMLA instructions in rare circumstances when a pair of
819 A510 CPUs are using shared neon hardware. As the sharing is not
820 discoverable by the kernel, hide the BF16 HWCAP to indicate that
821 user-space should not be using these instructions.
825 config ARM64_ERRATUM_2119858
826 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
828 depends on CORESIGHT_TRBE
829 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
831 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
833 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
834 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
835 the event of a WRAP event.
837 Work around the issue by always making sure we move the TRBPTR_EL1 by
838 256 bytes before enabling the buffer and filling the first 256 bytes of
839 the buffer with ETM ignore packets upon disabling.
843 config ARM64_ERRATUM_2139208
844 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
846 depends on CORESIGHT_TRBE
847 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
849 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
851 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
852 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
853 the event of a WRAP event.
855 Work around the issue by always making sure we move the TRBPTR_EL1 by
856 256 bytes before enabling the buffer and filling the first 256 bytes of
857 the buffer with ETM ignore packets upon disabling.
861 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
864 config ARM64_ERRATUM_2054223
865 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
867 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
869 Enable workaround for ARM Cortex-A710 erratum 2054223
871 Affected cores may fail to flush the trace data on a TSB instruction, when
872 the PE is in trace prohibited state. This will cause losing a few bytes
875 Workaround is to issue two TSB consecutively on affected cores.
879 config ARM64_ERRATUM_2067961
880 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
882 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
884 Enable workaround for ARM Neoverse-N2 erratum 2067961
886 Affected cores may fail to flush the trace data on a TSB instruction, when
887 the PE is in trace prohibited state. This will cause losing a few bytes
890 Workaround is to issue two TSB consecutively on affected cores.
894 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
897 config ARM64_ERRATUM_2253138
898 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
899 depends on CORESIGHT_TRBE
901 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
903 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
905 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
906 for TRBE. Under some conditions, the TRBE might generate a write to the next
907 virtually addressed page following the last page of the TRBE address space
908 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
910 Work around this in the driver by always making sure that there is a
911 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
915 config ARM64_ERRATUM_2224489
916 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
917 depends on CORESIGHT_TRBE
919 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
921 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
923 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
924 for TRBE. Under some conditions, the TRBE might generate a write to the next
925 virtually addressed page following the last page of the TRBE address space
926 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
928 Work around this in the driver by always making sure that there is a
929 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
933 config ARM64_ERRATUM_2441009
934 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
936 select ARM64_WORKAROUND_REPEAT_TLBI
938 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
940 Under very rare circumstances, affected Cortex-A510 CPUs
941 may not handle a race between a break-before-make sequence on one
942 CPU, and another CPU accessing the same page. This could allow a
943 store to a page that has been unmapped.
945 Work around this by adding the affected CPUs to the list that needs
946 TLB sequences to be done twice.
950 config ARM64_ERRATUM_2064142
951 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
952 depends on CORESIGHT_TRBE
955 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
957 Affected Cortex-A510 core might fail to write into system registers after the
958 TRBE has been disabled. Under some conditions after the TRBE has been disabled
959 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
960 and TRBTRG_EL1 will be ignored and will not be effected.
962 Work around this in the driver by executing TSB CSYNC and DSB after collection
963 is stopped and before performing a system register write to one of the affected
968 config ARM64_ERRATUM_2038923
969 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
970 depends on CORESIGHT_TRBE
973 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
975 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
976 prohibited within the CPU. As a result, the trace buffer or trace buffer state
977 might be corrupted. This happens after TRBE buffer has been enabled by setting
978 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
979 execution changes from a context, in which trace is prohibited to one where it
980 isn't, or vice versa. In these mentioned conditions, the view of whether trace
981 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
982 the trace buffer state might be corrupted.
984 Work around this in the driver by preventing an inconsistent view of whether the
985 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
986 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
987 two ISB instructions if no ERET is to take place.
991 config ARM64_ERRATUM_1902691
992 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
993 depends on CORESIGHT_TRBE
996 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
998 Affected Cortex-A510 core might cause trace data corruption, when being written
999 into the memory. Effectively TRBE is broken and hence cannot be used to capture
1002 Work around this problem in the driver by just preventing TRBE initialization on
1003 affected cpus. The firmware must have disabled the access to TRBE for the kernel
1004 on such implementations. This will cover the kernel for any firmware that doesn't
1009 config ARM64_ERRATUM_2457168
1010 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1011 depends on ARM64_AMU_EXTN
1014 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1016 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
1017 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1018 incorrectly giving a significantly higher output value.
1020 Work around this problem by returning 0 when reading the affected counter in
1021 key locations that results in disabling all users of this counter. This effect
1022 is the same to firmware disabling affected counters.
1026 config ARM64_ERRATUM_2645198
1027 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1030 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1032 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1033 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1034 next instruction abort caused by permission fault.
1036 Only user-space does executable to non-executable permission transition via
1037 mprotect() system call. Workaround the problem by doing a break-before-make
1038 TLB invalidation, for all changes to executable user space mappings.
1042 config ARM64_ERRATUM_2966298
1043 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1046 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1048 On an affected Cortex-A520 core, a speculatively executed unprivileged
1049 load might leak data from a privileged level via a cache side channel.
1051 Work around this problem by executing a TLBI before returning to EL0.
1055 config CAVIUM_ERRATUM_22375
1056 bool "Cavium erratum 22375, 24313"
1059 Enable workaround for errata 22375 and 24313.
1061 This implements two gicv3-its errata workarounds for ThunderX. Both
1062 with a small impact affecting only ITS table allocation.
1064 erratum 22375: only alloc 8MB table size
1065 erratum 24313: ignore memory access type
1067 The fixes are in ITS initialization and basically ignore memory access
1068 type and table size provided by the TYPER and BASER registers.
1072 config CAVIUM_ERRATUM_23144
1073 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1077 ITS SYNC command hang for cross node io and collections/cpu mapping.
1081 config CAVIUM_ERRATUM_23154
1082 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1085 The ThunderX GICv3 implementation requires a modified version for
1086 reading the IAR status to ensure data synchronization
1087 (access to icc_iar1_el1 is not sync'ed before and after).
1089 It also suffers from erratum 38545 (also present on Marvell's
1090 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1091 spuriously presented to the CPU interface.
1095 config CAVIUM_ERRATUM_27456
1096 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1099 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1100 instructions may cause the icache to become corrupted if it
1101 contains data for a non-current ASID. The fix is to
1102 invalidate the icache when changing the mm context.
1106 config CAVIUM_ERRATUM_30115
1107 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1110 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1111 1.2, and T83 Pass 1.0, KVM guest execution may disable
1112 interrupts in host. Trapping both GICv3 group-0 and group-1
1113 accesses sidesteps the issue.
1117 config CAVIUM_TX2_ERRATUM_219
1118 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1121 On Cavium ThunderX2, a load, store or prefetch instruction between a
1122 TTBR update and the corresponding context synchronizing operation can
1123 cause a spurious Data Abort to be delivered to any hardware thread in
1126 Work around the issue by avoiding the problematic code sequence and
1127 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1128 trap handler performs the corresponding register access, skips the
1129 instruction and ensures context synchronization by virtue of the
1134 config FUJITSU_ERRATUM_010001
1135 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1138 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1139 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1140 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1141 This fault occurs under a specific hardware condition when a
1142 load/store instruction performs an address translation using:
1143 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1144 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1145 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1146 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1148 The workaround is to ensure these bits are clear in TCR_ELx.
1149 The workaround only affects the Fujitsu-A64FX.
1153 config HISILICON_ERRATUM_161600802
1154 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1157 The HiSilicon Hip07 SoC uses the wrong redistributor base
1158 when issued ITS commands such as VMOVP and VMAPP, and requires
1159 a 128kB offset to be applied to the target address in this commands.
1163 config QCOM_FALKOR_ERRATUM_1003
1164 bool "Falkor E1003: Incorrect translation due to ASID change"
1167 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1168 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1169 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1170 then only for entries in the walk cache, since the leaf translation
1171 is unchanged. Work around the erratum by invalidating the walk cache
1172 entries for the trampoline before entering the kernel proper.
1174 config QCOM_FALKOR_ERRATUM_1009
1175 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1177 select ARM64_WORKAROUND_REPEAT_TLBI
1179 On Falkor v1, the CPU may prematurely complete a DSB following a
1180 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1181 one more time to fix the issue.
1185 config QCOM_QDF2400_ERRATUM_0065
1186 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1189 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1190 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1191 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1195 config QCOM_FALKOR_ERRATUM_E1041
1196 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1199 Falkor CPU may speculatively fetch instructions from an improper
1200 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1201 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1205 config NVIDIA_CARMEL_CNP_ERRATUM
1206 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1209 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1210 invalidate shared TLB entries installed by a different core, as it would
1211 on standard ARM cores.
1215 config ROCKCHIP_ERRATUM_3588001
1216 bool "Rockchip 3588001: GIC600 can not support shareability attributes"
1219 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1220 This means, that its sharability feature may not be used, even though it
1221 is supported by the IP itself.
1225 config SOCIONEXT_SYNQUACER_PREITS
1226 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1229 Socionext Synquacer SoCs implement a separate h/w block to generate
1230 MSI doorbell writes with non-zero values for the device ID.
1234 endmenu # "ARM errata workarounds via the alternatives framework"
1238 default ARM64_4K_PAGES
1240 Page size (translation granule) configuration.
1242 config ARM64_4K_PAGES
1245 This feature enables 4KB pages support.
1247 config ARM64_16K_PAGES
1250 The system will use 16KB pages support. AArch32 emulation
1251 requires applications compiled with 16K (or a multiple of 16K)
1254 config ARM64_64K_PAGES
1257 This feature enables 64KB pages support (4KB by default)
1258 allowing only two levels of page tables and faster TLB
1259 look-up. AArch32 emulation requires applications compiled
1260 with 64K aligned segments.
1265 prompt "Virtual address space size"
1266 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1267 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1268 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1270 Allows choosing one of multiple possible virtual address
1271 space sizes. The level of translation table is determined by
1272 a combination of page size and virtual address space size.
1274 config ARM64_VA_BITS_36
1275 bool "36-bit" if EXPERT
1276 depends on ARM64_16K_PAGES
1278 config ARM64_VA_BITS_39
1280 depends on ARM64_4K_PAGES
1282 config ARM64_VA_BITS_42
1284 depends on ARM64_64K_PAGES
1286 config ARM64_VA_BITS_47
1288 depends on ARM64_16K_PAGES
1290 config ARM64_VA_BITS_48
1293 config ARM64_VA_BITS_52
1295 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1297 Enable 52-bit virtual addressing for userspace when explicitly
1298 requested via a hint to mmap(). The kernel will also use 52-bit
1299 virtual addresses for its own mappings (provided HW support for
1300 this feature is available, otherwise it reverts to 48-bit).
1302 NOTE: Enabling 52-bit virtual addressing in conjunction with
1303 ARMv8.3 Pointer Authentication will result in the PAC being
1304 reduced from 7 bits to 3 bits, which may have a significant
1305 impact on its susceptibility to brute-force attacks.
1307 If unsure, select 48-bit virtual addressing instead.
1311 config ARM64_FORCE_52BIT
1312 bool "Force 52-bit virtual addresses for userspace"
1313 depends on ARM64_VA_BITS_52 && EXPERT
1315 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1316 to maintain compatibility with older software by providing 48-bit VAs
1317 unless a hint is supplied to mmap.
1319 This configuration option disables the 48-bit compatibility logic, and
1320 forces all userspace addresses to be 52-bit on HW that supports it. One
1321 should only enable this configuration option for stress testing userspace
1322 memory management code. If unsure say N here.
1324 config ARM64_VA_BITS
1326 default 36 if ARM64_VA_BITS_36
1327 default 39 if ARM64_VA_BITS_39
1328 default 42 if ARM64_VA_BITS_42
1329 default 47 if ARM64_VA_BITS_47
1330 default 48 if ARM64_VA_BITS_48
1331 default 52 if ARM64_VA_BITS_52
1334 prompt "Physical address space size"
1335 default ARM64_PA_BITS_48
1337 Choose the maximum physical address range that the kernel will
1340 config ARM64_PA_BITS_48
1343 config ARM64_PA_BITS_52
1344 bool "52-bit (ARMv8.2)"
1345 depends on ARM64_64K_PAGES
1346 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1348 Enable support for a 52-bit physical address space, introduced as
1349 part of the ARMv8.2-LPA extension.
1351 With this enabled, the kernel will also continue to work on CPUs that
1352 do not support ARMv8.2-LPA, but with some added memory overhead (and
1353 minor performance overhead).
1357 config ARM64_PA_BITS
1359 default 48 if ARM64_PA_BITS_48
1360 default 52 if ARM64_PA_BITS_52
1364 default CPU_LITTLE_ENDIAN
1366 Select the endianness of data accesses performed by the CPU. Userspace
1367 applications will need to be compiled and linked for the endianness
1368 that is selected here.
1370 config CPU_BIG_ENDIAN
1371 bool "Build big-endian kernel"
1372 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1373 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1374 depends on AS_IS_GNU || AS_VERSION >= 150000
1376 Say Y if you plan on running a kernel with a big-endian userspace.
1378 config CPU_LITTLE_ENDIAN
1379 bool "Build little-endian kernel"
1381 Say Y if you plan on running a kernel with a little-endian userspace.
1382 This is usually the case for distributions targeting arm64.
1387 bool "Multi-core scheduler support"
1389 Multi-core scheduler support improves the CPU scheduler's decision
1390 making when dealing with multi-core CPU chips at a cost of slightly
1391 increased overhead in some places. If unsure say N here.
1393 config SCHED_CLUSTER
1394 bool "Cluster scheduler support"
1396 Cluster scheduler support improves the CPU scheduler's decision
1397 making when dealing with machines that have clusters of CPUs.
1398 Cluster usually means a couple of CPUs which are placed closely
1399 by sharing mid-level caches, last-level cache tags or internal
1403 bool "SMT scheduler support"
1405 Improves the CPU scheduler's decision making when dealing with
1406 MultiThreading at a cost of slightly increased overhead in some
1407 places. If unsure say N here.
1410 int "Maximum number of CPUs (2-4096)"
1415 bool "Support for hot-pluggable CPUs"
1416 select GENERIC_IRQ_MIGRATION
1418 Say Y here to experiment with turning CPUs off and on. CPUs
1419 can be controlled through /sys/devices/system/cpu.
1421 # Common NUMA Features
1423 bool "NUMA Memory Allocation and Scheduler Support"
1424 select GENERIC_ARCH_NUMA
1425 select ACPI_NUMA if ACPI
1427 select HAVE_SETUP_PER_CPU_AREA
1428 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1429 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1430 select USE_PERCPU_NUMA_NODE_ID
1432 Enable NUMA (Non-Uniform Memory Access) support.
1434 The kernel will try to allocate memory used by a CPU on the
1435 local memory of the CPU and add some more
1436 NUMA awareness to the kernel.
1439 int "Maximum NUMA Nodes (as a power of 2)"
1444 Specify the maximum number of NUMA Nodes available on the target
1445 system. Increases memory reserved to accommodate various tables.
1447 source "kernel/Kconfig.hz"
1449 config ARCH_SPARSEMEM_ENABLE
1451 select SPARSEMEM_VMEMMAP_ENABLE
1452 select SPARSEMEM_VMEMMAP
1454 config HW_PERF_EVENTS
1458 # Supported by clang >= 7.0 or GCC >= 12.0.0
1459 config CC_HAVE_SHADOW_CALL_STACK
1460 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1463 bool "Enable paravirtualization code"
1465 This changes the kernel so it can modify itself when it is run
1466 under a hypervisor, potentially improving performance significantly
1467 over full virtualization.
1469 config PARAVIRT_TIME_ACCOUNTING
1470 bool "Paravirtual steal time accounting"
1473 Select this option to enable fine granularity task steal time
1474 accounting. Time spent executing other tasks in parallel with
1475 the current vCPU is discounted from the vCPU power. To account for
1476 that, there can be a small performance impact.
1478 If in doubt, say N here.
1480 config ARCH_SUPPORTS_KEXEC
1481 def_bool PM_SLEEP_SMP
1483 config ARCH_SUPPORTS_KEXEC_FILE
1486 config ARCH_SELECTS_KEXEC_FILE
1488 depends on KEXEC_FILE
1489 select HAVE_IMA_KEXEC if IMA
1491 config ARCH_SUPPORTS_KEXEC_SIG
1494 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG
1497 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG
1500 config ARCH_SUPPORTS_CRASH_DUMP
1503 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION
1508 depends on HIBERNATION || KEXEC_CORE
1515 bool "Xen guest support on ARM64"
1516 depends on ARM64 && OF
1520 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1522 # include/linux/mmzone.h requires the following to be true:
1524 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1526 # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1528 # | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER |
1529 # ----+-------------------+--------------+----------------------+-------------------------+
1530 # 4K | 27 | 12 | 15 | 10 |
1531 # 16K | 27 | 14 | 13 | 11 |
1532 # 64K | 29 | 16 | 13 | 13 |
1533 config ARCH_FORCE_MAX_ORDER
1535 default "13" if ARM64_64K_PAGES
1536 default "11" if ARM64_16K_PAGES
1539 The kernel page allocator limits the size of maximal physically
1540 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
1541 defines the maximal power of two of number of pages that can be
1542 allocated as a single contiguous block. This option allows
1543 overriding the default setting when ability to allocate very
1544 large blocks of physically contiguous memory is required.
1546 The maximal size of allocation cannot exceed the size of the
1547 section, so the value of MAX_PAGE_ORDER should satisfy
1549 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1551 Don't change if unsure.
1553 config UNMAP_KERNEL_AT_EL0
1554 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT
1557 Speculation attacks against some high-performance processors can
1558 be used to bypass MMU permission checks and leak kernel data to
1559 userspace. This can be defended against by unmapping the kernel
1560 when running in userspace, mapping it back in on exception entry
1561 via a trampoline page in the vector table.
1565 config MITIGATE_SPECTRE_BRANCH_HISTORY
1566 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1569 Speculation attacks against some high-performance processors can
1570 make use of branch history to influence future speculation.
1571 When taking an exception from user-space, a sequence of branches
1572 or a firmware call overwrites the branch history.
1574 config RODATA_FULL_DEFAULT_ENABLED
1575 bool "Apply r/o permissions of VM areas also to their linear aliases"
1578 Apply read-only attributes of VM areas to the linear alias of
1579 the backing pages as well. This prevents code or read-only data
1580 from being modified (inadvertently or intentionally) via another
1581 mapping of the same memory page. This additional enhancement can
1582 be turned off at runtime by passing rodata=[off|on] (and turned on
1583 with rodata=full if this option is set to 'n')
1585 This requires the linear region to be mapped down to pages,
1586 which may adversely affect performance in some cases.
1588 config ARM64_SW_TTBR0_PAN
1589 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1591 Enabling this option prevents the kernel from accessing
1592 user-space memory directly by pointing TTBR0_EL1 to a reserved
1593 zeroed area and reserved ASID. The user access routines
1594 restore the valid TTBR0_EL1 temporarily.
1596 config ARM64_TAGGED_ADDR_ABI
1597 bool "Enable the tagged user addresses syscall ABI"
1600 When this option is enabled, user applications can opt in to a
1601 relaxed ABI via prctl() allowing tagged addresses to be passed
1602 to system calls as pointer arguments. For details, see
1603 Documentation/arch/arm64/tagged-address-abi.rst.
1606 bool "Kernel support for 32-bit EL0"
1607 depends on ARM64_4K_PAGES || EXPERT
1609 select OLD_SIGSUSPEND3
1610 select COMPAT_OLD_SIGACTION
1612 This option enables support for a 32-bit EL0 running under a 64-bit
1613 kernel at EL1. AArch32-specific components such as system calls,
1614 the user helper functions, VFP support and the ptrace interface are
1615 handled appropriately by the kernel.
1617 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1618 that you will only be able to execute AArch32 binaries that were compiled
1619 with page size aligned segments.
1621 If you want to execute 32-bit userspace applications, say Y.
1625 config KUSER_HELPERS
1626 bool "Enable kuser helpers page for 32-bit applications"
1629 Warning: disabling this option may break 32-bit user programs.
1631 Provide kuser helpers to compat tasks. The kernel provides
1632 helper code to userspace in read only form at a fixed location
1633 to allow userspace to be independent of the CPU type fitted to
1634 the system. This permits binaries to be run on ARMv4 through
1635 to ARMv8 without modification.
1637 See Documentation/arch/arm/kernel_user_helpers.rst for details.
1639 However, the fixed address nature of these helpers can be used
1640 by ROP (return orientated programming) authors when creating
1643 If all of the binaries and libraries which run on your platform
1644 are built specifically for your platform, and make no use of
1645 these helpers, then you can turn this option off to hinder
1646 such exploits. However, in that case, if a binary or library
1647 relying on those helpers is run, it will not function correctly.
1649 Say N here only if you are absolutely certain that you do not
1650 need these helpers; otherwise, the safe option is to say Y.
1653 bool "Enable vDSO for 32-bit applications"
1654 depends on !CPU_BIG_ENDIAN
1655 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1656 select GENERIC_COMPAT_VDSO
1659 Place in the process address space of 32-bit applications an
1660 ELF shared object providing fast implementations of gettimeofday
1663 You must have a 32-bit build of glibc 2.22 or later for programs
1664 to seamlessly take advantage of this.
1666 config THUMB2_COMPAT_VDSO
1667 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1668 depends on COMPAT_VDSO
1671 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1672 otherwise with '-marm'.
1674 config COMPAT_ALIGNMENT_FIXUPS
1675 bool "Fix up misaligned multi-word loads and stores in user space"
1677 menuconfig ARMV8_DEPRECATED
1678 bool "Emulate deprecated/obsolete ARMv8 instructions"
1681 Legacy software support may require certain instructions
1682 that have been deprecated or obsoleted in the architecture.
1684 Enable this config to enable selective emulation of these
1691 config SWP_EMULATION
1692 bool "Emulate SWP/SWPB instructions"
1694 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1695 they are always undefined. Say Y here to enable software
1696 emulation of these instructions for userspace using LDXR/STXR.
1697 This feature can be controlled at runtime with the abi.swp
1698 sysctl which is disabled by default.
1700 In some older versions of glibc [<=2.8] SWP is used during futex
1701 trylock() operations with the assumption that the code will not
1702 be preempted. This invalid assumption may be more likely to fail
1703 with SWP emulation enabled, leading to deadlock of the user
1706 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1707 on an external transaction monitoring block called a global
1708 monitor to maintain update atomicity. If your system does not
1709 implement a global monitor, this option can cause programs that
1710 perform SWP operations to uncached memory to deadlock.
1714 config CP15_BARRIER_EMULATION
1715 bool "Emulate CP15 Barrier instructions"
1717 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1718 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1719 strongly recommended to use the ISB, DSB, and DMB
1720 instructions instead.
1722 Say Y here to enable software emulation of these
1723 instructions for AArch32 userspace code. When this option is
1724 enabled, CP15 barrier usage is traced which can help
1725 identify software that needs updating. This feature can be
1726 controlled at runtime with the abi.cp15_barrier sysctl.
1730 config SETEND_EMULATION
1731 bool "Emulate SETEND instruction"
1733 The SETEND instruction alters the data-endianness of the
1734 AArch32 EL0, and is deprecated in ARMv8.
1736 Say Y here to enable software emulation of the instruction
1737 for AArch32 userspace code. This feature can be controlled
1738 at runtime with the abi.setend sysctl.
1740 Note: All the cpus on the system must have mixed endian support at EL0
1741 for this feature to be enabled. If a new CPU - which doesn't support mixed
1742 endian - is hotplugged in after this feature has been enabled, there could
1743 be unexpected results in the applications.
1746 endif # ARMV8_DEPRECATED
1750 menu "ARMv8.1 architectural features"
1752 config ARM64_HW_AFDBM
1753 bool "Support for hardware updates of the Access and Dirty page flags"
1756 The ARMv8.1 architecture extensions introduce support for
1757 hardware updates of the access and dirty information in page
1758 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1759 capable processors, accesses to pages with PTE_AF cleared will
1760 set this bit instead of raising an access flag fault.
1761 Similarly, writes to read-only pages with the DBM bit set will
1762 clear the read-only bit (AP[2]) instead of raising a
1765 Kernels built with this configuration option enabled continue
1766 to work on pre-ARMv8.1 hardware and the performance impact is
1767 minimal. If unsure, say Y.
1770 bool "Enable support for Privileged Access Never (PAN)"
1773 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1774 prevents the kernel or hypervisor from accessing user-space (EL0)
1777 Choosing this option will cause any unprotected (not using
1778 copy_to_user et al) memory access to fail with a permission fault.
1780 The feature is detected at runtime, and will remain as a 'nop'
1781 instruction if the cpu does not implement the feature.
1783 config AS_HAS_LSE_ATOMICS
1784 def_bool $(as-instr,.arch_extension lse)
1786 config ARM64_LSE_ATOMICS
1788 default ARM64_USE_LSE_ATOMICS
1789 depends on AS_HAS_LSE_ATOMICS
1791 config ARM64_USE_LSE_ATOMICS
1792 bool "Atomic instructions"
1795 As part of the Large System Extensions, ARMv8.1 introduces new
1796 atomic instructions that are designed specifically to scale in
1799 Say Y here to make use of these instructions for the in-kernel
1800 atomic routines. This incurs a small overhead on CPUs that do
1801 not support these instructions and requires the kernel to be
1802 built with binutils >= 2.25 in order for the new instructions
1805 endmenu # "ARMv8.1 architectural features"
1807 menu "ARMv8.2 architectural features"
1809 config AS_HAS_ARMV8_2
1810 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1813 def_bool $(as-instr,.arch armv8.2-a+sha3)
1816 bool "Enable support for persistent memory"
1817 select ARCH_HAS_PMEM_API
1818 select ARCH_HAS_UACCESS_FLUSHCACHE
1820 Say Y to enable support for the persistent memory API based on the
1821 ARMv8.2 DCPoP feature.
1823 The feature is detected at runtime, and the kernel will use DC CVAC
1824 operations if DC CVAP is not supported (following the behaviour of
1825 DC CVAP itself if the system does not define a point of persistence).
1827 config ARM64_RAS_EXTN
1828 bool "Enable support for RAS CPU Extensions"
1831 CPUs that support the Reliability, Availability and Serviceability
1832 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1833 errors, classify them and report them to software.
1835 On CPUs with these extensions system software can use additional
1836 barriers to determine if faults are pending and read the
1837 classification from a new set of registers.
1839 Selecting this feature will allow the kernel to use these barriers
1840 and access the new registers if the system supports the extension.
1841 Platform RAS features may additionally depend on firmware support.
1844 bool "Enable support for Common Not Private (CNP) translations"
1846 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1848 Common Not Private (CNP) allows translation table entries to
1849 be shared between different PEs in the same inner shareable
1850 domain, so the hardware can use this fact to optimise the
1851 caching of such entries in the TLB.
1853 Selecting this option allows the CNP feature to be detected
1854 at runtime, and does not affect PEs that do not implement
1857 endmenu # "ARMv8.2 architectural features"
1859 menu "ARMv8.3 architectural features"
1861 config ARM64_PTR_AUTH
1862 bool "Enable support for pointer authentication"
1865 Pointer authentication (part of the ARMv8.3 Extensions) provides
1866 instructions for signing and authenticating pointers against secret
1867 keys, which can be used to mitigate Return Oriented Programming (ROP)
1870 This option enables these instructions at EL0 (i.e. for userspace).
1871 Choosing this option will cause the kernel to initialise secret keys
1872 for each process at exec() time, with these keys being
1873 context-switched along with the process.
1875 The feature is detected at runtime. If the feature is not present in
1876 hardware it will not be advertised to userspace/KVM guest nor will it
1879 If the feature is present on the boot CPU but not on a late CPU, then
1880 the late CPU will be parked. Also, if the boot CPU does not have
1881 address auth and the late CPU has then the late CPU will still boot
1882 but with the feature disabled. On such a system, this option should
1885 config ARM64_PTR_AUTH_KERNEL
1886 bool "Use pointer authentication for kernel"
1888 depends on ARM64_PTR_AUTH
1889 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3
1890 # Modern compilers insert a .note.gnu.property section note for PAC
1891 # which is only understood by binutils starting with version 2.33.1.
1892 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1893 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1894 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1896 If the compiler supports the -mbranch-protection or
1897 -msign-return-address flag (e.g. GCC 7 or later), then this option
1898 will cause the kernel itself to be compiled with return address
1899 protection. In this case, and if the target hardware is known to
1900 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1901 disabled with minimal loss of protection.
1903 This feature works with FUNCTION_GRAPH_TRACER option only if
1904 DYNAMIC_FTRACE_WITH_ARGS is enabled.
1906 config CC_HAS_BRANCH_PROT_PAC_RET
1907 # GCC 9 or later, clang 8 or later
1908 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1910 config CC_HAS_SIGN_RETURN_ADDRESS
1912 def_bool $(cc-option,-msign-return-address=all)
1914 config AS_HAS_ARMV8_3
1915 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1917 config AS_HAS_CFI_NEGATE_RA_STATE
1918 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1921 def_bool $(as-instr,.arch_extension rcpc)
1923 endmenu # "ARMv8.3 architectural features"
1925 menu "ARMv8.4 architectural features"
1927 config ARM64_AMU_EXTN
1928 bool "Enable support for the Activity Monitors Unit CPU extension"
1931 The activity monitors extension is an optional extension introduced
1932 by the ARMv8.4 CPU architecture. This enables support for version 1
1933 of the activity monitors architecture, AMUv1.
1935 To enable the use of this extension on CPUs that implement it, say Y.
1937 Note that for architectural reasons, firmware _must_ implement AMU
1938 support when running on CPUs that present the activity monitors
1939 extension. The required support is present in:
1940 * Version 1.5 and later of the ARM Trusted Firmware
1942 For kernels that have this configuration enabled but boot with broken
1943 firmware, you may need to say N here until the firmware is fixed.
1944 Otherwise you may experience firmware panics or lockups when
1945 accessing the counter registers. Even if you are not observing these
1946 symptoms, the values returned by the register reads might not
1947 correctly reflect reality. Most commonly, the value read will be 0,
1948 indicating that the counter is not enabled.
1950 config AS_HAS_ARMV8_4
1951 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1953 config ARM64_TLB_RANGE
1954 bool "Enable support for tlbi range feature"
1956 depends on AS_HAS_ARMV8_4
1958 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1959 range of input addresses.
1961 The feature introduces new assembly instructions, and they were
1962 support when binutils >= 2.30.
1964 endmenu # "ARMv8.4 architectural features"
1966 menu "ARMv8.5 architectural features"
1968 config AS_HAS_ARMV8_5
1969 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1972 bool "Branch Target Identification support"
1975 Branch Target Identification (part of the ARMv8.5 Extensions)
1976 provides a mechanism to limit the set of locations to which computed
1977 branch instructions such as BR or BLR can jump.
1979 To make use of BTI on CPUs that support it, say Y.
1981 BTI is intended to provide complementary protection to other control
1982 flow integrity protection mechanisms, such as the Pointer
1983 authentication mechanism provided as part of the ARMv8.3 Extensions.
1984 For this reason, it does not make sense to enable this option without
1985 also enabling support for pointer authentication. Thus, when
1986 enabling this option you should also select ARM64_PTR_AUTH=y.
1988 Userspace binaries must also be specifically compiled to make use of
1989 this mechanism. If you say N here or the hardware does not support
1990 BTI, such binaries can still run, but you get no additional
1991 enforcement of branch destinations.
1993 config ARM64_BTI_KERNEL
1994 bool "Use Branch Target Identification for kernel"
1996 depends on ARM64_BTI
1997 depends on ARM64_PTR_AUTH_KERNEL
1998 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1999 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
2000 depends on !CC_IS_GCC || GCC_VERSION >= 100100
2001 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
2002 depends on !CC_IS_GCC
2003 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
2004 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
2005 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
2007 Build the kernel with Branch Target Identification annotations
2008 and enable enforcement of this for kernel code. When this option
2009 is enabled and the system supports BTI all kernel code including
2010 modular code must have BTI enabled.
2012 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
2013 # GCC 9 or later, clang 8 or later
2014 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2017 bool "Enable support for E0PD"
2020 E0PD (part of the ARMv8.5 extensions) allows us to ensure
2021 that EL0 accesses made via TTBR1 always fault in constant time,
2022 providing similar benefits to KASLR as those provided by KPTI, but
2023 with lower overhead and without disrupting legitimate access to
2024 kernel memory such as SPE.
2026 This option enables E0PD for TTBR1 where available.
2028 config ARM64_AS_HAS_MTE
2029 # Initial support for MTE went in binutils 2.32.0, checked with
2030 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2031 # as a late addition to the final architecture spec (LDGM/STGM)
2032 # is only supported in the newer 2.32.x and 2.33 binutils
2033 # versions, hence the extra "stgm" instruction check below.
2034 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2037 bool "Memory Tagging Extension support"
2039 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
2040 depends on AS_HAS_ARMV8_5
2041 depends on AS_HAS_LSE_ATOMICS
2042 # Required for tag checking in the uaccess routines
2043 depends on ARM64_PAN
2044 select ARCH_HAS_SUBPAGE_FAULTS
2045 select ARCH_USES_HIGH_VMA_FLAGS
2046 select ARCH_USES_PG_ARCH_X
2048 Memory Tagging (part of the ARMv8.5 Extensions) provides
2049 architectural support for run-time, always-on detection of
2050 various classes of memory error to aid with software debugging
2051 to eliminate vulnerabilities arising from memory-unsafe
2054 This option enables the support for the Memory Tagging
2055 Extension at EL0 (i.e. for userspace).
2057 Selecting this option allows the feature to be detected at
2058 runtime. Any secondary CPU not implementing this feature will
2059 not be allowed a late bring-up.
2061 Userspace binaries that want to use this feature must
2062 explicitly opt in. The mechanism for the userspace is
2065 Documentation/arch/arm64/memory-tagging-extension.rst.
2067 endmenu # "ARMv8.5 architectural features"
2069 menu "ARMv8.7 architectural features"
2072 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2074 depends on ARM64_PAN
2076 Enhanced Privileged Access Never (EPAN) allows Privileged
2077 Access Never to be used with Execute-only mappings.
2079 The feature is detected at runtime, and will remain disabled
2080 if the cpu does not implement the feature.
2081 endmenu # "ARMv8.7 architectural features"
2084 bool "ARM Scalable Vector Extension support"
2087 The Scalable Vector Extension (SVE) is an extension to the AArch64
2088 execution state which complements and extends the SIMD functionality
2089 of the base architecture to support much larger vectors and to enable
2090 additional vectorisation opportunities.
2092 To enable use of this extension on CPUs that implement it, say Y.
2094 On CPUs that support the SVE2 extensions, this option will enable
2097 Note that for architectural reasons, firmware _must_ implement SVE
2098 support when running on SVE capable hardware. The required support
2101 * version 1.5 and later of the ARM Trusted Firmware
2102 * the AArch64 boot wrapper since commit 5e1261e08abf
2103 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2105 For other firmware implementations, consult the firmware documentation
2108 If you need the kernel to boot on SVE-capable hardware with broken
2109 firmware, you may need to say N here until you get your firmware
2110 fixed. Otherwise, you may experience firmware panics or lockups when
2111 booting the kernel. If unsure and you are not observing these
2112 symptoms, you should assume that it is safe to say Y.
2115 bool "ARM Scalable Matrix Extension support"
2117 depends on ARM64_SVE
2119 The Scalable Matrix Extension (SME) is an extension to the AArch64
2120 execution state which utilises a substantial subset of the SVE
2121 instruction set, together with the addition of new architectural
2122 register state capable of holding two dimensional matrix tiles to
2123 enable various matrix operations.
2125 config ARM64_PSEUDO_NMI
2126 bool "Support for NMI-like interrupts"
2129 Adds support for mimicking Non-Maskable Interrupts through the use of
2130 GIC interrupt priority. This support requires version 3 or later of
2133 This high priority configuration for interrupts needs to be
2134 explicitly enabled by setting the kernel parameter
2135 "irqchip.gicv3_pseudo_nmi" to 1.
2140 config ARM64_DEBUG_PRIORITY_MASKING
2141 bool "Debug interrupt priority masking"
2143 This adds runtime checks to functions enabling/disabling
2144 interrupts when using priority masking. The additional checks verify
2145 the validity of ICC_PMR_EL1 when calling concerned functions.
2148 endif # ARM64_PSEUDO_NMI
2151 bool "Build a relocatable kernel image" if EXPERT
2152 select ARCH_HAS_RELR
2155 This builds the kernel as a Position Independent Executable (PIE),
2156 which retains all relocation metadata required to relocate the
2157 kernel binary at runtime to a different virtual address than the
2158 address it was linked at.
2159 Since AArch64 uses the RELA relocation format, this requires a
2160 relocation pass at runtime even if the kernel is loaded at the
2161 same address it was linked at.
2163 config RANDOMIZE_BASE
2164 bool "Randomize the address of the kernel image"
2167 Randomizes the virtual address at which the kernel image is
2168 loaded, as a security feature that deters exploit attempts
2169 relying on knowledge of the location of kernel internals.
2171 It is the bootloader's job to provide entropy, by passing a
2172 random u64 value in /chosen/kaslr-seed at kernel entry.
2174 When booting via the UEFI stub, it will invoke the firmware's
2175 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2176 to the kernel proper. In addition, it will randomise the physical
2177 location of the kernel Image as well.
2181 config RANDOMIZE_MODULE_REGION_FULL
2182 bool "Randomize the module region over a 2 GB range"
2183 depends on RANDOMIZE_BASE
2186 Randomizes the location of the module region inside a 2 GB window
2187 covering the core kernel. This way, it is less likely for modules
2188 to leak information about the location of core kernel data structures
2189 but it does imply that function calls between modules and the core
2190 kernel will need to be resolved via veneers in the module PLT.
2192 When this option is not set, the module region will be randomized over
2193 a limited range that contains the [_stext, _etext] interval of the
2194 core kernel, so branch relocations are almost always in range unless
2195 the region is exhausted. In this particular case of region
2196 exhaustion, modules might be able to fall back to a larger 2GB area.
2198 config CC_HAVE_STACKPROTECTOR_SYSREG
2199 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2201 config STACKPROTECTOR_PER_TASK
2203 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2205 config UNWIND_PATCH_PAC_INTO_SCS
2206 bool "Enable shadow call stack dynamically using code patching"
2207 # needs Clang with https://reviews.llvm.org/D111780 incorporated
2208 depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2209 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2210 depends on SHADOW_CALL_STACK
2211 select UNWIND_TABLES
2214 endmenu # "Kernel Features"
2218 config ARM64_ACPI_PARKING_PROTOCOL
2219 bool "Enable support for the ARM64 ACPI parking protocol"
2222 Enable support for the ARM64 ACPI parking protocol. If disabled
2223 the kernel will not allow booting through the ARM64 ACPI parking
2224 protocol even if the corresponding data is present in the ACPI
2228 string "Default kernel command string"
2231 Provide a set of default command-line options at build time by
2232 entering them here. As a minimum, you should specify the the
2233 root device (e.g. root=/dev/nfs).
2236 prompt "Kernel command line type" if CMDLINE != ""
2237 default CMDLINE_FROM_BOOTLOADER
2239 Choose how the kernel will handle the provided default kernel
2240 command line string.
2242 config CMDLINE_FROM_BOOTLOADER
2243 bool "Use bootloader kernel arguments if available"
2245 Uses the command-line options passed by the boot loader. If
2246 the boot loader doesn't provide any, the default kernel command
2247 string provided in CMDLINE will be used.
2249 config CMDLINE_FORCE
2250 bool "Always use the default kernel command string"
2252 Always use the default kernel command string, even if the boot
2253 loader passes other arguments to the kernel.
2254 This is useful if you cannot or don't want to change the
2255 command-line options your boot loader passes to the kernel.
2263 bool "UEFI runtime support"
2264 depends on OF && !CPU_BIG_ENDIAN
2265 depends on KERNEL_MODE_NEON
2266 select ARCH_SUPPORTS_ACPI
2269 select EFI_PARAMS_FROM_FDT
2270 select EFI_RUNTIME_WRAPPERS
2272 select EFI_GENERIC_STUB
2273 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2276 This option provides support for runtime services provided
2277 by UEFI firmware (such as non-volatile variables, realtime
2278 clock, and platform reset). A UEFI stub is also provided to
2279 allow the kernel to be booted as an EFI application. This
2280 is only useful on systems that have UEFI firmware.
2283 bool "Enable support for SMBIOS (DMI) tables"
2287 This enables SMBIOS/DMI feature for systems.
2289 This option is only useful on systems that have UEFI firmware.
2290 However, even with this option, the resultant kernel should
2291 continue to boot on existing non-UEFI platforms.
2293 endmenu # "Boot options"
2295 menu "Power management options"
2297 source "kernel/power/Kconfig"
2299 config ARCH_HIBERNATION_POSSIBLE
2303 config ARCH_HIBERNATION_HEADER
2305 depends on HIBERNATION
2307 config ARCH_SUSPEND_POSSIBLE
2310 endmenu # "Power management options"
2312 menu "CPU Power Management"
2314 source "drivers/cpuidle/Kconfig"
2316 source "drivers/cpufreq/Kconfig"
2318 endmenu # "CPU Power Management"
2320 source "drivers/acpi/Kconfig"
2322 source "arch/arm64/kvm/Kconfig"