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Merge tag 'io_uring-5.7-2020-05-22' of git://git.kernel.dk/linux-block
[thirdparty/linux.git] / arch / arm64 / boot / dts / allwinner / sun50i-a64.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/reset/sun8i-r-ccu.h>
13 #include <dt-bindings/thermal/thermal.h>
14
15 / {
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 chosen {
21 #address-cells = <1>;
22 #size-cells = <1>;
23 ranges;
24
25 simplefb_lcd: framebuffer-lcd {
26 compatible = "allwinner,simple-framebuffer",
27 "simple-framebuffer";
28 allwinner,pipeline = "mixer0-lcd0";
29 clocks = <&ccu CLK_TCON0>,
30 <&display_clocks CLK_MIXER0>;
31 status = "disabled";
32 };
33
34 simplefb_hdmi: framebuffer-hdmi {
35 compatible = "allwinner,simple-framebuffer",
36 "simple-framebuffer";
37 allwinner,pipeline = "mixer1-lcd1-hdmi";
38 clocks = <&display_clocks CLK_MIXER1>,
39 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
40 status = "disabled";
41 };
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 cpu0: cpu@0 {
49 compatible = "arm,cortex-a53";
50 device_type = "cpu";
51 reg = <0>;
52 enable-method = "psci";
53 next-level-cache = <&L2>;
54 clocks = <&ccu 21>;
55 clock-names = "cpu";
56 #cooling-cells = <2>;
57 };
58
59 cpu1: cpu@1 {
60 compatible = "arm,cortex-a53";
61 device_type = "cpu";
62 reg = <1>;
63 enable-method = "psci";
64 next-level-cache = <&L2>;
65 clocks = <&ccu 21>;
66 clock-names = "cpu";
67 #cooling-cells = <2>;
68 };
69
70 cpu2: cpu@2 {
71 compatible = "arm,cortex-a53";
72 device_type = "cpu";
73 reg = <2>;
74 enable-method = "psci";
75 next-level-cache = <&L2>;
76 clocks = <&ccu 21>;
77 clock-names = "cpu";
78 #cooling-cells = <2>;
79 };
80
81 cpu3: cpu@3 {
82 compatible = "arm,cortex-a53";
83 device_type = "cpu";
84 reg = <3>;
85 enable-method = "psci";
86 next-level-cache = <&L2>;
87 clocks = <&ccu 21>;
88 clock-names = "cpu";
89 #cooling-cells = <2>;
90 };
91
92 L2: l2-cache {
93 compatible = "cache";
94 cache-level = <2>;
95 };
96 };
97
98 de: display-engine {
99 compatible = "allwinner,sun50i-a64-display-engine";
100 allwinner,pipelines = <&mixer0>,
101 <&mixer1>;
102 status = "disabled";
103 };
104
105 osc24M: osc24M_clk {
106 #clock-cells = <0>;
107 compatible = "fixed-clock";
108 clock-frequency = <24000000>;
109 clock-output-names = "osc24M";
110 };
111
112 osc32k: osc32k_clk {
113 #clock-cells = <0>;
114 compatible = "fixed-clock";
115 clock-frequency = <32768>;
116 clock-output-names = "ext-osc32k";
117 };
118
119 pmu {
120 compatible = "arm,cortex-a53-pmu";
121 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
125 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
126 };
127
128 psci {
129 compatible = "arm,psci-0.2";
130 method = "smc";
131 };
132
133 sound: sound {
134 compatible = "simple-audio-card";
135 simple-audio-card,name = "sun50i-a64-audio";
136 simple-audio-card,format = "i2s";
137 simple-audio-card,frame-master = <&cpudai>;
138 simple-audio-card,bitclock-master = <&cpudai>;
139 simple-audio-card,mclk-fs = <128>;
140 simple-audio-card,aux-devs = <&codec_analog>;
141 simple-audio-card,routing =
142 "Left DAC", "AIF1 Slot 0 Left",
143 "Right DAC", "AIF1 Slot 0 Right",
144 "AIF1 Slot 0 Left ADC", "Left ADC",
145 "AIF1 Slot 0 Right ADC", "Right ADC";
146 status = "disabled";
147
148 cpudai: simple-audio-card,cpu {
149 sound-dai = <&dai>;
150 };
151
152 link_codec: simple-audio-card,codec {
153 sound-dai = <&codec>;
154 };
155 };
156
157 timer {
158 compatible = "arm,armv8-timer";
159 allwinner,erratum-unknown1;
160 interrupts = <GIC_PPI 13
161 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
162 <GIC_PPI 14
163 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
164 <GIC_PPI 11
165 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
166 <GIC_PPI 10
167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
168 };
169
170 thermal-zones {
171 cpu_thermal: cpu0-thermal {
172 /* milliseconds */
173 polling-delay-passive = <0>;
174 polling-delay = <0>;
175 thermal-sensors = <&ths 0>;
176
177 cooling-maps {
178 map0 {
179 trip = <&cpu_alert0>;
180 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
181 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
182 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
183 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
184 };
185 map1 {
186 trip = <&cpu_alert1>;
187 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
188 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
189 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
190 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
191 };
192 };
193
194 trips {
195 cpu_alert0: cpu_alert0 {
196 /* milliCelsius */
197 temperature = <75000>;
198 hysteresis = <2000>;
199 type = "passive";
200 };
201
202 cpu_alert1: cpu_alert1 {
203 /* milliCelsius */
204 temperature = <90000>;
205 hysteresis = <2000>;
206 type = "hot";
207 };
208
209 cpu_crit: cpu_crit {
210 /* milliCelsius */
211 temperature = <110000>;
212 hysteresis = <2000>;
213 type = "critical";
214 };
215 };
216 };
217
218 gpu0_thermal: gpu0-thermal {
219 /* milliseconds */
220 polling-delay-passive = <0>;
221 polling-delay = <0>;
222 thermal-sensors = <&ths 1>;
223 };
224
225 gpu1_thermal: gpu1-thermal {
226 /* milliseconds */
227 polling-delay-passive = <0>;
228 polling-delay = <0>;
229 thermal-sensors = <&ths 2>;
230 };
231 };
232
233 soc {
234 compatible = "simple-bus";
235 #address-cells = <1>;
236 #size-cells = <1>;
237 ranges;
238
239 bus@1000000 {
240 compatible = "allwinner,sun50i-a64-de2";
241 reg = <0x1000000 0x400000>;
242 allwinner,sram = <&de2_sram 1>;
243 #address-cells = <1>;
244 #size-cells = <1>;
245 ranges = <0 0x1000000 0x400000>;
246
247 display_clocks: clock@0 {
248 compatible = "allwinner,sun50i-a64-de2-clk";
249 reg = <0x0 0x10000>;
250 clocks = <&ccu CLK_BUS_DE>,
251 <&ccu CLK_DE>;
252 clock-names = "bus",
253 "mod";
254 resets = <&ccu RST_BUS_DE>;
255 #clock-cells = <1>;
256 #reset-cells = <1>;
257 };
258
259 rotate: rotate@20000 {
260 compatible = "allwinner,sun50i-a64-de2-rotate",
261 "allwinner,sun8i-a83t-de2-rotate";
262 reg = <0x20000 0x10000>;
263 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&display_clocks CLK_BUS_ROT>,
265 <&display_clocks CLK_ROT>;
266 clock-names = "bus",
267 "mod";
268 resets = <&display_clocks RST_ROT>;
269 };
270
271 mixer0: mixer@100000 {
272 compatible = "allwinner,sun50i-a64-de2-mixer-0";
273 reg = <0x100000 0x100000>;
274 clocks = <&display_clocks CLK_BUS_MIXER0>,
275 <&display_clocks CLK_MIXER0>;
276 clock-names = "bus",
277 "mod";
278 resets = <&display_clocks RST_MIXER0>;
279
280 ports {
281 #address-cells = <1>;
282 #size-cells = <0>;
283
284 mixer0_out: port@1 {
285 #address-cells = <1>;
286 #size-cells = <0>;
287 reg = <1>;
288
289 mixer0_out_tcon0: endpoint@0 {
290 reg = <0>;
291 remote-endpoint = <&tcon0_in_mixer0>;
292 };
293
294 mixer0_out_tcon1: endpoint@1 {
295 reg = <1>;
296 remote-endpoint = <&tcon1_in_mixer0>;
297 };
298 };
299 };
300 };
301
302 mixer1: mixer@200000 {
303 compatible = "allwinner,sun50i-a64-de2-mixer-1";
304 reg = <0x200000 0x100000>;
305 clocks = <&display_clocks CLK_BUS_MIXER1>,
306 <&display_clocks CLK_MIXER1>;
307 clock-names = "bus",
308 "mod";
309 resets = <&display_clocks RST_MIXER1>;
310
311 ports {
312 #address-cells = <1>;
313 #size-cells = <0>;
314
315 mixer1_out: port@1 {
316 #address-cells = <1>;
317 #size-cells = <0>;
318 reg = <1>;
319
320 mixer1_out_tcon0: endpoint@0 {
321 reg = <0>;
322 remote-endpoint = <&tcon0_in_mixer1>;
323 };
324
325 mixer1_out_tcon1: endpoint@1 {
326 reg = <1>;
327 remote-endpoint = <&tcon1_in_mixer1>;
328 };
329 };
330 };
331 };
332 };
333
334 syscon: syscon@1c00000 {
335 compatible = "allwinner,sun50i-a64-system-control";
336 reg = <0x01c00000 0x1000>;
337 #address-cells = <1>;
338 #size-cells = <1>;
339 ranges;
340
341 sram_c: sram@18000 {
342 compatible = "mmio-sram";
343 reg = <0x00018000 0x28000>;
344 #address-cells = <1>;
345 #size-cells = <1>;
346 ranges = <0 0x00018000 0x28000>;
347
348 de2_sram: sram-section@0 {
349 compatible = "allwinner,sun50i-a64-sram-c";
350 reg = <0x0000 0x28000>;
351 };
352 };
353
354 sram_c1: sram@1d00000 {
355 compatible = "mmio-sram";
356 reg = <0x01d00000 0x40000>;
357 #address-cells = <1>;
358 #size-cells = <1>;
359 ranges = <0 0x01d00000 0x40000>;
360
361 ve_sram: sram-section@0 {
362 compatible = "allwinner,sun50i-a64-sram-c1",
363 "allwinner,sun4i-a10-sram-c1";
364 reg = <0x000000 0x40000>;
365 };
366 };
367 };
368
369 dma: dma-controller@1c02000 {
370 compatible = "allwinner,sun50i-a64-dma";
371 reg = <0x01c02000 0x1000>;
372 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&ccu CLK_BUS_DMA>;
374 dma-channels = <8>;
375 dma-requests = <27>;
376 resets = <&ccu RST_BUS_DMA>;
377 #dma-cells = <1>;
378 };
379
380 tcon0: lcd-controller@1c0c000 {
381 compatible = "allwinner,sun50i-a64-tcon-lcd",
382 "allwinner,sun8i-a83t-tcon-lcd";
383 reg = <0x01c0c000 0x1000>;
384 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
386 clock-names = "ahb", "tcon-ch0";
387 clock-output-names = "tcon-pixel-clock";
388 #clock-cells = <0>;
389 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
390 reset-names = "lcd", "lvds";
391
392 ports {
393 #address-cells = <1>;
394 #size-cells = <0>;
395
396 tcon0_in: port@0 {
397 #address-cells = <1>;
398 #size-cells = <0>;
399 reg = <0>;
400
401 tcon0_in_mixer0: endpoint@0 {
402 reg = <0>;
403 remote-endpoint = <&mixer0_out_tcon0>;
404 };
405
406 tcon0_in_mixer1: endpoint@1 {
407 reg = <1>;
408 remote-endpoint = <&mixer1_out_tcon0>;
409 };
410 };
411
412 tcon0_out: port@1 {
413 #address-cells = <1>;
414 #size-cells = <0>;
415 reg = <1>;
416
417 tcon0_out_dsi: endpoint@1 {
418 reg = <1>;
419 remote-endpoint = <&dsi_in_tcon0>;
420 allwinner,tcon-channel = <1>;
421 };
422 };
423 };
424 };
425
426 tcon1: lcd-controller@1c0d000 {
427 compatible = "allwinner,sun50i-a64-tcon-tv",
428 "allwinner,sun8i-a83t-tcon-tv";
429 reg = <0x01c0d000 0x1000>;
430 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
432 clock-names = "ahb", "tcon-ch1";
433 resets = <&ccu RST_BUS_TCON1>;
434 reset-names = "lcd";
435
436 ports {
437 #address-cells = <1>;
438 #size-cells = <0>;
439
440 tcon1_in: port@0 {
441 #address-cells = <1>;
442 #size-cells = <0>;
443 reg = <0>;
444
445 tcon1_in_mixer0: endpoint@0 {
446 reg = <0>;
447 remote-endpoint = <&mixer0_out_tcon1>;
448 };
449
450 tcon1_in_mixer1: endpoint@1 {
451 reg = <1>;
452 remote-endpoint = <&mixer1_out_tcon1>;
453 };
454 };
455
456 tcon1_out: port@1 {
457 #address-cells = <1>;
458 #size-cells = <0>;
459 reg = <1>;
460
461 tcon1_out_hdmi: endpoint@1 {
462 reg = <1>;
463 remote-endpoint = <&hdmi_in_tcon1>;
464 };
465 };
466 };
467 };
468
469 video-codec@1c0e000 {
470 compatible = "allwinner,sun50i-a64-video-engine";
471 reg = <0x01c0e000 0x1000>;
472 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
473 <&ccu CLK_DRAM_VE>;
474 clock-names = "ahb", "mod", "ram";
475 resets = <&ccu RST_BUS_VE>;
476 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
477 allwinner,sram = <&ve_sram 1>;
478 };
479
480 mmc0: mmc@1c0f000 {
481 compatible = "allwinner,sun50i-a64-mmc";
482 reg = <0x01c0f000 0x1000>;
483 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
484 clock-names = "ahb", "mmc";
485 resets = <&ccu RST_BUS_MMC0>;
486 reset-names = "ahb";
487 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
488 max-frequency = <150000000>;
489 status = "disabled";
490 #address-cells = <1>;
491 #size-cells = <0>;
492 };
493
494 mmc1: mmc@1c10000 {
495 compatible = "allwinner,sun50i-a64-mmc";
496 reg = <0x01c10000 0x1000>;
497 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
498 clock-names = "ahb", "mmc";
499 resets = <&ccu RST_BUS_MMC1>;
500 reset-names = "ahb";
501 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
502 max-frequency = <150000000>;
503 status = "disabled";
504 #address-cells = <1>;
505 #size-cells = <0>;
506 };
507
508 mmc2: mmc@1c11000 {
509 compatible = "allwinner,sun50i-a64-emmc";
510 reg = <0x01c11000 0x1000>;
511 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
512 clock-names = "ahb", "mmc";
513 resets = <&ccu RST_BUS_MMC2>;
514 reset-names = "ahb";
515 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
516 max-frequency = <200000000>;
517 status = "disabled";
518 #address-cells = <1>;
519 #size-cells = <0>;
520 };
521
522 sid: eeprom@1c14000 {
523 compatible = "allwinner,sun50i-a64-sid";
524 reg = <0x1c14000 0x400>;
525 #address-cells = <1>;
526 #size-cells = <1>;
527
528 ths_calibration: thermal-sensor-calibration@34 {
529 reg = <0x34 0x8>;
530 };
531 };
532
533 crypto: crypto@1c15000 {
534 compatible = "allwinner,sun50i-a64-crypto";
535 reg = <0x01c15000 0x1000>;
536 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
538 clock-names = "bus", "mod";
539 resets = <&ccu RST_BUS_CE>;
540 };
541
542 usb_otg: usb@1c19000 {
543 compatible = "allwinner,sun8i-a33-musb";
544 reg = <0x01c19000 0x0400>;
545 clocks = <&ccu CLK_BUS_OTG>;
546 resets = <&ccu RST_BUS_OTG>;
547 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
548 interrupt-names = "mc";
549 phys = <&usbphy 0>;
550 phy-names = "usb";
551 extcon = <&usbphy 0>;
552 dr_mode = "otg";
553 status = "disabled";
554 };
555
556 usbphy: phy@1c19400 {
557 compatible = "allwinner,sun50i-a64-usb-phy";
558 reg = <0x01c19400 0x14>,
559 <0x01c1a800 0x4>,
560 <0x01c1b800 0x4>;
561 reg-names = "phy_ctrl",
562 "pmu0",
563 "pmu1";
564 clocks = <&ccu CLK_USB_PHY0>,
565 <&ccu CLK_USB_PHY1>;
566 clock-names = "usb0_phy",
567 "usb1_phy";
568 resets = <&ccu RST_USB_PHY0>,
569 <&ccu RST_USB_PHY1>;
570 reset-names = "usb0_reset",
571 "usb1_reset";
572 status = "disabled";
573 #phy-cells = <1>;
574 };
575
576 ehci0: usb@1c1a000 {
577 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
578 reg = <0x01c1a000 0x100>;
579 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&ccu CLK_BUS_OHCI0>,
581 <&ccu CLK_BUS_EHCI0>,
582 <&ccu CLK_USB_OHCI0>;
583 resets = <&ccu RST_BUS_OHCI0>,
584 <&ccu RST_BUS_EHCI0>;
585 status = "disabled";
586 };
587
588 ohci0: usb@1c1a400 {
589 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
590 reg = <0x01c1a400 0x100>;
591 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&ccu CLK_BUS_OHCI0>,
593 <&ccu CLK_USB_OHCI0>;
594 resets = <&ccu RST_BUS_OHCI0>;
595 status = "disabled";
596 };
597
598 ehci1: usb@1c1b000 {
599 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
600 reg = <0x01c1b000 0x100>;
601 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&ccu CLK_BUS_OHCI1>,
603 <&ccu CLK_BUS_EHCI1>,
604 <&ccu CLK_USB_OHCI1>;
605 resets = <&ccu RST_BUS_OHCI1>,
606 <&ccu RST_BUS_EHCI1>;
607 phys = <&usbphy 1>;
608 phy-names = "usb";
609 status = "disabled";
610 };
611
612 ohci1: usb@1c1b400 {
613 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
614 reg = <0x01c1b400 0x100>;
615 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&ccu CLK_BUS_OHCI1>,
617 <&ccu CLK_USB_OHCI1>;
618 resets = <&ccu RST_BUS_OHCI1>;
619 phys = <&usbphy 1>;
620 phy-names = "usb";
621 status = "disabled";
622 };
623
624 ccu: clock@1c20000 {
625 compatible = "allwinner,sun50i-a64-ccu";
626 reg = <0x01c20000 0x400>;
627 clocks = <&osc24M>, <&rtc 0>;
628 clock-names = "hosc", "losc";
629 #clock-cells = <1>;
630 #reset-cells = <1>;
631 };
632
633 pio: pinctrl@1c20800 {
634 compatible = "allwinner,sun50i-a64-pinctrl";
635 reg = <0x01c20800 0x400>;
636 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
640 clock-names = "apb", "hosc", "losc";
641 gpio-controller;
642 #gpio-cells = <3>;
643 interrupt-controller;
644 #interrupt-cells = <3>;
645
646 csi_pins: csi-pins {
647 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
648 "PE7", "PE8", "PE9", "PE10", "PE11";
649 function = "csi";
650 };
651
652 /omit-if-no-ref/
653 csi_mclk_pin: csi-mclk-pin {
654 pins = "PE1";
655 function = "csi";
656 };
657
658 i2c0_pins: i2c0-pins {
659 pins = "PH0", "PH1";
660 function = "i2c0";
661 };
662
663 i2c1_pins: i2c1-pins {
664 pins = "PH2", "PH3";
665 function = "i2c1";
666 };
667
668 i2c2_pins: i2c2-pins {
669 pins = "PE14", "PE15";
670 function = "i2c2";
671 };
672
673 /omit-if-no-ref/
674 lcd_rgb666_pins: lcd-rgb666-pins {
675 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
676 "PD5", "PD6", "PD7", "PD8", "PD9",
677 "PD10", "PD11", "PD12", "PD13",
678 "PD14", "PD15", "PD16", "PD17",
679 "PD18", "PD19", "PD20", "PD21";
680 function = "lcd0";
681 };
682
683 mmc0_pins: mmc0-pins {
684 pins = "PF0", "PF1", "PF2", "PF3",
685 "PF4", "PF5";
686 function = "mmc0";
687 drive-strength = <30>;
688 bias-pull-up;
689 };
690
691 mmc1_pins: mmc1-pins {
692 pins = "PG0", "PG1", "PG2", "PG3",
693 "PG4", "PG5";
694 function = "mmc1";
695 drive-strength = <30>;
696 bias-pull-up;
697 };
698
699 mmc2_pins: mmc2-pins {
700 pins = "PC5", "PC6", "PC8", "PC9",
701 "PC10","PC11", "PC12", "PC13",
702 "PC14", "PC15", "PC16";
703 function = "mmc2";
704 drive-strength = <30>;
705 bias-pull-up;
706 };
707
708 mmc2_ds_pin: mmc2-ds-pin {
709 pins = "PC1";
710 function = "mmc2";
711 drive-strength = <30>;
712 bias-pull-up;
713 };
714
715 pwm_pin: pwm-pin {
716 pins = "PD22";
717 function = "pwm";
718 };
719
720 rmii_pins: rmii-pins {
721 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
722 "PD18", "PD19", "PD20", "PD22", "PD23";
723 function = "emac";
724 drive-strength = <40>;
725 };
726
727 rgmii_pins: rgmii-pins {
728 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
729 "PD13", "PD15", "PD16", "PD17", "PD18",
730 "PD19", "PD20", "PD21", "PD22", "PD23";
731 function = "emac";
732 drive-strength = <40>;
733 };
734
735 spdif_tx_pin: spdif-tx-pin {
736 pins = "PH8";
737 function = "spdif";
738 };
739
740 spi0_pins: spi0-pins {
741 pins = "PC0", "PC1", "PC2", "PC3";
742 function = "spi0";
743 };
744
745 spi1_pins: spi1-pins {
746 pins = "PD0", "PD1", "PD2", "PD3";
747 function = "spi1";
748 };
749
750 uart0_pb_pins: uart0-pb-pins {
751 pins = "PB8", "PB9";
752 function = "uart0";
753 };
754
755 uart1_pins: uart1-pins {
756 pins = "PG6", "PG7";
757 function = "uart1";
758 };
759
760 uart1_rts_cts_pins: uart1-rts-cts-pins {
761 pins = "PG8", "PG9";
762 function = "uart1";
763 };
764
765 uart2_pins: uart2-pins {
766 pins = "PB0", "PB1";
767 function = "uart2";
768 };
769
770 uart3_pins: uart3-pins {
771 pins = "PD0", "PD1";
772 function = "uart3";
773 };
774
775 uart4_pins: uart4-pins {
776 pins = "PD2", "PD3";
777 function = "uart4";
778 };
779
780 uart4_rts_cts_pins: uart4-rts-cts-pins {
781 pins = "PD4", "PD5";
782 function = "uart4";
783 };
784 };
785
786 spdif: spdif@1c21000 {
787 #sound-dai-cells = <0>;
788 compatible = "allwinner,sun50i-a64-spdif",
789 "allwinner,sun8i-h3-spdif";
790 reg = <0x01c21000 0x400>;
791 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
793 resets = <&ccu RST_BUS_SPDIF>;
794 clock-names = "apb", "spdif";
795 dmas = <&dma 2>;
796 dma-names = "tx";
797 pinctrl-names = "default";
798 pinctrl-0 = <&spdif_tx_pin>;
799 status = "disabled";
800 };
801
802 lradc: lradc@1c21800 {
803 compatible = "allwinner,sun50i-a64-lradc",
804 "allwinner,sun8i-a83t-r-lradc";
805 reg = <0x01c21800 0x400>;
806 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
807 status = "disabled";
808 };
809
810 i2s0: i2s@1c22000 {
811 #sound-dai-cells = <0>;
812 compatible = "allwinner,sun50i-a64-i2s",
813 "allwinner,sun8i-h3-i2s";
814 reg = <0x01c22000 0x400>;
815 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
817 clock-names = "apb", "mod";
818 resets = <&ccu RST_BUS_I2S0>;
819 dma-names = "rx", "tx";
820 dmas = <&dma 3>, <&dma 3>;
821 status = "disabled";
822 };
823
824 i2s1: i2s@1c22400 {
825 #sound-dai-cells = <0>;
826 compatible = "allwinner,sun50i-a64-i2s",
827 "allwinner,sun8i-h3-i2s";
828 reg = <0x01c22400 0x400>;
829 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
831 clock-names = "apb", "mod";
832 resets = <&ccu RST_BUS_I2S1>;
833 dma-names = "rx", "tx";
834 dmas = <&dma 4>, <&dma 4>;
835 status = "disabled";
836 };
837
838 dai: dai@1c22c00 {
839 #sound-dai-cells = <0>;
840 compatible = "allwinner,sun50i-a64-codec-i2s";
841 reg = <0x01c22c00 0x200>;
842 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
844 clock-names = "apb", "mod";
845 resets = <&ccu RST_BUS_CODEC>;
846 dmas = <&dma 15>, <&dma 15>;
847 dma-names = "rx", "tx";
848 status = "disabled";
849 };
850
851 codec: codec@1c22e00 {
852 #sound-dai-cells = <0>;
853 compatible = "allwinner,sun8i-a33-codec";
854 reg = <0x01c22e00 0x600>;
855 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
857 clock-names = "bus", "mod";
858 status = "disabled";
859 };
860
861 ths: thermal-sensor@1c25000 {
862 compatible = "allwinner,sun50i-a64-ths";
863 reg = <0x01c25000 0x100>;
864 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
865 clock-names = "bus", "mod";
866 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
867 resets = <&ccu RST_BUS_THS>;
868 nvmem-cells = <&ths_calibration>;
869 nvmem-cell-names = "calibration";
870 #thermal-sensor-cells = <1>;
871 };
872
873 uart0: serial@1c28000 {
874 compatible = "snps,dw-apb-uart";
875 reg = <0x01c28000 0x400>;
876 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
877 reg-shift = <2>;
878 reg-io-width = <4>;
879 clocks = <&ccu CLK_BUS_UART0>;
880 resets = <&ccu RST_BUS_UART0>;
881 status = "disabled";
882 };
883
884 uart1: serial@1c28400 {
885 compatible = "snps,dw-apb-uart";
886 reg = <0x01c28400 0x400>;
887 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
888 reg-shift = <2>;
889 reg-io-width = <4>;
890 clocks = <&ccu CLK_BUS_UART1>;
891 resets = <&ccu RST_BUS_UART1>;
892 status = "disabled";
893 };
894
895 uart2: serial@1c28800 {
896 compatible = "snps,dw-apb-uart";
897 reg = <0x01c28800 0x400>;
898 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
899 reg-shift = <2>;
900 reg-io-width = <4>;
901 clocks = <&ccu CLK_BUS_UART2>;
902 resets = <&ccu RST_BUS_UART2>;
903 status = "disabled";
904 };
905
906 uart3: serial@1c28c00 {
907 compatible = "snps,dw-apb-uart";
908 reg = <0x01c28c00 0x400>;
909 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
910 reg-shift = <2>;
911 reg-io-width = <4>;
912 clocks = <&ccu CLK_BUS_UART3>;
913 resets = <&ccu RST_BUS_UART3>;
914 status = "disabled";
915 };
916
917 uart4: serial@1c29000 {
918 compatible = "snps,dw-apb-uart";
919 reg = <0x01c29000 0x400>;
920 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
921 reg-shift = <2>;
922 reg-io-width = <4>;
923 clocks = <&ccu CLK_BUS_UART4>;
924 resets = <&ccu RST_BUS_UART4>;
925 status = "disabled";
926 };
927
928 i2c0: i2c@1c2ac00 {
929 compatible = "allwinner,sun6i-a31-i2c";
930 reg = <0x01c2ac00 0x400>;
931 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&ccu CLK_BUS_I2C0>;
933 resets = <&ccu RST_BUS_I2C0>;
934 pinctrl-names = "default";
935 pinctrl-0 = <&i2c0_pins>;
936 status = "disabled";
937 #address-cells = <1>;
938 #size-cells = <0>;
939 };
940
941 i2c1: i2c@1c2b000 {
942 compatible = "allwinner,sun6i-a31-i2c";
943 reg = <0x01c2b000 0x400>;
944 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&ccu CLK_BUS_I2C1>;
946 resets = <&ccu RST_BUS_I2C1>;
947 pinctrl-names = "default";
948 pinctrl-0 = <&i2c1_pins>;
949 status = "disabled";
950 #address-cells = <1>;
951 #size-cells = <0>;
952 };
953
954 i2c2: i2c@1c2b400 {
955 compatible = "allwinner,sun6i-a31-i2c";
956 reg = <0x01c2b400 0x400>;
957 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&ccu CLK_BUS_I2C2>;
959 resets = <&ccu RST_BUS_I2C2>;
960 pinctrl-names = "default";
961 pinctrl-0 = <&i2c2_pins>;
962 status = "disabled";
963 #address-cells = <1>;
964 #size-cells = <0>;
965 };
966
967 spi0: spi@1c68000 {
968 compatible = "allwinner,sun8i-h3-spi";
969 reg = <0x01c68000 0x1000>;
970 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
972 clock-names = "ahb", "mod";
973 dmas = <&dma 23>, <&dma 23>;
974 dma-names = "rx", "tx";
975 pinctrl-names = "default";
976 pinctrl-0 = <&spi0_pins>;
977 resets = <&ccu RST_BUS_SPI0>;
978 status = "disabled";
979 num-cs = <1>;
980 #address-cells = <1>;
981 #size-cells = <0>;
982 };
983
984 spi1: spi@1c69000 {
985 compatible = "allwinner,sun8i-h3-spi";
986 reg = <0x01c69000 0x1000>;
987 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
989 clock-names = "ahb", "mod";
990 dmas = <&dma 24>, <&dma 24>;
991 dma-names = "rx", "tx";
992 pinctrl-names = "default";
993 pinctrl-0 = <&spi1_pins>;
994 resets = <&ccu RST_BUS_SPI1>;
995 status = "disabled";
996 num-cs = <1>;
997 #address-cells = <1>;
998 #size-cells = <0>;
999 };
1000
1001 emac: ethernet@1c30000 {
1002 compatible = "allwinner,sun50i-a64-emac";
1003 syscon = <&syscon>;
1004 reg = <0x01c30000 0x10000>;
1005 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1006 interrupt-names = "macirq";
1007 resets = <&ccu RST_BUS_EMAC>;
1008 reset-names = "stmmaceth";
1009 clocks = <&ccu CLK_BUS_EMAC>;
1010 clock-names = "stmmaceth";
1011 status = "disabled";
1012
1013 mdio: mdio {
1014 compatible = "snps,dwmac-mdio";
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017 };
1018 };
1019
1020 mali: gpu@1c40000 {
1021 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1022 reg = <0x01c40000 0x10000>;
1023 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1028 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1029 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1030 interrupt-names = "gp",
1031 "gpmmu",
1032 "pp0",
1033 "ppmmu0",
1034 "pp1",
1035 "ppmmu1",
1036 "pmu";
1037 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1038 clock-names = "bus", "core";
1039 resets = <&ccu RST_BUS_GPU>;
1040 };
1041
1042 gic: interrupt-controller@1c81000 {
1043 compatible = "arm,gic-400";
1044 reg = <0x01c81000 0x1000>,
1045 <0x01c82000 0x2000>,
1046 <0x01c84000 0x2000>,
1047 <0x01c86000 0x2000>;
1048 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1049 interrupt-controller;
1050 #interrupt-cells = <3>;
1051 };
1052
1053 pwm: pwm@1c21400 {
1054 compatible = "allwinner,sun50i-a64-pwm",
1055 "allwinner,sun5i-a13-pwm";
1056 reg = <0x01c21400 0x400>;
1057 clocks = <&osc24M>;
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&pwm_pin>;
1060 #pwm-cells = <3>;
1061 status = "disabled";
1062 };
1063
1064 mbus: dram-controller@1c62000 {
1065 compatible = "allwinner,sun50i-a64-mbus";
1066 reg = <0x01c62000 0x1000>;
1067 clocks = <&ccu 112>;
1068 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1069 #interconnect-cells = <1>;
1070 };
1071
1072 csi: csi@1cb0000 {
1073 compatible = "allwinner,sun50i-a64-csi";
1074 reg = <0x01cb0000 0x1000>;
1075 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&ccu CLK_BUS_CSI>,
1077 <&ccu CLK_CSI_SCLK>,
1078 <&ccu CLK_DRAM_CSI>;
1079 clock-names = "bus", "mod", "ram";
1080 resets = <&ccu RST_BUS_CSI>;
1081 pinctrl-names = "default";
1082 pinctrl-0 = <&csi_pins>;
1083 status = "disabled";
1084 };
1085
1086 dsi: dsi@1ca0000 {
1087 compatible = "allwinner,sun50i-a64-mipi-dsi";
1088 reg = <0x01ca0000 0x1000>;
1089 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1090 clocks = <&ccu CLK_BUS_MIPI_DSI>;
1091 resets = <&ccu RST_BUS_MIPI_DSI>;
1092 phys = <&dphy>;
1093 phy-names = "dphy";
1094 status = "disabled";
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1097
1098 port {
1099 dsi_in_tcon0: endpoint {
1100 remote-endpoint = <&tcon0_out_dsi>;
1101 };
1102 };
1103 };
1104
1105 dphy: d-phy@1ca1000 {
1106 compatible = "allwinner,sun50i-a64-mipi-dphy",
1107 "allwinner,sun6i-a31-mipi-dphy";
1108 reg = <0x01ca1000 0x1000>;
1109 clocks = <&ccu CLK_BUS_MIPI_DSI>,
1110 <&ccu CLK_DSI_DPHY>;
1111 clock-names = "bus", "mod";
1112 resets = <&ccu RST_BUS_MIPI_DSI>;
1113 status = "disabled";
1114 #phy-cells = <0>;
1115 };
1116
1117 deinterlace: deinterlace@1e00000 {
1118 compatible = "allwinner,sun50i-a64-deinterlace",
1119 "allwinner,sun8i-h3-deinterlace";
1120 reg = <0x01e00000 0x20000>;
1121 clocks = <&ccu CLK_BUS_DEINTERLACE>,
1122 <&ccu CLK_DEINTERLACE>,
1123 <&ccu CLK_DRAM_DEINTERLACE>;
1124 clock-names = "bus", "mod", "ram";
1125 resets = <&ccu RST_BUS_DEINTERLACE>;
1126 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1127 interconnects = <&mbus 9>;
1128 interconnect-names = "dma-mem";
1129 };
1130
1131 hdmi: hdmi@1ee0000 {
1132 compatible = "allwinner,sun50i-a64-dw-hdmi",
1133 "allwinner,sun8i-a83t-dw-hdmi";
1134 reg = <0x01ee0000 0x10000>;
1135 reg-io-width = <1>;
1136 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1137 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1138 <&ccu CLK_HDMI>;
1139 clock-names = "iahb", "isfr", "tmds";
1140 resets = <&ccu RST_BUS_HDMI1>;
1141 reset-names = "ctrl";
1142 phys = <&hdmi_phy>;
1143 phy-names = "phy";
1144 status = "disabled";
1145
1146 ports {
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1149
1150 hdmi_in: port@0 {
1151 reg = <0>;
1152
1153 hdmi_in_tcon1: endpoint {
1154 remote-endpoint = <&tcon1_out_hdmi>;
1155 };
1156 };
1157
1158 hdmi_out: port@1 {
1159 reg = <1>;
1160 };
1161 };
1162 };
1163
1164 hdmi_phy: hdmi-phy@1ef0000 {
1165 compatible = "allwinner,sun50i-a64-hdmi-phy";
1166 reg = <0x01ef0000 0x10000>;
1167 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1168 <&ccu CLK_PLL_VIDEO0>;
1169 clock-names = "bus", "mod", "pll-0";
1170 resets = <&ccu RST_BUS_HDMI0>;
1171 reset-names = "phy";
1172 #phy-cells = <0>;
1173 };
1174
1175 rtc: rtc@1f00000 {
1176 compatible = "allwinner,sun50i-a64-rtc",
1177 "allwinner,sun8i-h3-rtc";
1178 reg = <0x01f00000 0x400>;
1179 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1180 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1181 clock-output-names = "osc32k", "osc32k-out", "iosc";
1182 clocks = <&osc32k>;
1183 #clock-cells = <1>;
1184 };
1185
1186 r_intc: interrupt-controller@1f00c00 {
1187 compatible = "allwinner,sun50i-a64-r-intc",
1188 "allwinner,sun6i-a31-r-intc";
1189 interrupt-controller;
1190 #interrupt-cells = <2>;
1191 reg = <0x01f00c00 0x400>;
1192 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1193 };
1194
1195 r_ccu: clock@1f01400 {
1196 compatible = "allwinner,sun50i-a64-r-ccu";
1197 reg = <0x01f01400 0x100>;
1198 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1199 <&ccu CLK_PLL_PERIPH0>;
1200 clock-names = "hosc", "losc", "iosc", "pll-periph";
1201 #clock-cells = <1>;
1202 #reset-cells = <1>;
1203 };
1204
1205 codec_analog: codec-analog@1f015c0 {
1206 compatible = "allwinner,sun50i-a64-codec-analog";
1207 reg = <0x01f015c0 0x4>;
1208 status = "disabled";
1209 };
1210
1211 r_i2c: i2c@1f02400 {
1212 compatible = "allwinner,sun50i-a64-i2c",
1213 "allwinner,sun6i-a31-i2c";
1214 reg = <0x01f02400 0x400>;
1215 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1216 clocks = <&r_ccu CLK_APB0_I2C>;
1217 resets = <&r_ccu RST_APB0_I2C>;
1218 status = "disabled";
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1221 };
1222
1223 r_ir: ir@1f02000 {
1224 compatible = "allwinner,sun50i-a64-ir",
1225 "allwinner,sun6i-a31-ir";
1226 reg = <0x01f02000 0x400>;
1227 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1228 clock-names = "apb", "ir";
1229 resets = <&r_ccu RST_APB0_IR>;
1230 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1231 pinctrl-names = "default";
1232 pinctrl-0 = <&r_ir_rx_pin>;
1233 status = "disabled";
1234 };
1235
1236 r_pwm: pwm@1f03800 {
1237 compatible = "allwinner,sun50i-a64-pwm",
1238 "allwinner,sun5i-a13-pwm";
1239 reg = <0x01f03800 0x400>;
1240 clocks = <&osc24M>;
1241 pinctrl-names = "default";
1242 pinctrl-0 = <&r_pwm_pin>;
1243 #pwm-cells = <3>;
1244 status = "disabled";
1245 };
1246
1247 r_pio: pinctrl@1f02c00 {
1248 compatible = "allwinner,sun50i-a64-r-pinctrl";
1249 reg = <0x01f02c00 0x400>;
1250 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1251 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1252 clock-names = "apb", "hosc", "losc";
1253 gpio-controller;
1254 #gpio-cells = <3>;
1255 interrupt-controller;
1256 #interrupt-cells = <3>;
1257
1258 r_i2c_pl89_pins: r-i2c-pl89-pins {
1259 pins = "PL8", "PL9";
1260 function = "s_i2c";
1261 };
1262
1263 r_ir_rx_pin: r-ir-rx-pin {
1264 pins = "PL11";
1265 function = "s_cir_rx";
1266 };
1267
1268 r_pwm_pin: r-pwm-pin {
1269 pins = "PL10";
1270 function = "s_pwm";
1271 };
1272
1273 r_rsb_pins: r-rsb-pins {
1274 pins = "PL0", "PL1";
1275 function = "s_rsb";
1276 };
1277 };
1278
1279 r_rsb: rsb@1f03400 {
1280 compatible = "allwinner,sun8i-a23-rsb";
1281 reg = <0x01f03400 0x400>;
1282 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1283 clocks = <&r_ccu 6>;
1284 clock-frequency = <3000000>;
1285 resets = <&r_ccu 2>;
1286 pinctrl-names = "default";
1287 pinctrl-0 = <&r_rsb_pins>;
1288 status = "disabled";
1289 #address-cells = <1>;
1290 #size-cells = <0>;
1291 };
1292
1293 wdt0: watchdog@1c20ca0 {
1294 compatible = "allwinner,sun50i-a64-wdt",
1295 "allwinner,sun6i-a31-wdt";
1296 reg = <0x01c20ca0 0x20>;
1297 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&osc24M>;
1299 };
1300 };
1301 };
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