]> git.ipfire.org Git - thirdparty/linux.git/blob - arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
projects / thirdparty / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'x86-fpu-2020-06-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
[thirdparty/linux.git] / arch / arm64 / boot / dts / amlogic / meson-g12-common.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */
5
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
14
15 / {
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 chosen {
21 #address-cells = <2>;
22 #size-cells = <2>;
23 ranges;
24
25 simplefb_cvbs: framebuffer-cvbs {
26 compatible = "amlogic,simple-framebuffer",
27 "simple-framebuffer";
28 amlogic,pipeline = "vpu-cvbs";
29 clocks = <&clkc CLKID_HDMI>,
30 <&clkc CLKID_HTX_PCLK>,
31 <&clkc CLKID_VPU_INTR>;
32 status = "disabled";
33 };
34
35 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "amlogic,simple-framebuffer",
37 "simple-framebuffer";
38 amlogic,pipeline = "vpu-hdmi";
39 clocks = <&clkc CLKID_HDMI>,
40 <&clkc CLKID_HTX_PCLK>,
41 <&clkc CLKID_VPU_INTR>;
42 status = "disabled";
43 };
44 };
45
46 efuse: efuse {
47 compatible = "amlogic,meson-gxbb-efuse";
48 clocks = <&clkc CLKID_EFUSE>;
49 #address-cells = <1>;
50 #size-cells = <1>;
51 read-only;
52 secure-monitor = <&sm>;
53 };
54
55 psci {
56 compatible = "arm,psci-1.0";
57 method = "smc";
58 };
59
60 reserved-memory {
61 #address-cells = <2>;
62 #size-cells = <2>;
63 ranges;
64
65 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
66 secmon_reserved: secmon@5000000 {
67 reg = <0x0 0x05000000 0x0 0x300000>;
68 no-map;
69 };
70
71 linux,cma {
72 compatible = "shared-dma-pool";
73 reusable;
74 size = <0x0 0x10000000>;
75 alignment = <0x0 0x400000>;
76 linux,cma-default;
77 };
78 };
79
80 sm: secure-monitor {
81 compatible = "amlogic,meson-gxbb-sm";
82 };
83
84 soc {
85 compatible = "simple-bus";
86 #address-cells = <2>;
87 #size-cells = <2>;
88 ranges;
89
90 pcie: pcie@fc000000 {
91 compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
92 reg = <0x0 0xfc000000 0x0 0x400000
93 0x0 0xff648000 0x0 0x2000
94 0x0 0xfc400000 0x0 0x200000>;
95 reg-names = "elbi", "cfg", "config";
96 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
97 #interrupt-cells = <1>;
98 interrupt-map-mask = <0 0 0 0>;
99 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
100 bus-range = <0x0 0xff>;
101 #address-cells = <3>;
102 #size-cells = <2>;
103 device_type = "pci";
104 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
105 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
106
107 clocks = <&clkc CLKID_PCIE_PHY
108 &clkc CLKID_PCIE_COMB
109 &clkc CLKID_PCIE_PLL>;
110 clock-names = "general",
111 "pclk",
112 "port";
113 resets = <&reset RESET_PCIE_CTRL_A>,
114 <&reset RESET_PCIE_APB>;
115 reset-names = "port",
116 "apb";
117 num-lanes = <1>;
118 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
119 phy-names = "pcie";
120 status = "disabled";
121 };
122
123 thermal-zones {
124 cpu_thermal: cpu-thermal {
125 polling-delay = <1000>;
126 polling-delay-passive = <100>;
127 thermal-sensors = <&cpu_temp>;
128
129 trips {
130 cpu_passive: cpu-passive {
131 temperature = <85000>; /* millicelsius */
132 hysteresis = <2000>; /* millicelsius */
133 type = "passive";
134 };
135
136 cpu_hot: cpu-hot {
137 temperature = <95000>; /* millicelsius */
138 hysteresis = <2000>; /* millicelsius */
139 type = "hot";
140 };
141
142 cpu_critical: cpu-critical {
143 temperature = <110000>; /* millicelsius */
144 hysteresis = <2000>; /* millicelsius */
145 type = "critical";
146 };
147 };
148 };
149
150 ddr_thermal: ddr-thermal {
151 polling-delay = <1000>;
152 polling-delay-passive = <100>;
153 thermal-sensors = <&ddr_temp>;
154
155 trips {
156 ddr_passive: ddr-passive {
157 temperature = <85000>; /* millicelsius */
158 hysteresis = <2000>; /* millicelsius */
159 type = "passive";
160 };
161
162 ddr_critical: ddr-critical {
163 temperature = <110000>; /* millicelsius */
164 hysteresis = <2000>; /* millicelsius */
165 type = "critical";
166 };
167 };
168
169 cooling-maps {
170 map {
171 trip = <&ddr_passive>;
172 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
173 };
174 };
175 };
176 };
177
178 ethmac: ethernet@ff3f0000 {
179 compatible = "amlogic,meson-axg-dwmac",
180 "snps,dwmac-3.70a",
181 "snps,dwmac";
182 reg = <0x0 0xff3f0000 0x0 0x10000>,
183 <0x0 0xff634540 0x0 0x8>;
184 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-names = "macirq";
186 clocks = <&clkc CLKID_ETH>,
187 <&clkc CLKID_FCLK_DIV2>,
188 <&clkc CLKID_MPLL2>;
189 clock-names = "stmmaceth", "clkin0", "clkin1";
190 rx-fifo-depth = <4096>;
191 tx-fifo-depth = <2048>;
192 status = "disabled";
193
194 mdio0: mdio {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "snps,dwmac-mdio";
198 };
199 };
200
201 apb: bus@ff600000 {
202 compatible = "simple-bus";
203 reg = <0x0 0xff600000 0x0 0x200000>;
204 #address-cells = <2>;
205 #size-cells = <2>;
206 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
207
208 hdmi_tx: hdmi-tx@0 {
209 compatible = "amlogic,meson-g12a-dw-hdmi";
210 reg = <0x0 0x0 0x0 0x10000>;
211 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
212 resets = <&reset RESET_HDMITX_CAPB3>,
213 <&reset RESET_HDMITX_PHY>,
214 <&reset RESET_HDMITX>;
215 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
216 clocks = <&clkc CLKID_HDMI>,
217 <&clkc CLKID_HTX_PCLK>,
218 <&clkc CLKID_VPU_INTR>;
219 clock-names = "isfr", "iahb", "venci";
220 #address-cells = <1>;
221 #size-cells = <0>;
222 #sound-dai-cells = <0>;
223 status = "disabled";
224
225 /* VPU VENC Input */
226 hdmi_tx_venc_port: port@0 {
227 reg = <0>;
228
229 hdmi_tx_in: endpoint {
230 remote-endpoint = <&hdmi_tx_out>;
231 };
232 };
233
234 /* TMDS Output */
235 hdmi_tx_tmds_port: port@1 {
236 reg = <1>;
237 };
238 };
239
240 apb_efuse: bus@30000 {
241 compatible = "simple-bus";
242 reg = <0x0 0x30000 0x0 0x2000>;
243 #address-cells = <2>;
244 #size-cells = <2>;
245 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
246
247 hwrng: rng@218 {
248 compatible = "amlogic,meson-rng";
249 reg = <0x0 0x218 0x0 0x4>;
250 };
251 };
252
253 periphs: bus@34400 {
254 compatible = "simple-bus";
255 reg = <0x0 0x34400 0x0 0x400>;
256 #address-cells = <2>;
257 #size-cells = <2>;
258 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
259
260 periphs_pinctrl: pinctrl@40 {
261 compatible = "amlogic,meson-g12a-periphs-pinctrl";
262 #address-cells = <2>;
263 #size-cells = <2>;
264 ranges;
265
266 gpio: bank@40 {
267 reg = <0x0 0x40 0x0 0x4c>,
268 <0x0 0xe8 0x0 0x18>,
269 <0x0 0x120 0x0 0x18>,
270 <0x0 0x2c0 0x0 0x40>,
271 <0x0 0x340 0x0 0x1c>;
272 reg-names = "gpio",
273 "pull",
274 "pull-enable",
275 "mux",
276 "ds";
277 gpio-controller;
278 #gpio-cells = <2>;
279 gpio-ranges = <&periphs_pinctrl 0 0 86>;
280 };
281
282 cec_ao_a_h_pins: cec_ao_a_h {
283 mux {
284 groups = "cec_ao_a_h";
285 function = "cec_ao_a_h";
286 bias-disable;
287 };
288 };
289
290 cec_ao_b_h_pins: cec_ao_b_h {
291 mux {
292 groups = "cec_ao_b_h";
293 function = "cec_ao_b_h";
294 bias-disable;
295 };
296 };
297
298 emmc_ctrl_pins: emmc-ctrl {
299 mux-0 {
300 groups = "emmc_cmd";
301 function = "emmc";
302 bias-pull-up;
303 drive-strength-microamp = <4000>;
304 };
305
306 mux-1 {
307 groups = "emmc_clk";
308 function = "emmc";
309 bias-disable;
310 drive-strength-microamp = <4000>;
311 };
312 };
313
314 emmc_data_4b_pins: emmc-data-4b {
315 mux-0 {
316 groups = "emmc_nand_d0",
317 "emmc_nand_d1",
318 "emmc_nand_d2",
319 "emmc_nand_d3";
320 function = "emmc";
321 bias-pull-up;
322 drive-strength-microamp = <4000>;
323 };
324 };
325
326 emmc_data_8b_pins: emmc-data-8b {
327 mux-0 {
328 groups = "emmc_nand_d0",
329 "emmc_nand_d1",
330 "emmc_nand_d2",
331 "emmc_nand_d3",
332 "emmc_nand_d4",
333 "emmc_nand_d5",
334 "emmc_nand_d6",
335 "emmc_nand_d7";
336 function = "emmc";
337 bias-pull-up;
338 drive-strength-microamp = <4000>;
339 };
340 };
341
342 emmc_ds_pins: emmc-ds {
343 mux {
344 groups = "emmc_nand_ds";
345 function = "emmc";
346 bias-pull-down;
347 drive-strength-microamp = <4000>;
348 };
349 };
350
351 emmc_clk_gate_pins: emmc_clk_gate {
352 mux {
353 groups = "BOOT_8";
354 function = "gpio_periphs";
355 bias-pull-down;
356 drive-strength-microamp = <4000>;
357 };
358 };
359
360 hdmitx_ddc_pins: hdmitx_ddc {
361 mux {
362 groups = "hdmitx_sda",
363 "hdmitx_sck";
364 function = "hdmitx";
365 bias-disable;
366 drive-strength-microamp = <4000>;
367 };
368 };
369
370 hdmitx_hpd_pins: hdmitx_hpd {
371 mux {
372 groups = "hdmitx_hpd_in";
373 function = "hdmitx";
374 bias-disable;
375 };
376 };
377
378
379 i2c0_sda_c_pins: i2c0-sda-c {
380 mux {
381 groups = "i2c0_sda_c";
382 function = "i2c0";
383 bias-disable;
384 drive-strength-microamp = <3000>;
385
386 };
387 };
388
389 i2c0_sck_c_pins: i2c0-sck-c {
390 mux {
391 groups = "i2c0_sck_c";
392 function = "i2c0";
393 bias-disable;
394 drive-strength-microamp = <3000>;
395 };
396 };
397
398 i2c0_sda_z0_pins: i2c0-sda-z0 {
399 mux {
400 groups = "i2c0_sda_z0";
401 function = "i2c0";
402 bias-disable;
403 drive-strength-microamp = <3000>;
404 };
405 };
406
407 i2c0_sck_z1_pins: i2c0-sck-z1 {
408 mux {
409 groups = "i2c0_sck_z1";
410 function = "i2c0";
411 bias-disable;
412 drive-strength-microamp = <3000>;
413 };
414 };
415
416 i2c0_sda_z7_pins: i2c0-sda-z7 {
417 mux {
418 groups = "i2c0_sda_z7";
419 function = "i2c0";
420 bias-disable;
421 drive-strength-microamp = <3000>;
422 };
423 };
424
425 i2c0_sda_z8_pins: i2c0-sda-z8 {
426 mux {
427 groups = "i2c0_sda_z8";
428 function = "i2c0";
429 bias-disable;
430 drive-strength-microamp = <3000>;
431 };
432 };
433
434 i2c1_sda_x_pins: i2c1-sda-x {
435 mux {
436 groups = "i2c1_sda_x";
437 function = "i2c1";
438 bias-disable;
439 drive-strength-microamp = <3000>;
440 };
441 };
442
443 i2c1_sck_x_pins: i2c1-sck-x {
444 mux {
445 groups = "i2c1_sck_x";
446 function = "i2c1";
447 bias-disable;
448 drive-strength-microamp = <3000>;
449 };
450 };
451
452 i2c1_sda_h2_pins: i2c1-sda-h2 {
453 mux {
454 groups = "i2c1_sda_h2";
455 function = "i2c1";
456 bias-disable;
457 drive-strength-microamp = <3000>;
458 };
459 };
460
461 i2c1_sck_h3_pins: i2c1-sck-h3 {
462 mux {
463 groups = "i2c1_sck_h3";
464 function = "i2c1";
465 bias-disable;
466 drive-strength-microamp = <3000>;
467 };
468 };
469
470 i2c1_sda_h6_pins: i2c1-sda-h6 {
471 mux {
472 groups = "i2c1_sda_h6";
473 function = "i2c1";
474 bias-disable;
475 drive-strength-microamp = <3000>;
476 };
477 };
478
479 i2c1_sck_h7_pins: i2c1-sck-h7 {
480 mux {
481 groups = "i2c1_sck_h7";
482 function = "i2c1";
483 bias-disable;
484 drive-strength-microamp = <3000>;
485 };
486 };
487
488 i2c2_sda_x_pins: i2c2-sda-x {
489 mux {
490 groups = "i2c2_sda_x";
491 function = "i2c2";
492 bias-disable;
493 drive-strength-microamp = <3000>;
494 };
495 };
496
497 i2c2_sck_x_pins: i2c2-sck-x {
498 mux {
499 groups = "i2c2_sck_x";
500 function = "i2c2";
501 bias-disable;
502 drive-strength-microamp = <3000>;
503 };
504 };
505
506 i2c2_sda_z_pins: i2c2-sda-z {
507 mux {
508 groups = "i2c2_sda_z";
509 function = "i2c2";
510 bias-disable;
511 drive-strength-microamp = <3000>;
512 };
513 };
514
515 i2c2_sck_z_pins: i2c2-sck-z {
516 mux {
517 groups = "i2c2_sck_z";
518 function = "i2c2";
519 bias-disable;
520 drive-strength-microamp = <3000>;
521 };
522 };
523
524 i2c3_sda_h_pins: i2c3-sda-h {
525 mux {
526 groups = "i2c3_sda_h";
527 function = "i2c3";
528 bias-disable;
529 drive-strength-microamp = <3000>;
530 };
531 };
532
533 i2c3_sck_h_pins: i2c3-sck-h {
534 mux {
535 groups = "i2c3_sck_h";
536 function = "i2c3";
537 bias-disable;
538 drive-strength-microamp = <3000>;
539 };
540 };
541
542 i2c3_sda_a_pins: i2c3-sda-a {
543 mux {
544 groups = "i2c3_sda_a";
545 function = "i2c3";
546 bias-disable;
547 drive-strength-microamp = <3000>;
548 };
549 };
550
551 i2c3_sck_a_pins: i2c3-sck-a {
552 mux {
553 groups = "i2c3_sck_a";
554 function = "i2c3";
555 bias-disable;
556 drive-strength-microamp = <3000>;
557 };
558 };
559
560 mclk0_a_pins: mclk0-a {
561 mux {
562 groups = "mclk0_a";
563 function = "mclk0";
564 bias-disable;
565 drive-strength-microamp = <3000>;
566 };
567 };
568
569 mclk1_a_pins: mclk1-a {
570 mux {
571 groups = "mclk1_a";
572 function = "mclk1";
573 bias-disable;
574 drive-strength-microamp = <3000>;
575 };
576 };
577
578 mclk1_x_pins: mclk1-x {
579 mux {
580 groups = "mclk1_x";
581 function = "mclk1";
582 bias-disable;
583 drive-strength-microamp = <3000>;
584 };
585 };
586
587 mclk1_z_pins: mclk1-z {
588 mux {
589 groups = "mclk1_z";
590 function = "mclk1";
591 bias-disable;
592 drive-strength-microamp = <3000>;
593 };
594 };
595
596 nor_pins: nor {
597 mux {
598 groups = "nor_d",
599 "nor_q",
600 "nor_c",
601 "nor_cs";
602 function = "nor";
603 bias-disable;
604 };
605 };
606
607 pdm_din0_a_pins: pdm-din0-a {
608 mux {
609 groups = "pdm_din0_a";
610 function = "pdm";
611 bias-disable;
612 };
613 };
614
615 pdm_din0_c_pins: pdm-din0-c {
616 mux {
617 groups = "pdm_din0_c";
618 function = "pdm";
619 bias-disable;
620 };
621 };
622
623 pdm_din0_x_pins: pdm-din0-x {
624 mux {
625 groups = "pdm_din0_x";
626 function = "pdm";
627 bias-disable;
628 };
629 };
630
631 pdm_din0_z_pins: pdm-din0-z {
632 mux {
633 groups = "pdm_din0_z";
634 function = "pdm";
635 bias-disable;
636 };
637 };
638
639 pdm_din1_a_pins: pdm-din1-a {
640 mux {
641 groups = "pdm_din1_a";
642 function = "pdm";
643 bias-disable;
644 };
645 };
646
647 pdm_din1_c_pins: pdm-din1-c {
648 mux {
649 groups = "pdm_din1_c";
650 function = "pdm";
651 bias-disable;
652 };
653 };
654
655 pdm_din1_x_pins: pdm-din1-x {
656 mux {
657 groups = "pdm_din1_x";
658 function = "pdm";
659 bias-disable;
660 };
661 };
662
663 pdm_din1_z_pins: pdm-din1-z {
664 mux {
665 groups = "pdm_din1_z";
666 function = "pdm";
667 bias-disable;
668 };
669 };
670
671 pdm_din2_a_pins: pdm-din2-a {
672 mux {
673 groups = "pdm_din2_a";
674 function = "pdm";
675 bias-disable;
676 };
677 };
678
679 pdm_din2_c_pins: pdm-din2-c {
680 mux {
681 groups = "pdm_din2_c";
682 function = "pdm";
683 bias-disable;
684 };
685 };
686
687 pdm_din2_x_pins: pdm-din2-x {
688 mux {
689 groups = "pdm_din2_x";
690 function = "pdm";
691 bias-disable;
692 };
693 };
694
695 pdm_din2_z_pins: pdm-din2-z {
696 mux {
697 groups = "pdm_din2_z";
698 function = "pdm";
699 bias-disable;
700 };
701 };
702
703 pdm_din3_a_pins: pdm-din3-a {
704 mux {
705 groups = "pdm_din3_a";
706 function = "pdm";
707 bias-disable;
708 };
709 };
710
711 pdm_din3_c_pins: pdm-din3-c {
712 mux {
713 groups = "pdm_din3_c";
714 function = "pdm";
715 bias-disable;
716 };
717 };
718
719 pdm_din3_x_pins: pdm-din3-x {
720 mux {
721 groups = "pdm_din3_x";
722 function = "pdm";
723 bias-disable;
724 };
725 };
726
727 pdm_din3_z_pins: pdm-din3-z {
728 mux {
729 groups = "pdm_din3_z";
730 function = "pdm";
731 bias-disable;
732 };
733 };
734
735 pdm_dclk_a_pins: pdm-dclk-a {
736 mux {
737 groups = "pdm_dclk_a";
738 function = "pdm";
739 bias-disable;
740 drive-strength-microamp = <500>;
741 };
742 };
743
744 pdm_dclk_c_pins: pdm-dclk-c {
745 mux {
746 groups = "pdm_dclk_c";
747 function = "pdm";
748 bias-disable;
749 drive-strength-microamp = <500>;
750 };
751 };
752
753 pdm_dclk_x_pins: pdm-dclk-x {
754 mux {
755 groups = "pdm_dclk_x";
756 function = "pdm";
757 bias-disable;
758 drive-strength-microamp = <500>;
759 };
760 };
761
762 pdm_dclk_z_pins: pdm-dclk-z {
763 mux {
764 groups = "pdm_dclk_z";
765 function = "pdm";
766 bias-disable;
767 drive-strength-microamp = <500>;
768 };
769 };
770
771 pwm_a_pins: pwm-a {
772 mux {
773 groups = "pwm_a";
774 function = "pwm_a";
775 bias-disable;
776 };
777 };
778
779 pwm_b_x7_pins: pwm-b-x7 {
780 mux {
781 groups = "pwm_b_x7";
782 function = "pwm_b";
783 bias-disable;
784 };
785 };
786
787 pwm_b_x19_pins: pwm-b-x19 {
788 mux {
789 groups = "pwm_b_x19";
790 function = "pwm_b";
791 bias-disable;
792 };
793 };
794
795 pwm_c_c_pins: pwm-c-c {
796 mux {
797 groups = "pwm_c_c";
798 function = "pwm_c";
799 bias-disable;
800 };
801 };
802
803 pwm_c_x5_pins: pwm-c-x5 {
804 mux {
805 groups = "pwm_c_x5";
806 function = "pwm_c";
807 bias-disable;
808 };
809 };
810
811 pwm_c_x8_pins: pwm-c-x8 {
812 mux {
813 groups = "pwm_c_x8";
814 function = "pwm_c";
815 bias-disable;
816 };
817 };
818
819 pwm_d_x3_pins: pwm-d-x3 {
820 mux {
821 groups = "pwm_d_x3";
822 function = "pwm_d";
823 bias-disable;
824 };
825 };
826
827 pwm_d_x6_pins: pwm-d-x6 {
828 mux {
829 groups = "pwm_d_x6";
830 function = "pwm_d";
831 bias-disable;
832 };
833 };
834
835 pwm_e_pins: pwm-e {
836 mux {
837 groups = "pwm_e";
838 function = "pwm_e";
839 bias-disable;
840 };
841 };
842
843 pwm_f_x_pins: pwm-f-x {
844 mux {
845 groups = "pwm_f_x";
846 function = "pwm_f";
847 bias-disable;
848 };
849 };
850
851 pwm_f_h_pins: pwm-f-h {
852 mux {
853 groups = "pwm_f_h";
854 function = "pwm_f";
855 bias-disable;
856 };
857 };
858
859 sdcard_c_pins: sdcard_c {
860 mux-0 {
861 groups = "sdcard_d0_c",
862 "sdcard_d1_c",
863 "sdcard_d2_c",
864 "sdcard_d3_c",
865 "sdcard_cmd_c";
866 function = "sdcard";
867 bias-pull-up;
868 drive-strength-microamp = <4000>;
869 };
870
871 mux-1 {
872 groups = "sdcard_clk_c";
873 function = "sdcard";
874 bias-disable;
875 drive-strength-microamp = <4000>;
876 };
877 };
878
879 sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
880 mux {
881 groups = "GPIOC_4";
882 function = "gpio_periphs";
883 bias-pull-down;
884 drive-strength-microamp = <4000>;
885 };
886 };
887
888 sdcard_z_pins: sdcard_z {
889 mux-0 {
890 groups = "sdcard_d0_z",
891 "sdcard_d1_z",
892 "sdcard_d2_z",
893 "sdcard_d3_z",
894 "sdcard_cmd_z";
895 function = "sdcard";
896 bias-pull-up;
897 drive-strength-microamp = <4000>;
898 };
899
900 mux-1 {
901 groups = "sdcard_clk_z";
902 function = "sdcard";
903 bias-disable;
904 drive-strength-microamp = <4000>;
905 };
906 };
907
908 sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
909 mux {
910 groups = "GPIOZ_6";
911 function = "gpio_periphs";
912 bias-pull-down;
913 drive-strength-microamp = <4000>;
914 };
915 };
916
917 sdio_pins: sdio {
918 mux {
919 groups = "sdio_d0",
920 "sdio_d1",
921 "sdio_d2",
922 "sdio_d3",
923 "sdio_clk",
924 "sdio_cmd";
925 function = "sdio";
926 bias-disable;
927 drive-strength-microamp = <4000>;
928 };
929 };
930
931 sdio_clk_gate_pins: sdio_clk_gate {
932 mux {
933 groups = "GPIOX_4";
934 function = "gpio_periphs";
935 bias-pull-down;
936 drive-strength-microamp = <4000>;
937 };
938 };
939
940 spdif_in_a10_pins: spdif-in-a10 {
941 mux {
942 groups = "spdif_in_a10";
943 function = "spdif_in";
944 bias-disable;
945 };
946 };
947
948 spdif_in_a12_pins: spdif-in-a12 {
949 mux {
950 groups = "spdif_in_a12";
951 function = "spdif_in";
952 bias-disable;
953 };
954 };
955
956 spdif_in_h_pins: spdif-in-h {
957 mux {
958 groups = "spdif_in_h";
959 function = "spdif_in";
960 bias-disable;
961 };
962 };
963
964 spdif_out_h_pins: spdif-out-h {
965 mux {
966 groups = "spdif_out_h";
967 function = "spdif_out";
968 drive-strength-microamp = <500>;
969 bias-disable;
970 };
971 };
972
973 spdif_out_a11_pins: spdif-out-a11 {
974 mux {
975 groups = "spdif_out_a11";
976 function = "spdif_out";
977 drive-strength-microamp = <500>;
978 bias-disable;
979 };
980 };
981
982 spdif_out_a13_pins: spdif-out-a13 {
983 mux {
984 groups = "spdif_out_a13";
985 function = "spdif_out";
986 drive-strength-microamp = <500>;
987 bias-disable;
988 };
989 };
990
991 spicc0_x_pins: spicc0-x {
992 mux {
993 groups = "spi0_mosi_x",
994 "spi0_miso_x",
995 "spi0_clk_x";
996 function = "spi0";
997 drive-strength-microamp = <4000>;
998 bias-disable;
999 };
1000 };
1001
1002 spicc0_ss0_x_pins: spicc0-ss0-x {
1003 mux {
1004 groups = "spi0_ss0_x";
1005 function = "spi0";
1006 drive-strength-microamp = <4000>;
1007 bias-disable;
1008 };
1009 };
1010
1011 spicc0_c_pins: spicc0-c {
1012 mux {
1013 groups = "spi0_mosi_c",
1014 "spi0_miso_c",
1015 "spi0_ss0_c",
1016 "spi0_clk_c";
1017 function = "spi0";
1018 drive-strength-microamp = <4000>;
1019 bias-disable;
1020 };
1021 };
1022
1023 spicc1_pins: spicc1 {
1024 mux {
1025 groups = "spi1_mosi",
1026 "spi1_miso",
1027 "spi1_clk";
1028 function = "spi1";
1029 drive-strength-microamp = <4000>;
1030 };
1031 };
1032
1033 spicc1_ss0_pins: spicc1-ss0 {
1034 mux {
1035 groups = "spi1_ss0";
1036 function = "spi1";
1037 drive-strength-microamp = <4000>;
1038 bias-disable;
1039 };
1040 };
1041
1042 tdm_a_din0_pins: tdm-a-din0 {
1043 mux {
1044 groups = "tdm_a_din0";
1045 function = "tdm_a";
1046 bias-disable;
1047 };
1048 };
1049
1050
1051 tdm_a_din1_pins: tdm-a-din1 {
1052 mux {
1053 groups = "tdm_a_din1";
1054 function = "tdm_a";
1055 bias-disable;
1056 };
1057 };
1058
1059 tdm_a_dout0_pins: tdm-a-dout0 {
1060 mux {
1061 groups = "tdm_a_dout0";
1062 function = "tdm_a";
1063 bias-disable;
1064 drive-strength-microamp = <3000>;
1065 };
1066 };
1067
1068 tdm_a_dout1_pins: tdm-a-dout1 {
1069 mux {
1070 groups = "tdm_a_dout1";
1071 function = "tdm_a";
1072 bias-disable;
1073 drive-strength-microamp = <3000>;
1074 };
1075 };
1076
1077 tdm_a_fs_pins: tdm-a-fs {
1078 mux {
1079 groups = "tdm_a_fs";
1080 function = "tdm_a";
1081 bias-disable;
1082 drive-strength-microamp = <3000>;
1083 };
1084 };
1085
1086 tdm_a_sclk_pins: tdm-a-sclk {
1087 mux {
1088 groups = "tdm_a_sclk";
1089 function = "tdm_a";
1090 bias-disable;
1091 drive-strength-microamp = <3000>;
1092 };
1093 };
1094
1095 tdm_a_slv_fs_pins: tdm-a-slv-fs {
1096 mux {
1097 groups = "tdm_a_slv_fs";
1098 function = "tdm_a";
1099 bias-disable;
1100 };
1101 };
1102
1103
1104 tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
1105 mux {
1106 groups = "tdm_a_slv_sclk";
1107 function = "tdm_a";
1108 bias-disable;
1109 };
1110 };
1111
1112 tdm_b_din0_pins: tdm-b-din0 {
1113 mux {
1114 groups = "tdm_b_din0";
1115 function = "tdm_b";
1116 bias-disable;
1117 };
1118 };
1119
1120 tdm_b_din1_pins: tdm-b-din1 {
1121 mux {
1122 groups = "tdm_b_din1";
1123 function = "tdm_b";
1124 bias-disable;
1125 };
1126 };
1127
1128 tdm_b_din2_pins: tdm-b-din2 {
1129 mux {
1130 groups = "tdm_b_din2";
1131 function = "tdm_b";
1132 bias-disable;
1133 };
1134 };
1135
1136 tdm_b_din3_a_pins: tdm-b-din3-a {
1137 mux {
1138 groups = "tdm_b_din3_a";
1139 function = "tdm_b";
1140 bias-disable;
1141 };
1142 };
1143
1144 tdm_b_din3_h_pins: tdm-b-din3-h {
1145 mux {
1146 groups = "tdm_b_din3_h";
1147 function = "tdm_b";
1148 bias-disable;
1149 };
1150 };
1151
1152 tdm_b_dout0_pins: tdm-b-dout0 {
1153 mux {
1154 groups = "tdm_b_dout0";
1155 function = "tdm_b";
1156 bias-disable;
1157 drive-strength-microamp = <3000>;
1158 };
1159 };
1160
1161 tdm_b_dout1_pins: tdm-b-dout1 {
1162 mux {
1163 groups = "tdm_b_dout1";
1164 function = "tdm_b";
1165 bias-disable;
1166 drive-strength-microamp = <3000>;
1167 };
1168 };
1169
1170 tdm_b_dout2_pins: tdm-b-dout2 {
1171 mux {
1172 groups = "tdm_b_dout2";
1173 function = "tdm_b";
1174 bias-disable;
1175 drive-strength-microamp = <3000>;
1176 };
1177 };
1178
1179 tdm_b_dout3_a_pins: tdm-b-dout3-a {
1180 mux {
1181 groups = "tdm_b_dout3_a";
1182 function = "tdm_b";
1183 bias-disable;
1184 drive-strength-microamp = <3000>;
1185 };
1186 };
1187
1188 tdm_b_dout3_h_pins: tdm-b-dout3-h {
1189 mux {
1190 groups = "tdm_b_dout3_h";
1191 function = "tdm_b";
1192 bias-disable;
1193 drive-strength-microamp = <3000>;
1194 };
1195 };
1196
1197 tdm_b_fs_pins: tdm-b-fs {
1198 mux {
1199 groups = "tdm_b_fs";
1200 function = "tdm_b";
1201 bias-disable;
1202 drive-strength-microamp = <3000>;
1203 };
1204 };
1205
1206 tdm_b_sclk_pins: tdm-b-sclk {
1207 mux {
1208 groups = "tdm_b_sclk";
1209 function = "tdm_b";
1210 bias-disable;
1211 drive-strength-microamp = <3000>;
1212 };
1213 };
1214
1215 tdm_b_slv_fs_pins: tdm-b-slv-fs {
1216 mux {
1217 groups = "tdm_b_slv_fs";
1218 function = "tdm_b";
1219 bias-disable;
1220 };
1221 };
1222
1223 tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
1224 mux {
1225 groups = "tdm_b_slv_sclk";
1226 function = "tdm_b";
1227 bias-disable;
1228 };
1229 };
1230
1231 tdm_c_din0_a_pins: tdm-c-din0-a {
1232 mux {
1233 groups = "tdm_c_din0_a";
1234 function = "tdm_c";
1235 bias-disable;
1236 };
1237 };
1238
1239 tdm_c_din0_z_pins: tdm-c-din0-z {
1240 mux {
1241 groups = "tdm_c_din0_z";
1242 function = "tdm_c";
1243 bias-disable;
1244 };
1245 };
1246
1247 tdm_c_din1_a_pins: tdm-c-din1-a {
1248 mux {
1249 groups = "tdm_c_din1_a";
1250 function = "tdm_c";
1251 bias-disable;
1252 };
1253 };
1254
1255 tdm_c_din1_z_pins: tdm-c-din1-z {
1256 mux {
1257 groups = "tdm_c_din1_z";
1258 function = "tdm_c";
1259 bias-disable;
1260 };
1261 };
1262
1263 tdm_c_din2_a_pins: tdm-c-din2-a {
1264 mux {
1265 groups = "tdm_c_din2_a";
1266 function = "tdm_c";
1267 bias-disable;
1268 };
1269 };
1270
1271 eth_leds_pins: eth-leds {
1272 mux {
1273 groups = "eth_link_led",
1274 "eth_act_led";
1275 function = "eth";
1276 bias-disable;
1277 };
1278 };
1279
1280 eth_pins: eth {
1281 mux {
1282 groups = "eth_mdio",
1283 "eth_mdc",
1284 "eth_rgmii_rx_clk",
1285 "eth_rx_dv",
1286 "eth_rxd0",
1287 "eth_rxd1",
1288 "eth_txen",
1289 "eth_txd0",
1290 "eth_txd1";
1291 function = "eth";
1292 drive-strength-microamp = <4000>;
1293 bias-disable;
1294 };
1295 };
1296
1297 eth_rgmii_pins: eth-rgmii {
1298 mux {
1299 groups = "eth_rxd2_rgmii",
1300 "eth_rxd3_rgmii",
1301 "eth_rgmii_tx_clk",
1302 "eth_txd2_rgmii",
1303 "eth_txd3_rgmii";
1304 function = "eth";
1305 drive-strength-microamp = <4000>;
1306 bias-disable;
1307 };
1308 };
1309
1310 tdm_c_din2_z_pins: tdm-c-din2-z {
1311 mux {
1312 groups = "tdm_c_din2_z";
1313 function = "tdm_c";
1314 bias-disable;
1315 };
1316 };
1317
1318 tdm_c_din3_a_pins: tdm-c-din3-a {
1319 mux {
1320 groups = "tdm_c_din3_a";
1321 function = "tdm_c";
1322 bias-disable;
1323 };
1324 };
1325
1326 tdm_c_din3_z_pins: tdm-c-din3-z {
1327 mux {
1328 groups = "tdm_c_din3_z";
1329 function = "tdm_c";
1330 bias-disable;
1331 };
1332 };
1333
1334 tdm_c_dout0_a_pins: tdm-c-dout0-a {
1335 mux {
1336 groups = "tdm_c_dout0_a";
1337 function = "tdm_c";
1338 bias-disable;
1339 drive-strength-microamp = <3000>;
1340 };
1341 };
1342
1343 tdm_c_dout0_z_pins: tdm-c-dout0-z {
1344 mux {
1345 groups = "tdm_c_dout0_z";
1346 function = "tdm_c";
1347 bias-disable;
1348 drive-strength-microamp = <3000>;
1349 };
1350 };
1351
1352 tdm_c_dout1_a_pins: tdm-c-dout1-a {
1353 mux {
1354 groups = "tdm_c_dout1_a";
1355 function = "tdm_c";
1356 bias-disable;
1357 drive-strength-microamp = <3000>;
1358 };
1359 };
1360
1361 tdm_c_dout1_z_pins: tdm-c-dout1-z {
1362 mux {
1363 groups = "tdm_c_dout1_z";
1364 function = "tdm_c";
1365 bias-disable;
1366 drive-strength-microamp = <3000>;
1367 };
1368 };
1369
1370 tdm_c_dout2_a_pins: tdm-c-dout2-a {
1371 mux {
1372 groups = "tdm_c_dout2_a";
1373 function = "tdm_c";
1374 bias-disable;
1375 drive-strength-microamp = <3000>;
1376 };
1377 };
1378
1379 tdm_c_dout2_z_pins: tdm-c-dout2-z {
1380 mux {
1381 groups = "tdm_c_dout2_z";
1382 function = "tdm_c";
1383 bias-disable;
1384 drive-strength-microamp = <3000>;
1385 };
1386 };
1387
1388 tdm_c_dout3_a_pins: tdm-c-dout3-a {
1389 mux {
1390 groups = "tdm_c_dout3_a";
1391 function = "tdm_c";
1392 bias-disable;
1393 drive-strength-microamp = <3000>;
1394 };
1395 };
1396
1397 tdm_c_dout3_z_pins: tdm-c-dout3-z {
1398 mux {
1399 groups = "tdm_c_dout3_z";
1400 function = "tdm_c";
1401 bias-disable;
1402 drive-strength-microamp = <3000>;
1403 };
1404 };
1405
1406 tdm_c_fs_a_pins: tdm-c-fs-a {
1407 mux {
1408 groups = "tdm_c_fs_a";
1409 function = "tdm_c";
1410 bias-disable;
1411 drive-strength-microamp = <3000>;
1412 };
1413 };
1414
1415 tdm_c_fs_z_pins: tdm-c-fs-z {
1416 mux {
1417 groups = "tdm_c_fs_z";
1418 function = "tdm_c";
1419 bias-disable;
1420 drive-strength-microamp = <3000>;
1421 };
1422 };
1423
1424 tdm_c_sclk_a_pins: tdm-c-sclk-a {
1425 mux {
1426 groups = "tdm_c_sclk_a";
1427 function = "tdm_c";
1428 bias-disable;
1429 drive-strength-microamp = <3000>;
1430 };
1431 };
1432
1433 tdm_c_sclk_z_pins: tdm-c-sclk-z {
1434 mux {
1435 groups = "tdm_c_sclk_z";
1436 function = "tdm_c";
1437 bias-disable;
1438 drive-strength-microamp = <3000>;
1439 };
1440 };
1441
1442 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
1443 mux {
1444 groups = "tdm_c_slv_fs_a";
1445 function = "tdm_c";
1446 bias-disable;
1447 };
1448 };
1449
1450 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
1451 mux {
1452 groups = "tdm_c_slv_fs_z";
1453 function = "tdm_c";
1454 bias-disable;
1455 };
1456 };
1457
1458 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
1459 mux {
1460 groups = "tdm_c_slv_sclk_a";
1461 function = "tdm_c";
1462 bias-disable;
1463 };
1464 };
1465
1466 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
1467 mux {
1468 groups = "tdm_c_slv_sclk_z";
1469 function = "tdm_c";
1470 bias-disable;
1471 };
1472 };
1473
1474 uart_a_pins: uart-a {
1475 mux {
1476 groups = "uart_a_tx",
1477 "uart_a_rx";
1478 function = "uart_a";
1479 bias-disable;
1480 };
1481 };
1482
1483 uart_a_cts_rts_pins: uart-a-cts-rts {
1484 mux {
1485 groups = "uart_a_cts",
1486 "uart_a_rts";
1487 function = "uart_a";
1488 bias-disable;
1489 };
1490 };
1491
1492 uart_b_pins: uart-b {
1493 mux {
1494 groups = "uart_b_tx",
1495 "uart_b_rx";
1496 function = "uart_b";
1497 bias-disable;
1498 };
1499 };
1500
1501 uart_c_pins: uart-c {
1502 mux {
1503 groups = "uart_c_tx",
1504 "uart_c_rx";
1505 function = "uart_c";
1506 bias-disable;
1507 };
1508 };
1509
1510 uart_c_cts_rts_pins: uart-c-cts-rts {
1511 mux {
1512 groups = "uart_c_cts",
1513 "uart_c_rts";
1514 function = "uart_c";
1515 bias-disable;
1516 };
1517 };
1518 };
1519 };
1520
1521 cpu_temp: temperature-sensor@34800 {
1522 compatible = "amlogic,g12a-cpu-thermal",
1523 "amlogic,g12a-thermal";
1524 reg = <0x0 0x34800 0x0 0x50>;
1525 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
1526 clocks = <&clkc CLKID_TS>;
1527 #thermal-sensor-cells = <0>;
1528 amlogic,ao-secure = <&sec_AO>;
1529 };
1530
1531 ddr_temp: temperature-sensor@34c00 {
1532 compatible = "amlogic,g12a-ddr-thermal",
1533 "amlogic,g12a-thermal";
1534 reg = <0x0 0x34c00 0x0 0x50>;
1535 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
1536 clocks = <&clkc CLKID_TS>;
1537 #thermal-sensor-cells = <0>;
1538 amlogic,ao-secure = <&sec_AO>;
1539 };
1540
1541 usb2_phy0: phy@36000 {
1542 compatible = "amlogic,g12a-usb2-phy";
1543 reg = <0x0 0x36000 0x0 0x2000>;
1544 clocks = <&xtal>;
1545 clock-names = "xtal";
1546 resets = <&reset RESET_USB_PHY20>;
1547 reset-names = "phy";
1548 #phy-cells = <0>;
1549 };
1550
1551 dmc: bus@38000 {
1552 compatible = "simple-bus";
1553 reg = <0x0 0x38000 0x0 0x400>;
1554 #address-cells = <2>;
1555 #size-cells = <2>;
1556 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
1557
1558 canvas: video-lut@48 {
1559 compatible = "amlogic,canvas";
1560 reg = <0x0 0x48 0x0 0x14>;
1561 };
1562 };
1563
1564 usb2_phy1: phy@3a000 {
1565 compatible = "amlogic,g12a-usb2-phy";
1566 reg = <0x0 0x3a000 0x0 0x2000>;
1567 clocks = <&xtal>;
1568 clock-names = "xtal";
1569 resets = <&reset RESET_USB_PHY21>;
1570 reset-names = "phy";
1571 #phy-cells = <0>;
1572 };
1573
1574 hiu: bus@3c000 {
1575 compatible = "simple-bus";
1576 reg = <0x0 0x3c000 0x0 0x1400>;
1577 #address-cells = <2>;
1578 #size-cells = <2>;
1579 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
1580
1581 hhi: system-controller@0 {
1582 compatible = "amlogic,meson-gx-hhi-sysctrl",
1583 "simple-mfd", "syscon";
1584 reg = <0 0 0 0x400>;
1585
1586 clkc: clock-controller {
1587 compatible = "amlogic,g12a-clkc";
1588 #clock-cells = <1>;
1589 clocks = <&xtal>;
1590 clock-names = "xtal";
1591 };
1592
1593 pwrc: power-controller {
1594 compatible = "amlogic,meson-g12a-pwrc";
1595 #power-domain-cells = <1>;
1596 amlogic,ao-sysctrl = <&rti>;
1597 resets = <&reset RESET_VIU>,
1598 <&reset RESET_VENC>,
1599 <&reset RESET_VCBUS>,
1600 <&reset RESET_BT656>,
1601 <&reset RESET_RDMA>,
1602 <&reset RESET_VENCI>,
1603 <&reset RESET_VENCP>,
1604 <&reset RESET_VDAC>,
1605 <&reset RESET_VDI6>,
1606 <&reset RESET_VENCL>,
1607 <&reset RESET_VID_LOCK>;
1608 reset-names = "viu", "venc", "vcbus", "bt656",
1609 "rdma", "venci", "vencp", "vdac",
1610 "vdi6", "vencl", "vid_lock";
1611 clocks = <&clkc CLKID_VPU>,
1612 <&clkc CLKID_VAPB>;
1613 clock-names = "vpu", "vapb";
1614 /*
1615 * VPU clocking is provided by two identical clock paths
1616 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1617 * free mux to safely change frequency while running.
1618 * Same for VAPB but with a final gate after the glitch free mux.
1619 */
1620 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1621 <&clkc CLKID_VPU_0>,
1622 <&clkc CLKID_VPU>, /* Glitch free mux */
1623 <&clkc CLKID_VAPB_0_SEL>,
1624 <&clkc CLKID_VAPB_0>,
1625 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1626 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1627 <0>, /* Do Nothing */
1628 <&clkc CLKID_VPU_0>,
1629 <&clkc CLKID_FCLK_DIV4>,
1630 <0>, /* Do Nothing */
1631 <&clkc CLKID_VAPB_0>;
1632 assigned-clock-rates = <0>, /* Do Nothing */
1633 <666666666>,
1634 <0>, /* Do Nothing */
1635 <0>, /* Do Nothing */
1636 <250000000>,
1637 <0>; /* Do Nothing */
1638 };
1639 };
1640 };
1641
1642 usb3_pcie_phy: phy@46000 {
1643 compatible = "amlogic,g12a-usb3-pcie-phy";
1644 reg = <0x0 0x46000 0x0 0x2000>;
1645 clocks = <&clkc CLKID_PCIE_PLL>;
1646 clock-names = "ref_clk";
1647 resets = <&reset RESET_PCIE_PHY>;
1648 reset-names = "phy";
1649 assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1650 assigned-clock-rates = <100000000>;
1651 #phy-cells = <1>;
1652 };
1653
1654 eth_phy: mdio-multiplexer@4c000 {
1655 compatible = "amlogic,g12a-mdio-mux";
1656 reg = <0x0 0x4c000 0x0 0xa4>;
1657 clocks = <&clkc CLKID_ETH_PHY>,
1658 <&xtal>,
1659 <&clkc CLKID_MPLL_50M>;
1660 clock-names = "pclk", "clkin0", "clkin1";
1661 mdio-parent-bus = <&mdio0>;
1662 #address-cells = <1>;
1663 #size-cells = <0>;
1664
1665 ext_mdio: mdio@0 {
1666 reg = <0>;
1667 #address-cells = <1>;
1668 #size-cells = <0>;
1669 };
1670
1671 int_mdio: mdio@1 {
1672 reg = <1>;
1673 #address-cells = <1>;
1674 #size-cells = <0>;
1675
1676 internal_ephy: ethernet_phy@8 {
1677 compatible = "ethernet-phy-id0180.3301",
1678 "ethernet-phy-ieee802.3-c22";
1679 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1680 reg = <8>;
1681 max-speed = <100>;
1682 };
1683 };
1684 };
1685 };
1686
1687 aobus: bus@ff800000 {
1688 compatible = "simple-bus";
1689 reg = <0x0 0xff800000 0x0 0x100000>;
1690 #address-cells = <2>;
1691 #size-cells = <2>;
1692 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1693
1694 rti: sys-ctrl@0 {
1695 compatible = "amlogic,meson-gx-ao-sysctrl",
1696 "simple-mfd", "syscon";
1697 reg = <0x0 0x0 0x0 0x100>;
1698 #address-cells = <2>;
1699 #size-cells = <2>;
1700 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
1701
1702 clkc_AO: clock-controller {
1703 compatible = "amlogic,meson-g12a-aoclkc";
1704 #clock-cells = <1>;
1705 #reset-cells = <1>;
1706 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1707 clock-names = "xtal", "mpeg-clk";
1708 };
1709
1710 ao_pinctrl: pinctrl@14 {
1711 compatible = "amlogic,meson-g12a-aobus-pinctrl";
1712 #address-cells = <2>;
1713 #size-cells = <2>;
1714 ranges;
1715
1716 gpio_ao: bank@14 {
1717 reg = <0x0 0x14 0x0 0x8>,
1718 <0x0 0x1c 0x0 0x8>,
1719 <0x0 0x24 0x0 0x14>;
1720 reg-names = "mux",
1721 "ds",
1722 "gpio";
1723 gpio-controller;
1724 #gpio-cells = <2>;
1725 gpio-ranges = <&ao_pinctrl 0 0 15>;
1726 };
1727
1728 i2c_ao_sck_pins: i2c_ao_sck_pins {
1729 mux {
1730 groups = "i2c_ao_sck";
1731 function = "i2c_ao";
1732 bias-disable;
1733 drive-strength-microamp = <3000>;
1734 };
1735 };
1736
1737 i2c_ao_sda_pins: i2c_ao_sda {
1738 mux {
1739 groups = "i2c_ao_sda";
1740 function = "i2c_ao";
1741 bias-disable;
1742 drive-strength-microamp = <3000>;
1743 };
1744 };
1745
1746 i2c_ao_sck_e_pins: i2c_ao_sck_e {
1747 mux {
1748 groups = "i2c_ao_sck_e";
1749 function = "i2c_ao";
1750 bias-disable;
1751 drive-strength-microamp = <3000>;
1752 };
1753 };
1754
1755 i2c_ao_sda_e_pins: i2c_ao_sda_e {
1756 mux {
1757 groups = "i2c_ao_sda_e";
1758 function = "i2c_ao";
1759 bias-disable;
1760 drive-strength-microamp = <3000>;
1761 };
1762 };
1763
1764 mclk0_ao_pins: mclk0-ao {
1765 mux {
1766 groups = "mclk0_ao";
1767 function = "mclk0_ao";
1768 bias-disable;
1769 drive-strength-microamp = <3000>;
1770 };
1771 };
1772
1773 tdm_ao_b_din0_pins: tdm-ao-b-din0 {
1774 mux {
1775 groups = "tdm_ao_b_din0";
1776 function = "tdm_ao_b";
1777 bias-disable;
1778 };
1779 };
1780
1781 spdif_ao_out_pins: spdif-ao-out {
1782 mux {
1783 groups = "spdif_ao_out";
1784 function = "spdif_ao_out";
1785 drive-strength-microamp = <500>;
1786 bias-disable;
1787 };
1788 };
1789
1790 tdm_ao_b_din1_pins: tdm-ao-b-din1 {
1791 mux {
1792 groups = "tdm_ao_b_din1";
1793 function = "tdm_ao_b";
1794 bias-disable;
1795 };
1796 };
1797
1798 tdm_ao_b_din2_pins: tdm-ao-b-din2 {
1799 mux {
1800 groups = "tdm_ao_b_din2";
1801 function = "tdm_ao_b";
1802 bias-disable;
1803 };
1804 };
1805
1806 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
1807 mux {
1808 groups = "tdm_ao_b_dout0";
1809 function = "tdm_ao_b";
1810 bias-disable;
1811 drive-strength-microamp = <3000>;
1812 };
1813 };
1814
1815 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
1816 mux {
1817 groups = "tdm_ao_b_dout1";
1818 function = "tdm_ao_b";
1819 bias-disable;
1820 drive-strength-microamp = <3000>;
1821 };
1822 };
1823
1824 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
1825 mux {
1826 groups = "tdm_ao_b_dout2";
1827 function = "tdm_ao_b";
1828 bias-disable;
1829 drive-strength-microamp = <3000>;
1830 };
1831 };
1832
1833 tdm_ao_b_fs_pins: tdm-ao-b-fs {
1834 mux {
1835 groups = "tdm_ao_b_fs";
1836 function = "tdm_ao_b";
1837 bias-disable;
1838 drive-strength-microamp = <3000>;
1839 };
1840 };
1841
1842 tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
1843 mux {
1844 groups = "tdm_ao_b_sclk";
1845 function = "tdm_ao_b";
1846 bias-disable;
1847 drive-strength-microamp = <3000>;
1848 };
1849 };
1850
1851 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
1852 mux {
1853 groups = "tdm_ao_b_slv_fs";
1854 function = "tdm_ao_b";
1855 bias-disable;
1856 };
1857 };
1858
1859 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
1860 mux {
1861 groups = "tdm_ao_b_slv_sclk";
1862 function = "tdm_ao_b";
1863 bias-disable;
1864 };
1865 };
1866
1867 uart_ao_a_pins: uart-a-ao {
1868 mux {
1869 groups = "uart_ao_a_tx",
1870 "uart_ao_a_rx";
1871 function = "uart_ao_a";
1872 bias-disable;
1873 };
1874 };
1875
1876 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
1877 mux {
1878 groups = "uart_ao_a_cts",
1879 "uart_ao_a_rts";
1880 function = "uart_ao_a";
1881 bias-disable;
1882 };
1883 };
1884
1885 pwm_a_e_pins: pwm-a-e {
1886 mux {
1887 groups = "pwm_a_e";
1888 function = "pwm_a_e";
1889 bias-disable;
1890 };
1891 };
1892
1893 pwm_ao_a_pins: pwm-ao-a {
1894 mux {
1895 groups = "pwm_ao_a";
1896 function = "pwm_ao_a";
1897 bias-disable;
1898 };
1899 };
1900
1901 pwm_ao_b_pins: pwm-ao-b {
1902 mux {
1903 groups = "pwm_ao_b";
1904 function = "pwm_ao_b";
1905 bias-disable;
1906 };
1907 };
1908
1909 pwm_ao_c_4_pins: pwm-ao-c-4 {
1910 mux {
1911 groups = "pwm_ao_c_4";
1912 function = "pwm_ao_c";
1913 bias-disable;
1914 };
1915 };
1916
1917 pwm_ao_c_6_pins: pwm-ao-c-6 {
1918 mux {
1919 groups = "pwm_ao_c_6";
1920 function = "pwm_ao_c";
1921 bias-disable;
1922 };
1923 };
1924
1925 pwm_ao_d_5_pins: pwm-ao-d-5 {
1926 mux {
1927 groups = "pwm_ao_d_5";
1928 function = "pwm_ao_d";
1929 bias-disable;
1930 };
1931 };
1932
1933 pwm_ao_d_10_pins: pwm-ao-d-10 {
1934 mux {
1935 groups = "pwm_ao_d_10";
1936 function = "pwm_ao_d";
1937 bias-disable;
1938 };
1939 };
1940
1941 pwm_ao_d_e_pins: pwm-ao-d-e {
1942 mux {
1943 groups = "pwm_ao_d_e";
1944 function = "pwm_ao_d";
1945 };
1946 };
1947
1948 remote_input_ao_pins: remote-input-ao {
1949 mux {
1950 groups = "remote_ao_input";
1951 function = "remote_ao_input";
1952 bias-disable;
1953 };
1954 };
1955 };
1956 };
1957
1958 vrtc: rtc@0a8 {
1959 compatible = "amlogic,meson-vrtc";
1960 reg = <0x0 0x000a8 0x0 0x4>;
1961 };
1962
1963 cec_AO: cec@100 {
1964 compatible = "amlogic,meson-gx-ao-cec";
1965 reg = <0x0 0x00100 0x0 0x14>;
1966 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
1967 clocks = <&clkc_AO CLKID_AO_CEC>;
1968 clock-names = "core";
1969 status = "disabled";
1970 };
1971
1972 sec_AO: ao-secure@140 {
1973 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1974 reg = <0x0 0x140 0x0 0x140>;
1975 amlogic,has-chip-id;
1976 };
1977
1978 cecb_AO: cec@280 {
1979 compatible = "amlogic,meson-g12a-ao-cec";
1980 reg = <0x0 0x00280 0x0 0x1c>;
1981 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
1982 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
1983 clock-names = "oscin";
1984 status = "disabled";
1985 };
1986
1987 pwm_AO_cd: pwm@2000 {
1988 compatible = "amlogic,meson-g12a-ao-pwm-cd";
1989 reg = <0x0 0x2000 0x0 0x20>;
1990 #pwm-cells = <3>;
1991 status = "disabled";
1992 };
1993
1994 uart_AO: serial@3000 {
1995 compatible = "amlogic,meson-gx-uart",
1996 "amlogic,meson-ao-uart";
1997 reg = <0x0 0x3000 0x0 0x18>;
1998 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1999 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
2000 clock-names = "xtal", "pclk", "baud";
2001 status = "disabled";
2002 };
2003
2004 uart_AO_B: serial@4000 {
2005 compatible = "amlogic,meson-gx-uart",
2006 "amlogic,meson-ao-uart";
2007 reg = <0x0 0x4000 0x0 0x18>;
2008 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
2009 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
2010 clock-names = "xtal", "pclk", "baud";
2011 status = "disabled";
2012 };
2013
2014 i2c_AO: i2c@5000 {
2015 compatible = "amlogic,meson-axg-i2c";
2016 status = "disabled";
2017 reg = <0x0 0x05000 0x0 0x20>;
2018 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
2019 #address-cells = <1>;
2020 #size-cells = <0>;
2021 clocks = <&clkc CLKID_I2C>;
2022 };
2023
2024 pwm_AO_ab: pwm@7000 {
2025 compatible = "amlogic,meson-g12a-ao-pwm-ab";
2026 reg = <0x0 0x7000 0x0 0x20>;
2027 #pwm-cells = <3>;
2028 status = "disabled";
2029 };
2030
2031 ir: ir@8000 {
2032 compatible = "amlogic,meson-gxbb-ir";
2033 reg = <0x0 0x8000 0x0 0x20>;
2034 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
2035 status = "disabled";
2036 };
2037
2038 saradc: adc@9000 {
2039 compatible = "amlogic,meson-g12a-saradc",
2040 "amlogic,meson-saradc";
2041 reg = <0x0 0x9000 0x0 0x48>;
2042 #io-channel-cells = <1>;
2043 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
2044 clocks = <&xtal>,
2045 <&clkc_AO CLKID_AO_SAR_ADC>,
2046 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
2047 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
2048 clock-names = "clkin", "core", "adc_clk", "adc_sel";
2049 status = "disabled";
2050 };
2051 };
2052
2053 vdec: video-decoder@ff620000 {
2054 compatible = "amlogic,g12a-vdec";
2055 reg = <0x0 0xff620000 0x0 0x10000>,
2056 <0x0 0xffd0e180 0x0 0xe4>;
2057 reg-names = "dos", "esparser";
2058 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
2059 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
2060 interrupt-names = "vdec", "esparser";
2061
2062 amlogic,ao-sysctrl = <&rti>;
2063 amlogic,canvas = <&canvas>;
2064
2065 clocks = <&clkc CLKID_PARSER>,
2066 <&clkc CLKID_DOS>,
2067 <&clkc CLKID_VDEC_1>,
2068 <&clkc CLKID_VDEC_HEVC>,
2069 <&clkc CLKID_VDEC_HEVCF>;
2070 clock-names = "dos_parser", "dos", "vdec_1",
2071 "vdec_hevc", "vdec_hevcf";
2072 resets = <&reset RESET_PARSER>;
2073 reset-names = "esparser";
2074 };
2075
2076 vpu: vpu@ff900000 {
2077 compatible = "amlogic,meson-g12a-vpu";
2078 reg = <0x0 0xff900000 0x0 0x100000>,
2079 <0x0 0xff63c000 0x0 0x1000>;
2080 reg-names = "vpu", "hhi";
2081 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2082 #address-cells = <1>;
2083 #size-cells = <0>;
2084 amlogic,canvas = <&canvas>;
2085
2086 /* CVBS VDAC output port */
2087 cvbs_vdac_port: port@0 {
2088 reg = <0>;
2089 };
2090
2091 /* HDMI-TX output port */
2092 hdmi_tx_port: port@1 {
2093 reg = <1>;
2094
2095 hdmi_tx_out: endpoint {
2096 remote-endpoint = <&hdmi_tx_in>;
2097 };
2098 };
2099 };
2100
2101 gic: interrupt-controller@ffc01000 {
2102 compatible = "arm,gic-400";
2103 reg = <0x0 0xffc01000 0 0x1000>,
2104 <0x0 0xffc02000 0 0x2000>,
2105 <0x0 0xffc04000 0 0x2000>,
2106 <0x0 0xffc06000 0 0x2000>;
2107 interrupt-controller;
2108 interrupts = <GIC_PPI 9
2109 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2110 #interrupt-cells = <3>;
2111 #address-cells = <0>;
2112 };
2113
2114 cbus: bus@ffd00000 {
2115 compatible = "simple-bus";
2116 reg = <0x0 0xffd00000 0x0 0x100000>;
2117 #address-cells = <2>;
2118 #size-cells = <2>;
2119 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
2120
2121 reset: reset-controller@1004 {
2122 compatible = "amlogic,meson-axg-reset";
2123 reg = <0x0 0x1004 0x0 0x9c>;
2124 #reset-cells = <1>;
2125 };
2126
2127 gpio_intc: interrupt-controller@f080 {
2128 compatible = "amlogic,meson-g12a-gpio-intc",
2129 "amlogic,meson-gpio-intc";
2130 reg = <0x0 0xf080 0x0 0x10>;
2131 interrupt-controller;
2132 #interrupt-cells = <2>;
2133 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
2134 };
2135
2136 spicc0: spi@13000 {
2137 compatible = "amlogic,meson-g12a-spicc";
2138 reg = <0x0 0x13000 0x0 0x44>;
2139 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2140 clocks = <&clkc CLKID_SPICC0>,
2141 <&clkc CLKID_SPICC0_SCLK>;
2142 clock-names = "core", "pclk";
2143 #address-cells = <1>;
2144 #size-cells = <0>;
2145 status = "disabled";
2146 };
2147
2148 spicc1: spi@15000 {
2149 compatible = "amlogic,meson-g12a-spicc";
2150 reg = <0x0 0x15000 0x0 0x44>;
2151 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
2152 clocks = <&clkc CLKID_SPICC1>,
2153 <&clkc CLKID_SPICC1_SCLK>;
2154 clock-names = "core", "pclk";
2155 #address-cells = <1>;
2156 #size-cells = <0>;
2157 status = "disabled";
2158 };
2159
2160 spifc: spi@14000 {
2161 compatible = "amlogic,meson-gxbb-spifc";
2162 status = "disabled";
2163 reg = <0x0 0x14000 0x0 0x80>;
2164 #address-cells = <1>;
2165 #size-cells = <0>;
2166 clocks = <&clkc CLKID_CLK81>;
2167 };
2168
2169 pwm_ef: pwm@19000 {
2170 compatible = "amlogic,meson-g12a-ee-pwm";
2171 reg = <0x0 0x19000 0x0 0x20>;
2172 #pwm-cells = <3>;
2173 status = "disabled";
2174 };
2175
2176 pwm_cd: pwm@1a000 {
2177 compatible = "amlogic,meson-g12a-ee-pwm";
2178 reg = <0x0 0x1a000 0x0 0x20>;
2179 #pwm-cells = <3>;
2180 status = "disabled";
2181 };
2182
2183 pwm_ab: pwm@1b000 {
2184 compatible = "amlogic,meson-g12a-ee-pwm";
2185 reg = <0x0 0x1b000 0x0 0x20>;
2186 #pwm-cells = <3>;
2187 status = "disabled";
2188 };
2189
2190 i2c3: i2c@1c000 {
2191 compatible = "amlogic,meson-axg-i2c";
2192 status = "disabled";
2193 reg = <0x0 0x1c000 0x0 0x20>;
2194 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
2195 #address-cells = <1>;
2196 #size-cells = <0>;
2197 clocks = <&clkc CLKID_I2C>;
2198 };
2199
2200 i2c2: i2c@1d000 {
2201 compatible = "amlogic,meson-axg-i2c";
2202 status = "disabled";
2203 reg = <0x0 0x1d000 0x0 0x20>;
2204 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
2205 #address-cells = <1>;
2206 #size-cells = <0>;
2207 clocks = <&clkc CLKID_I2C>;
2208 };
2209
2210 i2c1: i2c@1e000 {
2211 compatible = "amlogic,meson-axg-i2c";
2212 status = "disabled";
2213 reg = <0x0 0x1e000 0x0 0x20>;
2214 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
2215 #address-cells = <1>;
2216 #size-cells = <0>;
2217 clocks = <&clkc CLKID_I2C>;
2218 };
2219
2220 i2c0: i2c@1f000 {
2221 compatible = "amlogic,meson-axg-i2c";
2222 status = "disabled";
2223 reg = <0x0 0x1f000 0x0 0x20>;
2224 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
2225 #address-cells = <1>;
2226 #size-cells = <0>;
2227 clocks = <&clkc CLKID_I2C>;
2228 };
2229
2230 clk_msr: clock-measure@18000 {
2231 compatible = "amlogic,meson-g12a-clk-measure";
2232 reg = <0x0 0x18000 0x0 0x10>;
2233 };
2234
2235 uart_C: serial@22000 {
2236 compatible = "amlogic,meson-gx-uart";
2237 reg = <0x0 0x22000 0x0 0x18>;
2238 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
2239 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
2240 clock-names = "xtal", "pclk", "baud";
2241 status = "disabled";
2242 };
2243
2244 uart_B: serial@23000 {
2245 compatible = "amlogic,meson-gx-uart";
2246 reg = <0x0 0x23000 0x0 0x18>;
2247 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
2248 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
2249 clock-names = "xtal", "pclk", "baud";
2250 status = "disabled";
2251 };
2252
2253 uart_A: serial@24000 {
2254 compatible = "amlogic,meson-gx-uart";
2255 reg = <0x0 0x24000 0x0 0x18>;
2256 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
2257 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
2258 clock-names = "xtal", "pclk", "baud";
2259 status = "disabled";
2260 };
2261 };
2262
2263 sd_emmc_a: sd@ffe03000 {
2264 compatible = "amlogic,meson-axg-mmc";
2265 reg = <0x0 0xffe03000 0x0 0x800>;
2266 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
2267 status = "disabled";
2268 clocks = <&clkc CLKID_SD_EMMC_A>,
2269 <&clkc CLKID_SD_EMMC_A_CLK0>,
2270 <&clkc CLKID_FCLK_DIV2>;
2271 clock-names = "core", "clkin0", "clkin1";
2272 resets = <&reset RESET_SD_EMMC_A>;
2273 };
2274
2275 sd_emmc_b: sd@ffe05000 {
2276 compatible = "amlogic,meson-axg-mmc";
2277 reg = <0x0 0xffe05000 0x0 0x800>;
2278 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
2279 status = "disabled";
2280 clocks = <&clkc CLKID_SD_EMMC_B>,
2281 <&clkc CLKID_SD_EMMC_B_CLK0>,
2282 <&clkc CLKID_FCLK_DIV2>;
2283 clock-names = "core", "clkin0", "clkin1";
2284 resets = <&reset RESET_SD_EMMC_B>;
2285 };
2286
2287 sd_emmc_c: mmc@ffe07000 {
2288 compatible = "amlogic,meson-axg-mmc";
2289 reg = <0x0 0xffe07000 0x0 0x800>;
2290 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
2291 status = "disabled";
2292 clocks = <&clkc CLKID_SD_EMMC_C>,
2293 <&clkc CLKID_SD_EMMC_C_CLK0>,
2294 <&clkc CLKID_FCLK_DIV2>;
2295 clock-names = "core", "clkin0", "clkin1";
2296 resets = <&reset RESET_SD_EMMC_C>;
2297 };
2298
2299 usb: usb@ffe09000 {
2300 status = "disabled";
2301 compatible = "amlogic,meson-g12a-usb-ctrl";
2302 reg = <0x0 0xffe09000 0x0 0xa0>;
2303 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2304 #address-cells = <2>;
2305 #size-cells = <2>;
2306 ranges;
2307
2308 clocks = <&clkc CLKID_USB>;
2309 resets = <&reset RESET_USB>;
2310
2311 dr_mode = "otg";
2312
2313 phys = <&usb2_phy0>, <&usb2_phy1>,
2314 <&usb3_pcie_phy PHY_TYPE_USB3>;
2315 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
2316
2317 dwc2: usb@ff400000 {
2318 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
2319 reg = <0x0 0xff400000 0x0 0x40000>;
2320 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2321 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2322 clock-names = "otg";
2323 phys = <&usb2_phy1>;
2324 phy-names = "usb2-phy";
2325 dr_mode = "peripheral";
2326 g-rx-fifo-size = <192>;
2327 g-np-tx-fifo-size = <128>;
2328 g-tx-fifo-size = <128 128 16 16 16>;
2329 };
2330
2331 dwc3: usb@ff500000 {
2332 compatible = "snps,dwc3";
2333 reg = <0x0 0xff500000 0x0 0x100000>;
2334 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2335 dr_mode = "host";
2336 snps,dis_u2_susphy_quirk;
2337 snps,quirk-frame-length-adjustment;
2338 snps,parkmode-disable-ss-quirk;
2339 };
2340 };
2341
2342 mali: gpu@ffe40000 {
2343 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
2344 reg = <0x0 0xffe40000 0x0 0x40000>;
2345 interrupt-parent = <&gic>;
2346 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2347 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2348 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2349 interrupt-names = "job", "mmu", "gpu";
2350 clocks = <&clkc CLKID_MALI>;
2351 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
2352
2353 /*
2354 * Mali clocking is provided by two identical clock paths
2355 * MALI_0 and MALI_1 muxed to a single clock by a glitch
2356 * free mux to safely change frequency while running.
2357 */
2358 assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
2359 <&clkc CLKID_MALI_0>,
2360 <&clkc CLKID_MALI>; /* Glitch free mux */
2361 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
2362 <0>, /* Do Nothing */
2363 <&clkc CLKID_MALI_0>;
2364 assigned-clock-rates = <0>, /* Do Nothing */
2365 <800000000>,
2366 <0>; /* Do Nothing */
2367 #cooling-cells = <2>;
2368 };
2369 };
2370
2371 timer {
2372 compatible = "arm,armv8-timer";
2373 interrupts = <GIC_PPI 13
2374 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2375 <GIC_PPI 14
2376 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2377 <GIC_PPI 11
2378 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2379 <GIC_PPI 10
2380 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
2381 arm,no-tick-in-suspend;
2382 };
2383
2384 xtal: xtal-clk {
2385 compatible = "fixed-clock";
2386 clock-frequency = <24000000>;
2387 clock-output-names = "xtal";
2388 #clock-cells = <0>;
2389 };
2390
2391 };
A mirror of Linus' kernel repository