arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2019 BayLibre, SAS
   4  * Author: Neil Armstrong <narmstrong@baylibre.com>
   5  * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
   6  */
   7
   8 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
   9
  10 / {
  11         model = "Khadas VIM3";
  12
  13         vddcpu_a: regulator-vddcpu-a {
  14                 /*
  15                  * MP8756GD Regulator.
  16                  */
  17                 compatible = "pwm-regulator";
  18
  19                 regulator-name = "VDDCPU_A";
  20                 regulator-min-microvolt = <690000>;
  21                 regulator-max-microvolt = <1050000>;
  22
  23                 vin-supply = <&dc_in>;
  24
  25                 pwms = <&pwm_ab 0 1250 0>;
  26                 pwm-dutycycle-range = <100 0>;
  27
  28                 regulator-boot-on;
  29                 regulator-always-on;
  30         };
  31
  32         vddcpu_b: regulator-vddcpu-b {
  33                 /*
  34                  * Silergy SY8030DEC Regulator.
  35                  */
  36                 compatible = "pwm-regulator";
  37
  38                 regulator-name = "VDDCPU_B";
  39                 regulator-min-microvolt = <690000>;
  40                 regulator-max-microvolt = <1050000>;
  41
  42                 vin-supply = <&vsys_3v3>;
  43
  44                 pwms = <&pwm_AO_cd 1 1250 0>;
  45                 pwm-dutycycle-range = <100 0>;
  46
  47                 regulator-boot-on;
  48                 regulator-always-on;
  49         };
  50
  51         sound {
  52                 compatible = "amlogic,axg-sound-card";
  53                 model = "G12B-KHADAS-VIM3";
  54                 audio-aux-devs = <&tdmout_b>;
  55                 audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
  56                                 "TDMOUT_B IN 1", "FRDDR_B OUT 1",
  57                                 "TDMOUT_B IN 2", "FRDDR_C OUT 1",
  58                                 "TDM_B Playback", "TDMOUT_B OUT";
  59
  60                 assigned-clocks = <&clkc CLKID_MPLL2>,
  61                                   <&clkc CLKID_MPLL0>,
  62                                   <&clkc CLKID_MPLL1>;
  63                 assigned-clock-parents = <0>, <0>, <0>;
  64                 assigned-clock-rates = <294912000>,
  65                                        <270950400>,
  66                                        <393216000>;
  67                 status = "okay";
  68
  69                 dai-link-0 {
  70                         sound-dai = <&frddr_a>;
  71                 };
  72
  73                 dai-link-1 {
  74                         sound-dai = <&frddr_b>;
  75                 };
  76
  77                 dai-link-2 {
  78                         sound-dai = <&frddr_c>;
  79                 };
  80
  81                 /* 8ch hdmi interface */
  82                 dai-link-3 {
  83                         sound-dai = <&tdmif_b>;
  84                         dai-format = "i2s";
  85                         dai-tdm-slot-tx-mask-0 = <1 1>;
  86                         dai-tdm-slot-tx-mask-1 = <1 1>;
  87                         dai-tdm-slot-tx-mask-2 = <1 1>;
  88                         dai-tdm-slot-tx-mask-3 = <1 1>;
  89                         mclk-fs = <256>;
  90
  91                         codec {
  92                                 sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
  93                         };
  94                 };
  95
  96                 /* hdmi glue */
  97                 dai-link-4 {
  98                         sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
  99
 100                         codec {
 101                                 sound-dai = <&hdmi_tx>;
 102                         };
 103                 };
 104         };
 105 };
 106
 107 &arb {
 108         status = "okay";
 109 };
 110
 111 &clkc_audio {
 112         status = "okay";
 113 };
 114
 115 &cpu0 {
 116         cpu-supply = <&vddcpu_b>;
 117         operating-points-v2 = <&cpu_opp_table_0>;
 118         clocks = <&clkc CLKID_CPU_CLK>;
 119         clock-latency = <50000>;
 120 };
 121
 122 &cpu1 {
 123         cpu-supply = <&vddcpu_b>;
 124         operating-points-v2 = <&cpu_opp_table_0>;
 125         clocks = <&clkc CLKID_CPU_CLK>;
 126         clock-latency = <50000>;
 127 };
 128
 129 &cpu100 {
 130         cpu-supply = <&vddcpu_a>;
 131         operating-points-v2 = <&cpub_opp_table_1>;
 132         clocks = <&clkc CLKID_CPUB_CLK>;
 133         clock-latency = <50000>;
 134 };
 135
 136 &cpu101 {
 137         cpu-supply = <&vddcpu_a>;
 138         operating-points-v2 = <&cpub_opp_table_1>;
 139         clocks = <&clkc CLKID_CPUB_CLK>;
 140         clock-latency = <50000>;
 141 };
 142
 143 &cpu102 {
 144         cpu-supply = <&vddcpu_a>;
 145         operating-points-v2 = <&cpub_opp_table_1>;
 146         clocks = <&clkc CLKID_CPUB_CLK>;
 147         clock-latency = <50000>;
 148 };
 149
 150 &cpu103 {
 151         cpu-supply = <&vddcpu_a>;
 152         operating-points-v2 = <&cpub_opp_table_1>;
 153         clocks = <&clkc CLKID_CPUB_CLK>;
 154         clock-latency = <50000>;
 155 };
 156
 157 &frddr_a {
 158         status = "okay";
 159 };
 160
 161 &frddr_b {
 162         status = "okay";
 163 };
 164
 165 &frddr_c {
 166         status = "okay";
 167 };
 168
 169 &pwm_ab {
 170         pinctrl-0 = <&pwm_a_e_pins>;
 171         pinctrl-names = "default";
 172         clocks = <&xtal>;
 173         clock-names = "clkin0";
 174         status = "okay";
 175 };
 176
 177 &pwm_AO_cd {
 178         pinctrl-0 = <&pwm_ao_d_e_pins>;
 179         pinctrl-names = "default";
 180         clocks = <&xtal>;
 181         clock-names = "clkin1";
 182         status = "okay";
 183 };
 184
 185 &tdmif_b {
 186         status = "okay";
 187 };
 188
 189 &tdmout_b {
 190         status = "okay";
 191 };
 192
 193 &tohdmitx {
 194         status = "okay";
 195 };