1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
7 * Harninder Rai <harninder.rai@nxp.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "fsl,ls1028a";
16 interrupt-parent = <&gic>;
26 compatible = "arm,cortex-a72";
28 enable-method = "psci";
29 clocks = <&clockgen 1 0>;
30 next-level-cache = <&l2>;
31 cpu-idle-states = <&CPU_PW20>;
37 compatible = "arm,cortex-a72";
39 enable-method = "psci";
40 clocks = <&clockgen 1 0>;
41 next-level-cache = <&l2>;
42 cpu-idle-states = <&CPU_PW20>;
53 * PSCI node is not added default, U-boot will add missing
54 * parts if it determines to use PSCI.
56 entry-method = "psci";
59 compatible = "arm,idle-state";
60 idle-state-name = "PW20";
61 arm,psci-suspend-param = <0x0>;
62 entry-latency-us = <2000>;
63 exit-latency-us = <2000>;
64 min-residency-us = <6000>;
68 sysclk: clock-sysclk {
69 compatible = "fixed-clock";
71 clock-frequency = <100000000>;
72 clock-output-names = "sysclk";
75 osc_27m: clock-osc-27m {
76 compatible = "fixed-clock";
78 clock-frequency = <27000000>;
79 clock-output-names = "phy_27m";
82 dpclk: clock-controller@f1f0000 {
83 compatible = "fsl,ls1028a-plldig";
84 reg = <0x0 0xf1f0000 0x0 0xffff>;
90 compatible ="syscon-reboot";
97 compatible = "arm,armv8-timer";
98 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
101 IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
103 IRQ_TYPE_LEVEL_LOW)>,
104 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
105 IRQ_TYPE_LEVEL_LOW)>;
109 compatible = "arm,cortex-a72-pmu";
110 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
113 gic: interrupt-controller@6000000 {
114 compatible= "arm,gic-v3";
115 #address-cells = <2>;
118 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
119 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
120 #interrupt-cells= <3>;
121 interrupt-controller;
122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
123 IRQ_TYPE_LEVEL_LOW)>;
124 its: gic-its@6020000 {
125 compatible = "arm,gic-v3-its";
127 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
133 polling-delay-passive = <1000>;
134 polling-delay = <5000>;
135 thermal-sensors = <&tmu 0>;
138 core_cluster_alert: core-cluster-alert {
139 temperature = <85000>;
144 core_cluster_crit: core-cluster-crit {
145 temperature = <95000>;
153 trip = <&core_cluster_alert>;
155 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
156 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
163 compatible = "simple-bus";
164 #address-cells = <2>;
168 ddr: memory-controller@1080000 {
169 compatible = "fsl,qoriq-memory-controller";
170 reg = <0x0 0x1080000 0x0 0x1000>;
171 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
175 dcfg: syscon@1e00000 {
176 compatible = "fsl,ls1028a-dcfg", "syscon";
177 reg = <0x0 0x1e00000 0x0 0x10000>;
181 rst: syscon@1e60000 {
182 compatible = "syscon";
183 reg = <0x0 0x1e60000 0x0 0x10000>;
187 scfg: syscon@1fc0000 {
188 compatible = "fsl,ls1028a-scfg", "syscon";
189 reg = <0x0 0x1fc0000 0x0 0x10000>;
193 clockgen: clock-controller@1300000 {
194 compatible = "fsl,ls1028a-clockgen";
195 reg = <0x0 0x1300000 0x0 0xa0000>;
201 compatible = "fsl,vf610-i2c";
202 #address-cells = <1>;
204 reg = <0x0 0x2000000 0x0 0x10000>;
205 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&clockgen 4 3>;
211 compatible = "fsl,vf610-i2c";
212 #address-cells = <1>;
214 reg = <0x0 0x2010000 0x0 0x10000>;
215 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&clockgen 4 3>;
221 compatible = "fsl,vf610-i2c";
222 #address-cells = <1>;
224 reg = <0x0 0x2020000 0x0 0x10000>;
225 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clockgen 4 3>;
231 compatible = "fsl,vf610-i2c";
232 #address-cells = <1>;
234 reg = <0x0 0x2030000 0x0 0x10000>;
235 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&clockgen 4 3>;
241 compatible = "fsl,vf610-i2c";
242 #address-cells = <1>;
244 reg = <0x0 0x2040000 0x0 0x10000>;
245 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&clockgen 4 3>;
251 compatible = "fsl,vf610-i2c";
252 #address-cells = <1>;
254 reg = <0x0 0x2050000 0x0 0x10000>;
255 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&clockgen 4 3>;
261 compatible = "fsl,vf610-i2c";
262 #address-cells = <1>;
264 reg = <0x0 0x2060000 0x0 0x10000>;
265 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&clockgen 4 3>;
271 compatible = "fsl,vf610-i2c";
272 #address-cells = <1>;
274 reg = <0x0 0x2070000 0x0 0x10000>;
275 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&clockgen 4 3>;
281 compatible = "nxp,lx2160a-fspi";
282 #address-cells = <1>;
284 reg = <0x0 0x20c0000 0x0 0x10000>,
285 <0x0 0x20000000 0x0 0x10000000>;
286 reg-names = "fspi_base", "fspi_mmap";
287 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
289 clock-names = "fspi_en", "fspi";
294 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
295 #address-cells = <1>;
297 reg = <0x0 0x2100000 0x0 0x10000>;
298 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
299 clock-names = "dspi";
300 clocks = <&clockgen 4 1>;
301 spi-num-chipselects = <4>;
307 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
308 #address-cells = <1>;
310 reg = <0x0 0x2110000 0x0 0x10000>;
311 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
312 clock-names = "dspi";
313 clocks = <&clockgen 4 1>;
314 spi-num-chipselects = <4>;
320 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
321 #address-cells = <1>;
323 reg = <0x0 0x2120000 0x0 0x10000>;
324 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
325 clock-names = "dspi";
326 clocks = <&clockgen 4 1>;
327 spi-num-chipselects = <3>;
333 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
334 reg = <0x0 0x2140000 0x0 0x10000>;
335 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
336 clock-frequency = <0>; /* fixed up by bootloader */
337 clocks = <&clockgen 2 1>;
338 voltage-ranges = <1800 1800 3300 3300>;
345 esdhc1: mmc@2150000 {
346 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
347 reg = <0x0 0x2150000 0x0 0x10000>;
348 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
349 clock-frequency = <0>; /* fixed up by bootloader */
350 clocks = <&clockgen 2 1>;
351 voltage-ranges = <1800 1800 3300 3300>;
359 duart0: serial@21c0500 {
360 compatible = "fsl,ns16550", "ns16550a";
361 reg = <0x00 0x21c0500 0x0 0x100>;
362 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&clockgen 4 1>;
367 duart1: serial@21c0600 {
368 compatible = "fsl,ns16550", "ns16550a";
369 reg = <0x00 0x21c0600 0x0 0x100>;
370 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clockgen 4 1>;
376 lpuart0: serial@2260000 {
377 compatible = "fsl,ls1028a-lpuart";
378 reg = <0x0 0x2260000 0x0 0x1000>;
379 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clockgen 4 1>;
382 dma-names = "rx","tx";
383 dmas = <&edma0 1 32>,
388 lpuart1: serial@2270000 {
389 compatible = "fsl,ls1028a-lpuart";
390 reg = <0x0 0x2270000 0x0 0x1000>;
391 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&clockgen 4 1>;
394 dma-names = "rx","tx";
395 dmas = <&edma0 1 30>,
400 lpuart2: serial@2280000 {
401 compatible = "fsl,ls1028a-lpuart";
402 reg = <0x0 0x2280000 0x0 0x1000>;
403 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clockgen 4 1>;
406 dma-names = "rx","tx";
407 dmas = <&edma0 1 28>,
412 lpuart3: serial@2290000 {
413 compatible = "fsl,ls1028a-lpuart";
414 reg = <0x0 0x2290000 0x0 0x1000>;
415 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&clockgen 4 1>;
418 dma-names = "rx","tx";
419 dmas = <&edma0 1 26>,
424 lpuart4: serial@22a0000 {
425 compatible = "fsl,ls1028a-lpuart";
426 reg = <0x0 0x22a0000 0x0 0x1000>;
427 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&clockgen 4 1>;
430 dma-names = "rx","tx";
431 dmas = <&edma0 1 24>,
436 lpuart5: serial@22b0000 {
437 compatible = "fsl,ls1028a-lpuart";
438 reg = <0x0 0x22b0000 0x0 0x1000>;
439 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&clockgen 4 1>;
442 dma-names = "rx","tx";
443 dmas = <&edma0 1 22>,
448 edma0: dma-controller@22c0000 {
450 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";
451 reg = <0x0 0x22c0000 0x0 0x10000>,
452 <0x0 0x22d0000 0x0 0x10000>,
453 <0x0 0x22e0000 0x0 0x10000>;
454 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
456 interrupt-names = "edma-tx", "edma-err";
458 clock-names = "dmamux0", "dmamux1";
459 clocks = <&clockgen 4 1>,
463 gpio1: gpio@2300000 {
464 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
465 reg = <0x0 0x2300000 0x0 0x10000>;
466 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
474 gpio2: gpio@2310000 {
475 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
476 reg = <0x0 0x2310000 0x0 0x10000>;
477 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
480 interrupt-controller;
481 #interrupt-cells = <2>;
485 gpio3: gpio@2320000 {
486 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
487 reg = <0x0 0x2320000 0x0 0x10000>;
488 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
491 interrupt-controller;
492 #interrupt-cells = <2>;
497 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
498 reg = <0x0 0x3100000 0x0 0x10000>;
499 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
501 snps,dis_rxdet_inp3_quirk;
502 snps,quirk-frame-length-adjustment = <0x20>;
503 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
507 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
508 reg = <0x0 0x3110000 0x0 0x10000>;
509 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
511 snps,dis_rxdet_inp3_quirk;
512 snps,quirk-frame-length-adjustment = <0x20>;
513 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
517 compatible = "fsl,ls1028a-ahci";
518 reg = <0x0 0x3200000 0x0 0x10000>,
519 <0x7 0x100520 0x0 0x4>;
520 reg-names = "ahci", "sata-ecc";
521 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&clockgen 4 1>;
527 compatible = "fsl,ls1028a-pcie";
528 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
529 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
530 reg-names = "regs", "config";
531 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
532 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
533 interrupt-names = "pme", "aer";
534 #address-cells = <3>;
539 bus-range = <0x0 0xff>;
540 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
541 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
543 #interrupt-cells = <1>;
544 interrupt-map-mask = <0 0 0 7>;
545 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
546 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
547 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
548 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
549 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
554 compatible = "fsl,ls1028a-pcie";
555 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
556 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
557 reg-names = "regs", "config";
558 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
560 interrupt-names = "pme", "aer";
561 #address-cells = <3>;
566 bus-range = <0x0 0xff>;
567 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
568 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
570 #interrupt-cells = <1>;
571 interrupt-map-mask = <0 0 0 7>;
572 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
573 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
574 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
575 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
576 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
580 smmu: iommu@5000000 {
581 compatible = "arm,mmu-500";
582 reg = <0 0x5000000 0 0x800000>;
583 #global-interrupts = <8>;
585 stream-match-mask = <0x7c00>;
586 /* global secure fault */
587 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
588 /* combined secure interrupt */
589 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
590 /* global non-secure fault */
591 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
592 /* combined non-secure interrupt */
593 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
594 /* performance counter interrupts 0-7 */
595 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
597 /* per context interrupt, 64 interrupts */
598 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
632 crypto: crypto@8000000 {
633 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
635 #address-cells = <1>;
637 ranges = <0x0 0x00 0x8000000 0x100000>;
638 reg = <0x00 0x8000000 0x0 0x100000>;
639 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
643 compatible = "fsl,sec-v5.0-job-ring",
644 "fsl,sec-v4.0-job-ring";
645 reg = <0x10000 0x10000>;
646 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
650 compatible = "fsl,sec-v5.0-job-ring",
651 "fsl,sec-v4.0-job-ring";
652 reg = <0x20000 0x10000>;
653 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
657 compatible = "fsl,sec-v5.0-job-ring",
658 "fsl,sec-v4.0-job-ring";
659 reg = <0x30000 0x10000>;
660 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
664 compatible = "fsl,sec-v5.0-job-ring",
665 "fsl,sec-v4.0-job-ring";
666 reg = <0x40000 0x10000>;
667 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
671 qdma: dma-controller@8380000 {
672 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
673 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
674 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
675 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
676 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
681 interrupt-names = "qdma-error", "qdma-queue0",
682 "qdma-queue1", "qdma-queue2", "qdma-queue3";
685 block-offset = <0x10000>;
686 fsl,dma-queues = <2>;
688 queue-sizes = <64 64>;
691 cluster1_core0_watchdog: watchdog@c000000 {
692 compatible = "arm,sp805", "arm,primecell";
693 reg = <0x0 0xc000000 0x0 0x1000>;
694 clocks = <&clockgen 4 15>, <&clockgen 4 15>;
695 clock-names = "apb_pclk", "wdog_clk";
698 cluster1_core1_watchdog: watchdog@c010000 {
699 compatible = "arm,sp805", "arm,primecell";
700 reg = <0x0 0xc010000 0x0 0x1000>;
701 clocks = <&clockgen 4 15>, <&clockgen 4 15>;
702 clock-names = "apb_pclk", "wdog_clk";
705 sai1: audio-controller@f100000 {
706 #sound-dai-cells = <0>;
707 compatible = "fsl,vf610-sai";
708 reg = <0x0 0xf100000 0x0 0x10000>;
709 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
711 <&clockgen 4 1>, <&clockgen 4 1>;
712 clock-names = "bus", "mclk1", "mclk2", "mclk3";
713 dma-names = "tx", "rx";
716 fsl,sai-asynchronous;
720 sai2: audio-controller@f110000 {
721 #sound-dai-cells = <0>;
722 compatible = "fsl,vf610-sai";
723 reg = <0x0 0xf110000 0x0 0x10000>;
724 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
726 <&clockgen 4 1>, <&clockgen 4 1>;
727 clock-names = "bus", "mclk1", "mclk2", "mclk3";
728 dma-names = "tx", "rx";
731 fsl,sai-asynchronous;
735 sai3: audio-controller@f120000 {
736 #sound-dai-cells = <0>;
737 compatible = "fsl,vf610-sai";
738 reg = <0x0 0xf120000 0x0 0x10000>;
739 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
741 <&clockgen 4 1>, <&clockgen 4 1>;
742 clock-names = "bus", "mclk1", "mclk2", "mclk3";
743 dma-names = "tx", "rx";
746 fsl,sai-asynchronous;
750 sai4: audio-controller@f130000 {
751 #sound-dai-cells = <0>;
752 compatible = "fsl,vf610-sai";
753 reg = <0x0 0xf130000 0x0 0x10000>;
754 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
756 <&clockgen 4 1>, <&clockgen 4 1>;
757 clock-names = "bus", "mclk1", "mclk2", "mclk3";
758 dma-names = "tx", "rx";
759 dmas = <&edma0 1 10>,
761 fsl,sai-asynchronous;
765 sai5: audio-controller@f140000 {
766 #sound-dai-cells = <0>;
767 compatible = "fsl,vf610-sai";
768 reg = <0x0 0xf140000 0x0 0x10000>;
769 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
771 <&clockgen 4 1>, <&clockgen 4 1>;
772 clock-names = "bus", "mclk1", "mclk2", "mclk3";
773 dma-names = "tx", "rx";
774 dmas = <&edma0 1 12>,
776 fsl,sai-asynchronous;
780 sai6: audio-controller@f150000 {
781 #sound-dai-cells = <0>;
782 compatible = "fsl,vf610-sai";
783 reg = <0x0 0xf150000 0x0 0x10000>;
784 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
786 <&clockgen 4 1>, <&clockgen 4 1>;
787 clock-names = "bus", "mclk1", "mclk2", "mclk3";
788 dma-names = "tx", "rx";
789 dmas = <&edma0 1 14>,
791 fsl,sai-asynchronous;
796 compatible = "fsl,qoriq-tmu";
797 reg = <0x0 0x1f80000 0x0 0x10000>;
798 interrupts = <0 23 0x4>;
799 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
800 fsl,tmu-calibration = <0x00000000 0x00000024
801 0x00000001 0x0000002b
802 0x00000002 0x00000031
803 0x00000003 0x00000038
804 0x00000004 0x0000003f
805 0x00000005 0x00000045
806 0x00000006 0x0000004c
807 0x00000007 0x00000053
808 0x00000008 0x00000059
809 0x00000009 0x00000060
810 0x0000000a 0x00000066
811 0x0000000b 0x0000006d
813 0x00010000 0x0000001c
814 0x00010001 0x00000024
815 0x00010002 0x0000002c
816 0x00010003 0x00000035
817 0x00010004 0x0000003d
818 0x00010005 0x00000045
819 0x00010006 0x0000004d
820 0x00010007 0x00000055
821 0x00010008 0x0000005e
822 0x00010009 0x00000066
823 0x0001000a 0x0000006e
825 0x00020000 0x00000018
826 0x00020001 0x00000022
827 0x00020002 0x0000002d
828 0x00020003 0x00000038
829 0x00020004 0x00000043
830 0x00020005 0x0000004d
831 0x00020006 0x00000058
832 0x00020007 0x00000063
833 0x00020008 0x0000006e
835 0x00030000 0x00000010
836 0x00030001 0x0000001c
837 0x00030002 0x00000029
838 0x00030003 0x00000036
839 0x00030004 0x00000042
840 0x00030005 0x0000004f
841 0x00030006 0x0000005b
842 0x00030007 0x00000068>;
844 #thermal-sensor-cells = <1>;
847 pcie@1f0000000 { /* Integrated Endpoint Root Complex */
848 compatible = "pci-host-ecam-generic";
849 reg = <0x01 0xf0000000 0x0 0x100000>;
850 #address-cells = <3>;
854 bus-range = <0x0 0x0>;
856 msi-map = <0 &its 0x17 0xe>;
857 iommu-map = <0 &smmu 0x17 0xe>;
858 /* PF0-6 BAR0 - non-prefetchable memory */
859 ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000
860 /* PF0-6 BAR2 - prefetchable memory */
861 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000
862 /* PF0: VF0-1 BAR0 - non-prefetchable memory */
863 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000
864 /* PF0: VF0-1 BAR2 - prefetchable memory */
865 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000
866 /* PF1: VF0-1 BAR0 - non-prefetchable memory */
867 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000
868 /* PF1: VF0-1 BAR2 - prefetchable memory */
869 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000
870 /* BAR4 (PF5) - non-prefetchable memory */
871 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>;
873 enetc_port0: ethernet@0,0 {
874 compatible = "fsl,enetc";
875 reg = <0x000000 0 0 0 0>;
879 enetc_port1: ethernet@0,1 {
880 compatible = "fsl,enetc";
881 reg = <0x000100 0 0 0 0>;
885 enetc_port2: ethernet@0,2 {
886 compatible = "fsl,enetc";
887 reg = <0x000200 0 0 0 0>;
888 phy-mode = "internal";
897 enetc_mdio_pf3: mdio@0,3 {
898 compatible = "fsl,enetc-mdio";
899 reg = <0x000300 0 0 0 0>;
900 #address-cells = <1>;
905 compatible = "fsl,enetc-ptp";
906 reg = <0x000400 0 0 0 0>;
907 clocks = <&clockgen 4 0>;
912 mscc_felix: ethernet-switch@0,5 {
913 reg = <0x000500 0 0 0 0>;
915 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
919 #address-cells = <1>;
923 mscc_felix_port0: port@0 {
928 mscc_felix_port1: port@1 {
933 mscc_felix_port2: port@2 {
938 mscc_felix_port3: port@3 {
944 mscc_felix_port4: port@4 {
946 phy-mode = "internal";
955 mscc_felix_port5: port@5 {
957 phy-mode = "internal";
968 enetc_port3: ethernet@0,6 {
969 compatible = "fsl,enetc";
970 reg = <0x000600 0 0 0 0>;
971 phy-mode = "internal";
982 malidp0: display@f080000 {
983 compatible = "arm,mali-dp500";
984 reg = <0x0 0xf080000 0x0 0x10000>;
985 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
986 <0 223 IRQ_TYPE_LEVEL_HIGH>;
987 interrupt-names = "DE", "SE";
988 clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
990 clock-names = "pxlclk", "mclk", "aclk", "pclk";
991 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
992 arm,malidp-arqos-value = <0xd000d000>;