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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[thirdparty/linux.git] / arch / arm64 / boot / dts / hisilicon / hi3660.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dts file for Hisilicon Hi3660 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 */
7
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/hi3660-clock.h>
10 #include <dt-bindings/thermal/thermal.h>
11
12 / {
13 compatible = "hisilicon,hi3660";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 psci {
19 compatible = "arm,psci-0.2";
20 method = "smc";
21 };
22
23 cpus {
24 #address-cells = <2>;
25 #size-cells = <0>;
26
27 cpu-map {
28 cluster0 {
29 core0 {
30 cpu = <&cpu0>;
31 };
32 core1 {
33 cpu = <&cpu1>;
34 };
35 core2 {
36 cpu = <&cpu2>;
37 };
38 core3 {
39 cpu = <&cpu3>;
40 };
41 };
42 cluster1 {
43 core0 {
44 cpu = <&cpu4>;
45 };
46 core1 {
47 cpu = <&cpu5>;
48 };
49 core2 {
50 cpu = <&cpu6>;
51 };
52 core3 {
53 cpu = <&cpu7>;
54 };
55 };
56 };
57
58 cpu0: cpu@0 {
59 compatible = "arm,cortex-a53", "arm,armv8";
60 device_type = "cpu";
61 reg = <0x0 0x0>;
62 enable-method = "psci";
63 next-level-cache = <&A53_L2>;
64 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
65 capacity-dmips-mhz = <592>;
66 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
67 operating-points-v2 = <&cluster0_opp>;
68 #cooling-cells = <2>;
69 dynamic-power-coefficient = <110>;
70 };
71
72 cpu1: cpu@1 {
73 compatible = "arm,cortex-a53", "arm,armv8";
74 device_type = "cpu";
75 reg = <0x0 0x1>;
76 enable-method = "psci";
77 next-level-cache = <&A53_L2>;
78 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
79 capacity-dmips-mhz = <592>;
80 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
81 operating-points-v2 = <&cluster0_opp>;
82 };
83
84 cpu2: cpu@2 {
85 compatible = "arm,cortex-a53", "arm,armv8";
86 device_type = "cpu";
87 reg = <0x0 0x2>;
88 enable-method = "psci";
89 next-level-cache = <&A53_L2>;
90 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
91 capacity-dmips-mhz = <592>;
92 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
93 operating-points-v2 = <&cluster0_opp>;
94 };
95
96 cpu3: cpu@3 {
97 compatible = "arm,cortex-a53", "arm,armv8";
98 device_type = "cpu";
99 reg = <0x0 0x3>;
100 enable-method = "psci";
101 next-level-cache = <&A53_L2>;
102 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
103 capacity-dmips-mhz = <592>;
104 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
105 operating-points-v2 = <&cluster0_opp>;
106 };
107
108 cpu4: cpu@100 {
109 compatible = "arm,cortex-a73", "arm,armv8";
110 device_type = "cpu";
111 reg = <0x0 0x100>;
112 enable-method = "psci";
113 next-level-cache = <&A73_L2>;
114 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
115 capacity-dmips-mhz = <1024>;
116 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
117 operating-points-v2 = <&cluster1_opp>;
118 #cooling-cells = <2>;
119 dynamic-power-coefficient = <550>;
120 };
121
122 cpu5: cpu@101 {
123 compatible = "arm,cortex-a73", "arm,armv8";
124 device_type = "cpu";
125 reg = <0x0 0x101>;
126 enable-method = "psci";
127 next-level-cache = <&A73_L2>;
128 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
129 capacity-dmips-mhz = <1024>;
130 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
131 operating-points-v2 = <&cluster1_opp>;
132 };
133
134 cpu6: cpu@102 {
135 compatible = "arm,cortex-a73", "arm,armv8";
136 device_type = "cpu";
137 reg = <0x0 0x102>;
138 enable-method = "psci";
139 next-level-cache = <&A73_L2>;
140 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
141 capacity-dmips-mhz = <1024>;
142 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
143 operating-points-v2 = <&cluster1_opp>;
144 };
145
146 cpu7: cpu@103 {
147 compatible = "arm,cortex-a73", "arm,armv8";
148 device_type = "cpu";
149 reg = <0x0 0x103>;
150 enable-method = "psci";
151 next-level-cache = <&A73_L2>;
152 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
153 capacity-dmips-mhz = <1024>;
154 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
155 operating-points-v2 = <&cluster1_opp>;
156 };
157
158 idle-states {
159 entry-method = "psci";
160
161 CPU_SLEEP_0: cpu-sleep-0 {
162 compatible = "arm,idle-state";
163 local-timer-stop;
164 arm,psci-suspend-param = <0x0010000>;
165 entry-latency-us = <400>;
166 exit-latency-us = <650>;
167 min-residency-us = <1500>;
168 };
169 CLUSTER_SLEEP_0: cluster-sleep-0 {
170 compatible = "arm,idle-state";
171 local-timer-stop;
172 arm,psci-suspend-param = <0x1010000>;
173 entry-latency-us = <500>;
174 exit-latency-us = <1600>;
175 min-residency-us = <3500>;
176 };
177
178
179 CPU_SLEEP_1: cpu-sleep-1 {
180 compatible = "arm,idle-state";
181 local-timer-stop;
182 arm,psci-suspend-param = <0x0010000>;
183 entry-latency-us = <400>;
184 exit-latency-us = <550>;
185 min-residency-us = <1500>;
186 };
187
188 CLUSTER_SLEEP_1: cluster-sleep-1 {
189 compatible = "arm,idle-state";
190 local-timer-stop;
191 arm,psci-suspend-param = <0x1010000>;
192 entry-latency-us = <800>;
193 exit-latency-us = <2900>;
194 min-residency-us = <3500>;
195 };
196 };
197
198 A53_L2: l2-cache0 {
199 compatible = "cache";
200 };
201
202 A73_L2: l2-cache1 {
203 compatible = "cache";
204 };
205 };
206
207 cluster0_opp: opp_table0 {
208 compatible = "operating-points-v2";
209 opp-shared;
210
211 opp00 {
212 opp-hz = /bits/ 64 <533000000>;
213 opp-microvolt = <700000>;
214 clock-latency-ns = <300000>;
215 };
216
217 opp01 {
218 opp-hz = /bits/ 64 <999000000>;
219 opp-microvolt = <800000>;
220 clock-latency-ns = <300000>;
221 };
222
223 opp02 {
224 opp-hz = /bits/ 64 <1402000000>;
225 opp-microvolt = <900000>;
226 clock-latency-ns = <300000>;
227 };
228
229 opp03 {
230 opp-hz = /bits/ 64 <1709000000>;
231 opp-microvolt = <1000000>;
232 clock-latency-ns = <300000>;
233 };
234
235 opp04 {
236 opp-hz = /bits/ 64 <1844000000>;
237 opp-microvolt = <1100000>;
238 clock-latency-ns = <300000>;
239 };
240 };
241
242 cluster1_opp: opp_table1 {
243 compatible = "operating-points-v2";
244 opp-shared;
245
246 opp10 {
247 opp-hz = /bits/ 64 <903000000>;
248 opp-microvolt = <700000>;
249 clock-latency-ns = <300000>;
250 };
251
252 opp11 {
253 opp-hz = /bits/ 64 <1421000000>;
254 opp-microvolt = <800000>;
255 clock-latency-ns = <300000>;
256 };
257
258 opp12 {
259 opp-hz = /bits/ 64 <1805000000>;
260 opp-microvolt = <900000>;
261 clock-latency-ns = <300000>;
262 };
263
264 opp13 {
265 opp-hz = /bits/ 64 <2112000000>;
266 opp-microvolt = <1000000>;
267 clock-latency-ns = <300000>;
268 };
269
270 opp14 {
271 opp-hz = /bits/ 64 <2362000000>;
272 opp-microvolt = <1100000>;
273 clock-latency-ns = <300000>;
274 };
275 };
276
277 gic: interrupt-controller@e82b0000 {
278 compatible = "arm,gic-400";
279 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
280 <0x0 0xe82b2000 0 0x2000>, /* GICC */
281 <0x0 0xe82b4000 0 0x2000>, /* GICH */
282 <0x0 0xe82b6000 0 0x2000>; /* GICV */
283 #address-cells = <0>;
284 #interrupt-cells = <3>;
285 interrupt-controller;
286 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
287 IRQ_TYPE_LEVEL_HIGH)>;
288 };
289
290 a53-pmu {
291 compatible = "arm,cortex-a53-pmu";
292 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-affinity = <&cpu0>,
297 <&cpu1>,
298 <&cpu2>,
299 <&cpu3>;
300 };
301
302 a73-pmu {
303 compatible = "arm,cortex-a73-pmu";
304 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
308 interrupt-affinity = <&cpu4>,
309 <&cpu5>,
310 <&cpu6>,
311 <&cpu7>;
312 };
313
314 timer {
315 compatible = "arm,armv8-timer";
316 interrupt-parent = <&gic>;
317 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
318 IRQ_TYPE_LEVEL_LOW)>,
319 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
320 IRQ_TYPE_LEVEL_LOW)>,
321 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
322 IRQ_TYPE_LEVEL_LOW)>,
323 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
324 IRQ_TYPE_LEVEL_LOW)>;
325 };
326
327 soc {
328 compatible = "simple-bus";
329 #address-cells = <2>;
330 #size-cells = <2>;
331 ranges;
332
333 crg_ctrl: crg_ctrl@fff35000 {
334 compatible = "hisilicon,hi3660-crgctrl", "syscon";
335 reg = <0x0 0xfff35000 0x0 0x1000>;
336 #clock-cells = <1>;
337 };
338
339 crg_rst: crg_rst_controller {
340 compatible = "hisilicon,hi3660-reset";
341 #reset-cells = <2>;
342 hisi,rst-syscon = <&crg_ctrl>;
343 };
344
345
346 pctrl: pctrl@e8a09000 {
347 compatible = "hisilicon,hi3660-pctrl", "syscon";
348 reg = <0x0 0xe8a09000 0x0 0x2000>;
349 #clock-cells = <1>;
350 };
351
352 pmuctrl: crg_ctrl@fff34000 {
353 compatible = "hisilicon,hi3660-pmuctrl", "syscon";
354 reg = <0x0 0xfff34000 0x0 0x1000>;
355 #clock-cells = <1>;
356 };
357
358 sctrl: sctrl@fff0a000 {
359 compatible = "hisilicon,hi3660-sctrl", "syscon";
360 reg = <0x0 0xfff0a000 0x0 0x1000>;
361 #clock-cells = <1>;
362 };
363
364 iomcu: iomcu@ffd7e000 {
365 compatible = "hisilicon,hi3660-iomcu", "syscon";
366 reg = <0x0 0xffd7e000 0x0 0x1000>;
367 #clock-cells = <1>;
368
369 };
370
371 iomcu_rst: reset {
372 compatible = "hisilicon,hi3660-reset";
373 hisi,rst-syscon = <&iomcu>;
374 #reset-cells = <2>;
375 };
376
377 mailbox: mailbox@e896b000 {
378 compatible = "hisilicon,hi3660-mbox";
379 reg = <0x0 0xe896b000 0x0 0x1000>;
380 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
382 #mbox-cells = <3>;
383 };
384
385 stub_clock: stub_clock@e896b500 {
386 compatible = "hisilicon,hi3660-stub-clk";
387 reg = <0x0 0xe896b500 0x0 0x0100>;
388 #clock-cells = <1>;
389 mboxes = <&mailbox 13 3 0>;
390 };
391
392 dual_timer0: timer@fff14000 {
393 compatible = "arm,sp804", "arm,primecell";
394 reg = <0x0 0xfff14000 0x0 0x1000>;
395 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&crg_ctrl HI3660_OSC32K>,
398 <&crg_ctrl HI3660_OSC32K>,
399 <&crg_ctrl HI3660_OSC32K>;
400 clock-names = "timer1", "timer2", "apb_pclk";
401 };
402
403 i2c0: i2c@ffd71000 {
404 compatible = "snps,designware-i2c";
405 reg = <0x0 0xffd71000 0x0 0x1000>;
406 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409 clock-frequency = <400000>;
410 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
411 resets = <&iomcu_rst 0x20 3>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
414 status = "disabled";
415 };
416
417 i2c1: i2c@ffd72000 {
418 compatible = "snps,designware-i2c";
419 reg = <0x0 0xffd72000 0x0 0x1000>;
420 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
421 #address-cells = <1>;
422 #size-cells = <0>;
423 clock-frequency = <400000>;
424 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
425 resets = <&iomcu_rst 0x20 4>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
428 status = "disabled";
429 };
430
431 i2c3: i2c@fdf0c000 {
432 compatible = "snps,designware-i2c";
433 reg = <0x0 0xfdf0c000 0x0 0x1000>;
434 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
435 #address-cells = <1>;
436 #size-cells = <0>;
437 clock-frequency = <400000>;
438 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
439 resets = <&crg_rst 0x78 7>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
442 status = "disabled";
443 };
444
445 i2c7: i2c@fdf0b000 {
446 compatible = "snps,designware-i2c";
447 reg = <0x0 0xfdf0b000 0x0 0x1000>;
448 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
449 #address-cells = <1>;
450 #size-cells = <0>;
451 clock-frequency = <400000>;
452 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
453 resets = <&crg_rst 0x60 14>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
456 status = "disabled";
457 };
458
459 uart0: serial@fdf02000 {
460 compatible = "arm,pl011", "arm,primecell";
461 reg = <0x0 0xfdf02000 0x0 0x1000>;
462 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
464 <&crg_ctrl HI3660_PCLK>;
465 clock-names = "uartclk", "apb_pclk";
466 pinctrl-names = "default";
467 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
468 status = "disabled";
469 };
470
471 uart1: serial@fdf00000 {
472 compatible = "arm,pl011", "arm,primecell";
473 reg = <0x0 0xfdf00000 0x0 0x1000>;
474 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
476 <&crg_ctrl HI3660_CLK_GATE_UART1>;
477 clock-names = "uartclk", "apb_pclk";
478 pinctrl-names = "default";
479 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
480 status = "disabled";
481 };
482
483 uart2: serial@fdf03000 {
484 compatible = "arm,pl011", "arm,primecell";
485 reg = <0x0 0xfdf03000 0x0 0x1000>;
486 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
488 <&crg_ctrl HI3660_PCLK>;
489 clock-names = "uartclk", "apb_pclk";
490 pinctrl-names = "default";
491 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
492 status = "disabled";
493 };
494
495 uart3: serial@ffd74000 {
496 compatible = "arm,pl011", "arm,primecell";
497 reg = <0x0 0xffd74000 0x0 0x1000>;
498 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
500 <&crg_ctrl HI3660_PCLK>;
501 clock-names = "uartclk", "apb_pclk";
502 pinctrl-names = "default";
503 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
504 status = "disabled";
505 };
506
507 uart4: serial@fdf01000 {
508 compatible = "arm,pl011", "arm,primecell";
509 reg = <0x0 0xfdf01000 0x0 0x1000>;
510 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
512 <&crg_ctrl HI3660_CLK_GATE_UART4>;
513 clock-names = "uartclk", "apb_pclk";
514 pinctrl-names = "default";
515 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
516 status = "disabled";
517 };
518
519 uart5: serial@fdf05000 {
520 compatible = "arm,pl011", "arm,primecell";
521 reg = <0x0 0xfdf05000 0x0 0x1000>;
522 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
524 <&crg_ctrl HI3660_CLK_GATE_UART5>;
525 clock-names = "uartclk", "apb_pclk";
526 pinctrl-names = "default";
527 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
528 status = "disabled";
529 };
530
531 uart6: serial@fff32000 {
532 compatible = "arm,pl011", "arm,primecell";
533 reg = <0x0 0xfff32000 0x0 0x1000>;
534 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&crg_ctrl HI3660_CLK_UART6>,
536 <&crg_ctrl HI3660_PCLK>;
537 clock-names = "uartclk", "apb_pclk";
538 pinctrl-names = "default";
539 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
540 status = "disabled";
541 };
542
543 dma0: dma@fdf30000 {
544 compatible = "hisilicon,k3-dma-1.0";
545 reg = <0x0 0xfdf30000 0x0 0x1000>;
546 #dma-cells = <1>;
547 dma-channels = <16>;
548 dma-requests = <32>;
549 dma-min-chan = <1>;
550 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
552 dma-no-cci;
553 dma-type = "hi3660_dma";
554 };
555
556 rtc0: rtc@fff04000 {
557 compatible = "arm,pl031", "arm,primecell";
558 reg = <0x0 0Xfff04000 0x0 0x1000>;
559 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&crg_ctrl HI3660_PCLK>;
561 clock-names = "apb_pclk";
562 };
563
564 gpio0: gpio@e8a0b000 {
565 compatible = "arm,pl061", "arm,primecell";
566 reg = <0 0xe8a0b000 0 0x1000>;
567 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
568 gpio-controller;
569 #gpio-cells = <2>;
570 gpio-ranges = <&pmx0 1 0 7>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
573 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
574 clock-names = "apb_pclk";
575 };
576
577 gpio1: gpio@e8a0c000 {
578 compatible = "arm,pl061", "arm,primecell";
579 reg = <0 0xe8a0c000 0 0x1000>;
580 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
581 gpio-controller;
582 #gpio-cells = <2>;
583 gpio-ranges = <&pmx0 1 7 7>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
586 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
587 clock-names = "apb_pclk";
588 };
589
590 gpio2: gpio@e8a0d000 {
591 compatible = "arm,pl061", "arm,primecell";
592 reg = <0 0xe8a0d000 0 0x1000>;
593 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
594 gpio-controller;
595 #gpio-cells = <2>;
596 gpio-ranges = <&pmx0 0 14 8>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
599 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
600 clock-names = "apb_pclk";
601 };
602
603 gpio3: gpio@e8a0e000 {
604 compatible = "arm,pl061", "arm,primecell";
605 reg = <0 0xe8a0e000 0 0x1000>;
606 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
607 gpio-controller;
608 #gpio-cells = <2>;
609 gpio-ranges = <&pmx0 0 22 8>;
610 interrupt-controller;
611 #interrupt-cells = <2>;
612 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
613 clock-names = "apb_pclk";
614 };
615
616 gpio4: gpio@e8a0f000 {
617 compatible = "arm,pl061", "arm,primecell";
618 reg = <0 0xe8a0f000 0 0x1000>;
619 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
620 gpio-controller;
621 #gpio-cells = <2>;
622 gpio-ranges = <&pmx0 0 30 8>;
623 interrupt-controller;
624 #interrupt-cells = <2>;
625 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
626 clock-names = "apb_pclk";
627 };
628
629 gpio5: gpio@e8a10000 {
630 compatible = "arm,pl061", "arm,primecell";
631 reg = <0 0xe8a10000 0 0x1000>;
632 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
633 gpio-controller;
634 #gpio-cells = <2>;
635 gpio-ranges = <&pmx0 0 38 8>;
636 interrupt-controller;
637 #interrupt-cells = <2>;
638 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
639 clock-names = "apb_pclk";
640 };
641
642 gpio6: gpio@e8a11000 {
643 compatible = "arm,pl061", "arm,primecell";
644 reg = <0 0xe8a11000 0 0x1000>;
645 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
646 gpio-controller;
647 #gpio-cells = <2>;
648 gpio-ranges = <&pmx0 0 46 8>;
649 interrupt-controller;
650 #interrupt-cells = <2>;
651 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
652 clock-names = "apb_pclk";
653 };
654
655 gpio7: gpio@e8a12000 {
656 compatible = "arm,pl061", "arm,primecell";
657 reg = <0 0xe8a12000 0 0x1000>;
658 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
659 gpio-controller;
660 #gpio-cells = <2>;
661 gpio-ranges = <&pmx0 0 54 8>;
662 interrupt-controller;
663 #interrupt-cells = <2>;
664 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
665 clock-names = "apb_pclk";
666 };
667
668 gpio8: gpio@e8a13000 {
669 compatible = "arm,pl061", "arm,primecell";
670 reg = <0 0xe8a13000 0 0x1000>;
671 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
672 gpio-controller;
673 #gpio-cells = <2>;
674 gpio-ranges = <&pmx0 0 62 8>;
675 interrupt-controller;
676 #interrupt-cells = <2>;
677 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
678 clock-names = "apb_pclk";
679 };
680
681 gpio9: gpio@e8a14000 {
682 compatible = "arm,pl061", "arm,primecell";
683 reg = <0 0xe8a14000 0 0x1000>;
684 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
685 gpio-controller;
686 #gpio-cells = <2>;
687 gpio-ranges = <&pmx0 0 70 8>;
688 interrupt-controller;
689 #interrupt-cells = <2>;
690 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
691 clock-names = "apb_pclk";
692 };
693
694 gpio10: gpio@e8a15000 {
695 compatible = "arm,pl061", "arm,primecell";
696 reg = <0 0xe8a15000 0 0x1000>;
697 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
698 gpio-controller;
699 #gpio-cells = <2>;
700 gpio-ranges = <&pmx0 0 78 8>;
701 interrupt-controller;
702 #interrupt-cells = <2>;
703 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
704 clock-names = "apb_pclk";
705 };
706
707 gpio11: gpio@e8a16000 {
708 compatible = "arm,pl061", "arm,primecell";
709 reg = <0 0xe8a16000 0 0x1000>;
710 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
711 gpio-controller;
712 #gpio-cells = <2>;
713 gpio-ranges = <&pmx0 0 86 8>;
714 interrupt-controller;
715 #interrupt-cells = <2>;
716 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
717 clock-names = "apb_pclk";
718 };
719
720 gpio12: gpio@e8a17000 {
721 compatible = "arm,pl061", "arm,primecell";
722 reg = <0 0xe8a17000 0 0x1000>;
723 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
724 gpio-controller;
725 #gpio-cells = <2>;
726 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
727 interrupt-controller;
728 #interrupt-cells = <2>;
729 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
730 clock-names = "apb_pclk";
731 };
732
733 gpio13: gpio@e8a18000 {
734 compatible = "arm,pl061", "arm,primecell";
735 reg = <0 0xe8a18000 0 0x1000>;
736 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
737 gpio-controller;
738 #gpio-cells = <2>;
739 gpio-ranges = <&pmx0 0 102 8>;
740 interrupt-controller;
741 #interrupt-cells = <2>;
742 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
743 clock-names = "apb_pclk";
744 };
745
746 gpio14: gpio@e8a19000 {
747 compatible = "arm,pl061", "arm,primecell";
748 reg = <0 0xe8a19000 0 0x1000>;
749 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
750 gpio-controller;
751 #gpio-cells = <2>;
752 gpio-ranges = <&pmx0 0 110 8>;
753 interrupt-controller;
754 #interrupt-cells = <2>;
755 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
756 clock-names = "apb_pclk";
757 };
758
759 gpio15: gpio@e8a1a000 {
760 compatible = "arm,pl061", "arm,primecell";
761 reg = <0 0xe8a1a000 0 0x1000>;
762 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
763 gpio-controller;
764 #gpio-cells = <2>;
765 gpio-ranges = <&pmx0 0 118 6>;
766 interrupt-controller;
767 #interrupt-cells = <2>;
768 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
769 clock-names = "apb_pclk";
770 };
771
772 gpio16: gpio@e8a1b000 {
773 compatible = "arm,pl061", "arm,primecell";
774 reg = <0 0xe8a1b000 0 0x1000>;
775 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
776 gpio-controller;
777 #gpio-cells = <2>;
778 interrupt-controller;
779 #interrupt-cells = <2>;
780 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
781 clock-names = "apb_pclk";
782 };
783
784 gpio17: gpio@e8a1c000 {
785 compatible = "arm,pl061", "arm,primecell";
786 reg = <0 0xe8a1c000 0 0x1000>;
787 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
788 gpio-controller;
789 #gpio-cells = <2>;
790 interrupt-controller;
791 #interrupt-cells = <2>;
792 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
793 clock-names = "apb_pclk";
794 };
795
796 gpio18: gpio@ff3b4000 {
797 compatible = "arm,pl061", "arm,primecell";
798 reg = <0 0xff3b4000 0 0x1000>;
799 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
800 gpio-controller;
801 #gpio-cells = <2>;
802 gpio-ranges = <&pmx2 0 0 8>;
803 interrupt-controller;
804 #interrupt-cells = <2>;
805 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
806 clock-names = "apb_pclk";
807 };
808
809 gpio19: gpio@ff3b5000 {
810 compatible = "arm,pl061", "arm,primecell";
811 reg = <0 0xff3b5000 0 0x1000>;
812 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
813 gpio-controller;
814 #gpio-cells = <2>;
815 gpio-ranges = <&pmx2 0 8 4>;
816 interrupt-controller;
817 #interrupt-cells = <2>;
818 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
819 clock-names = "apb_pclk";
820 };
821
822 gpio20: gpio@e8a1f000 {
823 compatible = "arm,pl061", "arm,primecell";
824 reg = <0 0xe8a1f000 0 0x1000>;
825 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
826 gpio-controller;
827 #gpio-cells = <2>;
828 gpio-ranges = <&pmx1 0 0 6>;
829 interrupt-controller;
830 #interrupt-cells = <2>;
831 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
832 clock-names = "apb_pclk";
833 };
834
835 gpio21: gpio@e8a20000 {
836 compatible = "arm,pl061", "arm,primecell";
837 reg = <0 0xe8a20000 0 0x1000>;
838 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
839 gpio-controller;
840 #gpio-cells = <2>;
841 interrupt-controller;
842 #interrupt-cells = <2>;
843 gpio-ranges = <&pmx3 0 0 6>;
844 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
845 clock-names = "apb_pclk";
846 };
847
848 gpio22: gpio@fff0b000 {
849 compatible = "arm,pl061", "arm,primecell";
850 reg = <0 0xfff0b000 0 0x1000>;
851 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
852 gpio-controller;
853 #gpio-cells = <2>;
854 /* GPIO176 */
855 gpio-ranges = <&pmx4 2 0 6>;
856 interrupt-controller;
857 #interrupt-cells = <2>;
858 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
859 clock-names = "apb_pclk";
860 };
861
862 gpio23: gpio@fff0c000 {
863 compatible = "arm,pl061", "arm,primecell";
864 reg = <0 0xfff0c000 0 0x1000>;
865 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
866 gpio-controller;
867 #gpio-cells = <2>;
868 /* GPIO184 */
869 gpio-ranges = <&pmx4 0 6 7>;
870 interrupt-controller;
871 #interrupt-cells = <2>;
872 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
873 clock-names = "apb_pclk";
874 };
875
876 gpio24: gpio@fff0d000 {
877 compatible = "arm,pl061", "arm,primecell";
878 reg = <0 0xfff0d000 0 0x1000>;
879 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
880 gpio-controller;
881 #gpio-cells = <2>;
882 /* GPIO192 */
883 gpio-ranges = <&pmx4 0 13 8>;
884 interrupt-controller;
885 #interrupt-cells = <2>;
886 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
887 clock-names = "apb_pclk";
888 };
889
890 gpio25: gpio@fff0e000 {
891 compatible = "arm,pl061", "arm,primecell";
892 reg = <0 0xfff0e000 0 0x1000>;
893 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
894 gpio-controller;
895 #gpio-cells = <2>;
896 /* GPIO200 */
897 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
898 interrupt-controller;
899 #interrupt-cells = <2>;
900 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
901 clock-names = "apb_pclk";
902 };
903
904 gpio26: gpio@fff0f000 {
905 compatible = "arm,pl061", "arm,primecell";
906 reg = <0 0xfff0f000 0 0x1000>;
907 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
908 gpio-controller;
909 #gpio-cells = <2>;
910 /* GPIO208 */
911 gpio-ranges = <&pmx4 0 28 8>;
912 interrupt-controller;
913 #interrupt-cells = <2>;
914 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
915 clock-names = "apb_pclk";
916 };
917
918 gpio27: gpio@fff10000 {
919 compatible = "arm,pl061", "arm,primecell";
920 reg = <0 0xfff10000 0 0x1000>;
921 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
922 gpio-controller;
923 #gpio-cells = <2>;
924 /* GPIO216 */
925 gpio-ranges = <&pmx4 0 36 6>;
926 interrupt-controller;
927 #interrupt-cells = <2>;
928 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
929 clock-names = "apb_pclk";
930 };
931
932 gpio28: gpio@fff1d000 {
933 compatible = "arm,pl061", "arm,primecell";
934 reg = <0 0xfff1d000 0 0x1000>;
935 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
936 gpio-controller;
937 #gpio-cells = <2>;
938 interrupt-controller;
939 #interrupt-cells = <2>;
940 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
941 clock-names = "apb_pclk";
942 };
943
944 spi2: spi@ffd68000 {
945 compatible = "arm,pl022", "arm,primecell";
946 reg = <0x0 0xffd68000 0x0 0x1000>;
947 #address-cells = <1>;
948 #size-cells = <0>;
949 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
951 clock-names = "apb_pclk";
952 pinctrl-names = "default";
953 pinctrl-0 = <&spi2_pmx_func>;
954 num-cs = <1>;
955 cs-gpios = <&gpio27 2 0>;
956 status = "disabled";
957 };
958
959 spi3: spi@ff3b3000 {
960 compatible = "arm,pl022", "arm,primecell";
961 reg = <0x0 0xff3b3000 0x0 0x1000>;
962 #address-cells = <1>;
963 #size-cells = <0>;
964 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
965 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
966 clock-names = "apb_pclk";
967 pinctrl-names = "default";
968 pinctrl-0 = <&spi3_pmx_func>;
969 num-cs = <1>;
970 cs-gpios = <&gpio18 5 0>;
971 status = "disabled";
972 };
973
974 pcie@f4000000 {
975 compatible = "hisilicon,kirin960-pcie";
976 reg = <0x0 0xf4000000 0x0 0x1000>,
977 <0x0 0xff3fe000 0x0 0x1000>,
978 <0x0 0xf3f20000 0x0 0x40000>,
979 <0x0 0xf5000000 0x0 0x2000>;
980 reg-names = "dbi", "apb", "phy", "config";
981 bus-range = <0x0 0x1>;
982 #address-cells = <3>;
983 #size-cells = <2>;
984 device_type = "pci";
985 ranges = <0x02000000 0x0 0x00000000
986 0x0 0xf6000000
987 0x0 0x02000000>;
988 num-lanes = <1>;
989 #interrupt-cells = <1>;
990 interrupts = <0 283 4>;
991 interrupt-names = "msi";
992 interrupt-map-mask = <0xf800 0 0 7>;
993 interrupt-map = <0x0 0 0 1
994 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
995 <0x0 0 0 2
996 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
997 <0x0 0 0 3
998 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
999 <0x0 0 0 4
1000 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
1002 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
1003 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
1004 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
1005 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
1006 clock-names = "pcie_phy_ref", "pcie_aux",
1007 "pcie_apb_phy", "pcie_apb_sys",
1008 "pcie_aclk";
1009 reset-gpios = <&gpio11 1 0 >;
1010 };
1011
1012 /* UFS */
1013 ufs: ufs@ff3b0000 {
1014 compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
1015 /* 0: HCI standard */
1016 /* 1: UFS SYS CTRL */
1017 reg = <0x0 0xff3b0000 0x0 0x1000>,
1018 <0x0 0xff3b1000 0x0 0x1000>;
1019 interrupt-parent = <&gic>;
1020 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
1022 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
1023 clock-names = "ref_clk", "phy_clk";
1024 freq-table-hz = <0 0>, <0 0>;
1025 /* offset: 0x84; bit: 12 */
1026 resets = <&crg_rst 0x84 12>;
1027 reset-names = "rst";
1028 };
1029
1030 /* SD */
1031 dwmmc1: dwmmc1@ff37f000 {
1032 compatible = "hisilicon,hi3660-dw-mshc";
1033 reg = <0x0 0xff37f000 0x0 0x1000>;
1034 #address-cells = <1>;
1035 #size-cells = <0>;
1036 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
1038 <&crg_ctrl HI3660_HCLK_GATE_SD>;
1039 clock-names = "ciu", "biu";
1040 clock-frequency = <3200000>;
1041 resets = <&crg_rst 0x94 18>;
1042 reset-names = "reset";
1043 hisilicon,peripheral-syscon = <&sctrl>;
1044 card-detect-delay = <200>;
1045 status = "disabled";
1046 };
1047
1048 /* SDIO */
1049 dwmmc2: dwmmc2@ff3ff000 {
1050 compatible = "hisilicon,hi3660-dw-mshc";
1051 reg = <0x0 0xff3ff000 0x0 0x1000>;
1052 #address-cells = <0x1>;
1053 #size-cells = <0x0>;
1054 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1055 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
1056 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
1057 clock-names = "ciu", "biu";
1058 resets = <&crg_rst 0x94 20>;
1059 reset-names = "reset";
1060 card-detect-delay = <200>;
1061 status = "disabled";
1062 };
1063
1064 watchdog0: watchdog@e8a06000 {
1065 compatible = "arm,sp805-wdt", "arm,primecell";
1066 reg = <0x0 0xe8a06000 0x0 0x1000>;
1067 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&crg_ctrl HI3660_OSC32K>;
1069 clock-names = "apb_pclk";
1070 };
1071
1072 watchdog1: watchdog@e8a07000 {
1073 compatible = "arm,sp805-wdt", "arm,primecell";
1074 reg = <0x0 0xe8a07000 0x0 0x1000>;
1075 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&crg_ctrl HI3660_OSC32K>;
1077 clock-names = "apb_pclk";
1078 };
1079
1080 tsensor: tsensor@fff30000 {
1081 compatible = "hisilicon,hi3660-tsensor";
1082 reg = <0x0 0xfff30000 0x0 0x1000>;
1083 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1084 #thermal-sensor-cells = <1>;
1085 };
1086
1087 thermal-zones {
1088
1089 cls0: cls0 {
1090 polling-delay = <1000>;
1091 polling-delay-passive = <100>;
1092 sustainable-power = <4500>;
1093
1094 /* sensor ID */
1095 thermal-sensors = <&tsensor 1>;
1096
1097 trips {
1098 threshold: trip-point@0 {
1099 temperature = <65000>;
1100 hysteresis = <1000>;
1101 type = "passive";
1102 };
1103
1104 target: trip-point@1 {
1105 temperature = <75000>;
1106 hysteresis = <1000>;
1107 type = "passive";
1108 };
1109 };
1110
1111 cooling-maps {
1112 map0 {
1113 trip = <&target>;
1114 contribution = <1024>;
1115 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1116 };
1117 map1 {
1118 trip = <&target>;
1119 contribution = <512>;
1120 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1121 };
1122 };
1123 };
1124 };
1125 };
1126 };
A mirror of Linus' kernel repository