1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for Globalscale Marvell ESPRESSOBin Board
4 * Copyright (C) 2016 Marvell
6 * Romain Perier <romain.perier@free-electrons.com>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "armada-372x.dtsi"
16 /* for DSA user port device */
17 ethernet1 = &switch0port1;
18 ethernet2 = &switch0port2;
19 ethernet3 = &switch0port3;
23 stdout-path = "serial0:115200n8";
27 device_type = "memory";
28 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
31 vcc_sd_reg1: regulator {
32 compatible = "regulator-gpio";
33 regulator-name = "vcc_sd1";
34 regulator-min-microvolt = <1800000>;
35 regulator-max-microvolt = <3300000>;
38 gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
46 /* led2 is working only on v7 board */
49 compatible = "gpio-leds";
53 gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
54 default-state = "off";
62 pinctrl-names = "default";
63 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
64 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
74 /* Main DTS file for Espressobin is without eMMC */
82 marvell,xenon-tun-count = <9>;
83 marvell,pad-type = "fixed-1-8v";
85 pinctrl-names = "default";
86 pinctrl-0 = <&mmc_pins>;
91 compatible = "mmc-card";
100 cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
101 marvell,pad-type = "sd";
102 vqmmc-supply = <&vcc_sd_reg1>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&sdio_pins>;
114 compatible = "jedec,spi-nor";
115 spi-max-frequency = <104000000>;
120 /* Exported on the micro USB connector J5 through an FTDI */
122 pinctrl-names = "default";
123 pinctrl-0 = <&uart1_pins>;
128 * Connector J17 and J18 expose a number of different features. Some pins are
129 * multiplexed. This is the case for instance for the following features:
130 * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
131 * how to enable it. Beware that the signals are 1.8V TTL.
148 switch0: ethernet-switch@1 {
149 compatible = "marvell,mv88e6085";
155 #address-cells = <1>;
158 switch0port0: ethernet-port@0 {
162 phy-mode = "rgmii-id";
169 switch0port1: ethernet-port@1 {
172 phy-handle = <&switch0phy0>;
175 switch0port2: ethernet-port@2 {
178 phy-handle = <&switch0phy1>;
181 switch0port3: ethernet-port@3 {
184 phy-handle = <&switch0phy2>;
190 #address-cells = <1>;
193 switch0phy0: ethernet-phy@11 {
196 switch0phy1: ethernet-phy@12 {
199 switch0phy2: ethernet-phy@13 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
209 phy-mode = "rgmii-id";