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Merge tag 'io_uring-5.7-2020-05-22' of git://git.kernel.dk/linux-block
[thirdparty/linux.git] / arch / arm64 / boot / dts / renesas / r8a77980-condor.dts
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the Condor board
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9 /dts-v1/;
10 #include "r8a77980.dtsi"
11
12 / {
13 model = "Renesas Condor board based on r8a77980";
14 compatible = "renesas,condor", "renesas,r8a77980";
15
16 aliases {
17 serial0 = &scif0;
18 ethernet0 = &gether;
19 };
20
21 chosen {
22 stdout-path = "serial0:115200n8";
23 };
24
25 d1_8v: regulator-2 {
26 compatible = "regulator-fixed";
27 regulator-name = "D1.8V";
28 regulator-min-microvolt = <1800000>;
29 regulator-max-microvolt = <1800000>;
30 regulator-boot-on;
31 regulator-always-on;
32 };
33
34 d3_3v: regulator-0 {
35 compatible = "regulator-fixed";
36 regulator-name = "D3.3V";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 regulator-boot-on;
40 regulator-always-on;
41 };
42
43 hdmi-out {
44 compatible = "hdmi-connector";
45 type = "a";
46
47 port {
48 hdmi_con: endpoint {
49 remote-endpoint = <&adv7511_out>;
50 };
51 };
52 };
53
54 lvds-decoder {
55 compatible = "thine,thc63lvd1024";
56 vcc-supply = <&d3_3v>;
57
58 ports {
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 port@0 {
63 reg = <0>;
64 thc63lvd1024_in: endpoint {
65 remote-endpoint = <&lvds0_out>;
66 };
67 };
68
69 port@2 {
70 reg = <2>;
71 thc63lvd1024_out: endpoint {
72 remote-endpoint = <&adv7511_in>;
73 };
74 };
75 };
76 };
77
78 memory@48000000 {
79 device_type = "memory";
80 /* first 128MB is reserved for secure area. */
81 reg = <0 0x48000000 0 0x78000000>;
82 };
83
84 vddq_vin01: regulator-1 {
85 compatible = "regulator-fixed";
86 regulator-name = "VDDQ_VIN01";
87 regulator-min-microvolt = <1800000>;
88 regulator-max-microvolt = <1800000>;
89 regulator-boot-on;
90 regulator-always-on;
91 };
92
93 x1_clk: x1-clock {
94 compatible = "fixed-clock";
95 #clock-cells = <0>;
96 clock-frequency = <148500000>;
97 };
98 };
99
100 &canfd {
101 pinctrl-0 = <&canfd0_pins>;
102 pinctrl-names = "default";
103 status = "okay";
104
105 channel0 {
106 status = "okay";
107 };
108 };
109
110 &du {
111 clocks = <&cpg CPG_MOD 724>,
112 <&x1_clk>;
113 clock-names = "du.0", "dclkin.0";
114 status = "okay";
115 };
116
117 &extal_clk {
118 clock-frequency = <16666666>;
119 };
120
121 &extalr_clk {
122 clock-frequency = <32768>;
123 };
124
125 &gether {
126 pinctrl-0 = <&gether_pins>;
127 pinctrl-names = "default";
128
129 phy-mode = "rgmii-id";
130 phy-handle = <&phy0>;
131 renesas,no-ether-link;
132 status = "okay";
133
134 phy0: ethernet-phy@0 {
135 rxc-skew-ps = <1500>;
136 reg = <0>;
137 interrupt-parent = <&gpio4>;
138 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
139 };
140 };
141
142 &i2c0 {
143 pinctrl-0 = <&i2c0_pins>;
144 pinctrl-names = "default";
145
146 status = "okay";
147 clock-frequency = <400000>;
148
149 io_expander0: gpio@20 {
150 compatible = "onnn,pca9654";
151 reg = <0x20>;
152 gpio-controller;
153 #gpio-cells = <2>;
154 };
155
156 io_expander1: gpio@21 {
157 compatible = "onnn,pca9654";
158 reg = <0x21>;
159 gpio-controller;
160 #gpio-cells = <2>;
161 };
162
163 hdmi@39 {
164 compatible = "adi,adv7511w";
165 reg = <0x39>;
166 interrupt-parent = <&gpio1>;
167 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
168 avdd-supply = <&d1_8v>;
169 dvdd-supply = <&d1_8v>;
170 pvdd-supply = <&d1_8v>;
171 bgvdd-supply = <&d1_8v>;
172 dvdd-3v-supply = <&d3_3v>;
173
174 adi,input-depth = <8>;
175 adi,input-colorspace = "rgb";
176 adi,input-clock = "1x";
177
178 ports {
179 #address-cells = <1>;
180 #size-cells = <0>;
181
182 port@0 {
183 reg = <0>;
184 adv7511_in: endpoint {
185 remote-endpoint = <&thc63lvd1024_out>;
186 };
187 };
188
189 port@1 {
190 reg = <1>;
191 adv7511_out: endpoint {
192 remote-endpoint = <&hdmi_con>;
193 };
194 };
195 };
196 };
197 };
198
199 &lvds0 {
200 status = "okay";
201
202 ports {
203 port@1 {
204 lvds0_out: endpoint {
205 remote-endpoint = <&thc63lvd1024_in>;
206 };
207 };
208 };
209 };
210
211 &mmc0 {
212 pinctrl-0 = <&mmc_pins>;
213 pinctrl-1 = <&mmc_pins_uhs>;
214 pinctrl-names = "default", "state_uhs";
215
216 vmmc-supply = <&d3_3v>;
217 vqmmc-supply = <&vddq_vin01>;
218 mmc-hs200-1_8v;
219 bus-width = <8>;
220 non-removable;
221 status = "okay";
222 };
223
224 &pciec {
225 status = "okay";
226 };
227
228 &pcie_bus_clk {
229 clock-frequency = <100000000>;
230 };
231
232 &pcie_phy {
233 status = "okay";
234 };
235
236 &pfc {
237 canfd0_pins: canfd0 {
238 groups = "canfd0_data_a";
239 function = "canfd0";
240 };
241
242 gether_pins: gether {
243 groups = "gether_mdio_a", "gether_rgmii",
244 "gether_txcrefclk", "gether_txcrefclk_mega";
245 function = "gether";
246 };
247
248 i2c0_pins: i2c0 {
249 groups = "i2c0";
250 function = "i2c0";
251 };
252
253 mmc_pins: mmc {
254 groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
255 function = "mmc";
256 power-source = <3300>;
257 };
258
259 mmc_pins_uhs: mmc_uhs {
260 groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
261 function = "mmc";
262 power-source = <1800>;
263 };
264
265 scif0_pins: scif0 {
266 groups = "scif0_data";
267 function = "scif0";
268 };
269
270 scif_clk_pins: scif_clk {
271 groups = "scif_clk_b";
272 function = "scif_clk";
273 };
274 };
275
276 &rwdt {
277 timeout-sec = <60>;
278 status = "okay";
279 };
280
281 &scif0 {
282 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
283 pinctrl-names = "default";
284
285 status = "okay";
286 };
287
288 &scif_clk {
289 clock-frequency = <14745600>;
290 };