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io_uring: reset -EBUSY error when io sq thread is waken up
[thirdparty/linux.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15 compatible = "rockchip,rk3399";
16
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 ethernet0 = &gmac;
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
29 i2c6 = &i2c6;
30 i2c7 = &i2c7;
31 i2c8 = &i2c8;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 };
38
39 cpus {
40 #address-cells = <2>;
41 #size-cells = <0>;
42
43 cpu-map {
44 cluster0 {
45 core0 {
46 cpu = <&cpu_l0>;
47 };
48 core1 {
49 cpu = <&cpu_l1>;
50 };
51 core2 {
52 cpu = <&cpu_l2>;
53 };
54 core3 {
55 cpu = <&cpu_l3>;
56 };
57 };
58
59 cluster1 {
60 core0 {
61 cpu = <&cpu_b0>;
62 };
63 core1 {
64 cpu = <&cpu_b1>;
65 };
66 };
67 };
68
69 cpu_l0: cpu@0 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a53";
72 reg = <0x0 0x0>;
73 enable-method = "psci";
74 capacity-dmips-mhz = <485>;
75 clocks = <&cru ARMCLKL>;
76 #cooling-cells = <2>; /* min followed by max */
77 dynamic-power-coefficient = <100>;
78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
79 };
80
81 cpu_l1: cpu@1 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a53";
84 reg = <0x0 0x1>;
85 enable-method = "psci";
86 capacity-dmips-mhz = <485>;
87 clocks = <&cru ARMCLKL>;
88 #cooling-cells = <2>; /* min followed by max */
89 dynamic-power-coefficient = <100>;
90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
91 };
92
93 cpu_l2: cpu@2 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a53";
96 reg = <0x0 0x2>;
97 enable-method = "psci";
98 capacity-dmips-mhz = <485>;
99 clocks = <&cru ARMCLKL>;
100 #cooling-cells = <2>; /* min followed by max */
101 dynamic-power-coefficient = <100>;
102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
103 };
104
105 cpu_l3: cpu@3 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a53";
108 reg = <0x0 0x3>;
109 enable-method = "psci";
110 capacity-dmips-mhz = <485>;
111 clocks = <&cru ARMCLKL>;
112 #cooling-cells = <2>; /* min followed by max */
113 dynamic-power-coefficient = <100>;
114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
115 };
116
117 cpu_b0: cpu@100 {
118 device_type = "cpu";
119 compatible = "arm,cortex-a72";
120 reg = <0x0 0x100>;
121 enable-method = "psci";
122 capacity-dmips-mhz = <1024>;
123 clocks = <&cru ARMCLKB>;
124 #cooling-cells = <2>; /* min followed by max */
125 dynamic-power-coefficient = <436>;
126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
127 };
128
129 cpu_b1: cpu@101 {
130 device_type = "cpu";
131 compatible = "arm,cortex-a72";
132 reg = <0x0 0x101>;
133 enable-method = "psci";
134 capacity-dmips-mhz = <1024>;
135 clocks = <&cru ARMCLKB>;
136 #cooling-cells = <2>; /* min followed by max */
137 dynamic-power-coefficient = <436>;
138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
139 };
140
141 idle-states {
142 entry-method = "psci";
143
144 CPU_SLEEP: cpu-sleep {
145 compatible = "arm,idle-state";
146 local-timer-stop;
147 arm,psci-suspend-param = <0x0010000>;
148 entry-latency-us = <120>;
149 exit-latency-us = <250>;
150 min-residency-us = <900>;
151 };
152
153 CLUSTER_SLEEP: cluster-sleep {
154 compatible = "arm,idle-state";
155 local-timer-stop;
156 arm,psci-suspend-param = <0x1010000>;
157 entry-latency-us = <400>;
158 exit-latency-us = <500>;
159 min-residency-us = <2000>;
160 };
161 };
162 };
163
164 display-subsystem {
165 compatible = "rockchip,display-subsystem";
166 ports = <&vopl_out>, <&vopb_out>;
167 };
168
169 pmu_a53 {
170 compatible = "arm,cortex-a53-pmu";
171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
172 };
173
174 pmu_a72 {
175 compatible = "arm,cortex-a72-pmu";
176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
177 };
178
179 psci {
180 compatible = "arm,psci-1.0";
181 method = "smc";
182 };
183
184 timer {
185 compatible = "arm,armv8-timer";
186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
190 arm,no-tick-in-suspend;
191 };
192
193 xin24m: xin24m {
194 compatible = "fixed-clock";
195 clock-frequency = <24000000>;
196 clock-output-names = "xin24m";
197 #clock-cells = <0>;
198 };
199
200 amba: bus {
201 compatible = "simple-bus";
202 #address-cells = <2>;
203 #size-cells = <2>;
204 ranges;
205
206 dmac_bus: dma-controller@ff6d0000 {
207 compatible = "arm,pl330", "arm,primecell";
208 reg = <0x0 0xff6d0000 0x0 0x4000>;
209 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
210 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
211 #dma-cells = <1>;
212 clocks = <&cru ACLK_DMAC0_PERILP>;
213 clock-names = "apb_pclk";
214 };
215
216 dmac_peri: dma-controller@ff6e0000 {
217 compatible = "arm,pl330", "arm,primecell";
218 reg = <0x0 0xff6e0000 0x0 0x4000>;
219 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
220 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
221 #dma-cells = <1>;
222 clocks = <&cru ACLK_DMAC1_PERILP>;
223 clock-names = "apb_pclk";
224 };
225 };
226
227 pcie0: pcie@f8000000 {
228 compatible = "rockchip,rk3399-pcie";
229 reg = <0x0 0xf8000000 0x0 0x2000000>,
230 <0x0 0xfd000000 0x0 0x1000000>;
231 reg-names = "axi-base", "apb-base";
232 #address-cells = <3>;
233 #size-cells = <2>;
234 #interrupt-cells = <1>;
235 aspm-no-l0s;
236 bus-range = <0x0 0x1f>;
237 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
238 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
239 clock-names = "aclk", "aclk-perf",
240 "hclk", "pm";
241 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
242 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
243 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
244 interrupt-names = "sys", "legacy", "client";
245 interrupt-map-mask = <0 0 0 7>;
246 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
247 <0 0 0 2 &pcie0_intc 1>,
248 <0 0 0 3 &pcie0_intc 2>,
249 <0 0 0 4 &pcie0_intc 3>;
250 linux,pci-domain = <0>;
251 max-link-speed = <1>;
252 msi-map = <0x0 &its 0x0 0x1000>;
253 phys = <&pcie_phy 0>, <&pcie_phy 1>,
254 <&pcie_phy 2>, <&pcie_phy 3>;
255 phy-names = "pcie-phy-0", "pcie-phy-1",
256 "pcie-phy-2", "pcie-phy-3";
257 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
258 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
259 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
260 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
261 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
262 <&cru SRST_A_PCIE>;
263 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
264 "pm", "pclk", "aclk";
265 status = "disabled";
266
267 pcie0_intc: interrupt-controller {
268 interrupt-controller;
269 #address-cells = <0>;
270 #interrupt-cells = <1>;
271 };
272 };
273
274 gmac: ethernet@fe300000 {
275 compatible = "rockchip,rk3399-gmac";
276 reg = <0x0 0xfe300000 0x0 0x10000>;
277 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
278 interrupt-names = "macirq";
279 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
280 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
281 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
282 <&cru PCLK_GMAC>;
283 clock-names = "stmmaceth", "mac_clk_rx",
284 "mac_clk_tx", "clk_mac_ref",
285 "clk_mac_refout", "aclk_mac",
286 "pclk_mac";
287 power-domains = <&power RK3399_PD_GMAC>;
288 resets = <&cru SRST_A_GMAC>;
289 reset-names = "stmmaceth";
290 rockchip,grf = <&grf>;
291 snps,txpbl = <0x4>;
292 status = "disabled";
293 };
294
295 sdio0: mmc@fe310000 {
296 compatible = "rockchip,rk3399-dw-mshc",
297 "rockchip,rk3288-dw-mshc";
298 reg = <0x0 0xfe310000 0x0 0x4000>;
299 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
300 max-frequency = <150000000>;
301 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
302 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
303 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
304 fifo-depth = <0x100>;
305 power-domains = <&power RK3399_PD_SDIOAUDIO>;
306 resets = <&cru SRST_SDIO0>;
307 reset-names = "reset";
308 status = "disabled";
309 };
310
311 sdmmc: mmc@fe320000 {
312 compatible = "rockchip,rk3399-dw-mshc",
313 "rockchip,rk3288-dw-mshc";
314 reg = <0x0 0xfe320000 0x0 0x4000>;
315 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
316 max-frequency = <150000000>;
317 assigned-clocks = <&cru HCLK_SD>;
318 assigned-clock-rates = <200000000>;
319 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
320 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
321 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
322 fifo-depth = <0x100>;
323 power-domains = <&power RK3399_PD_SD>;
324 resets = <&cru SRST_SDMMC>;
325 reset-names = "reset";
326 status = "disabled";
327 };
328
329 sdhci: sdhci@fe330000 {
330 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
331 reg = <0x0 0xfe330000 0x0 0x10000>;
332 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
333 arasan,soc-ctl-syscon = <&grf>;
334 assigned-clocks = <&cru SCLK_EMMC>;
335 assigned-clock-rates = <200000000>;
336 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
337 clock-names = "clk_xin", "clk_ahb";
338 clock-output-names = "emmc_cardclock";
339 #clock-cells = <0>;
340 phys = <&emmc_phy>;
341 phy-names = "phy_arasan";
342 power-domains = <&power RK3399_PD_EMMC>;
343 disable-cqe-dcmd;
344 status = "disabled";
345 };
346
347 usb_host0_ehci: usb@fe380000 {
348 compatible = "generic-ehci";
349 reg = <0x0 0xfe380000 0x0 0x20000>;
350 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
351 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
352 <&u2phy0>;
353 phys = <&u2phy0_host>;
354 phy-names = "usb";
355 status = "disabled";
356 };
357
358 usb_host0_ohci: usb@fe3a0000 {
359 compatible = "generic-ohci";
360 reg = <0x0 0xfe3a0000 0x0 0x20000>;
361 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
362 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
363 <&u2phy0>;
364 phys = <&u2phy0_host>;
365 phy-names = "usb";
366 status = "disabled";
367 };
368
369 usb_host1_ehci: usb@fe3c0000 {
370 compatible = "generic-ehci";
371 reg = <0x0 0xfe3c0000 0x0 0x20000>;
372 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
373 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
374 <&u2phy1>;
375 phys = <&u2phy1_host>;
376 phy-names = "usb";
377 status = "disabled";
378 };
379
380 usb_host1_ohci: usb@fe3e0000 {
381 compatible = "generic-ohci";
382 reg = <0x0 0xfe3e0000 0x0 0x20000>;
383 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
384 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
385 <&u2phy1>;
386 phys = <&u2phy1_host>;
387 phy-names = "usb";
388 status = "disabled";
389 };
390
391 usbdrd3_0: usb@fe800000 {
392 compatible = "rockchip,rk3399-dwc3";
393 #address-cells = <2>;
394 #size-cells = <2>;
395 ranges;
396 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
397 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
398 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
399 clock-names = "ref_clk", "suspend_clk",
400 "bus_clk", "aclk_usb3_rksoc_axi_perf",
401 "aclk_usb3", "grf_clk";
402 resets = <&cru SRST_A_USB3_OTG0>;
403 reset-names = "usb3-otg";
404 status = "disabled";
405
406 usbdrd_dwc3_0: dwc3 {
407 compatible = "snps,dwc3";
408 reg = <0x0 0xfe800000 0x0 0x100000>;
409 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
410 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
411 <&cru SCLK_USB3OTG0_SUSPEND>;
412 clock-names = "ref", "bus_early", "suspend";
413 dr_mode = "otg";
414 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
415 phy-names = "usb2-phy", "usb3-phy";
416 phy_type = "utmi_wide";
417 snps,dis_enblslpm_quirk;
418 snps,dis-u2-freeclk-exists-quirk;
419 snps,dis_u2_susphy_quirk;
420 snps,dis-del-phy-power-chg-quirk;
421 snps,dis-tx-ipgap-linecheck-quirk;
422 power-domains = <&power RK3399_PD_USB3>;
423 status = "disabled";
424 };
425 };
426
427 usbdrd3_1: usb@fe900000 {
428 compatible = "rockchip,rk3399-dwc3";
429 #address-cells = <2>;
430 #size-cells = <2>;
431 ranges;
432 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
433 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
434 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
435 clock-names = "ref_clk", "suspend_clk",
436 "bus_clk", "aclk_usb3_rksoc_axi_perf",
437 "aclk_usb3", "grf_clk";
438 resets = <&cru SRST_A_USB3_OTG1>;
439 reset-names = "usb3-otg";
440 status = "disabled";
441
442 usbdrd_dwc3_1: dwc3 {
443 compatible = "snps,dwc3";
444 reg = <0x0 0xfe900000 0x0 0x100000>;
445 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
446 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
447 <&cru SCLK_USB3OTG1_SUSPEND>;
448 clock-names = "ref", "bus_early", "suspend";
449 dr_mode = "otg";
450 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
451 phy-names = "usb2-phy", "usb3-phy";
452 phy_type = "utmi_wide";
453 snps,dis_enblslpm_quirk;
454 snps,dis-u2-freeclk-exists-quirk;
455 snps,dis_u2_susphy_quirk;
456 snps,dis-del-phy-power-chg-quirk;
457 snps,dis-tx-ipgap-linecheck-quirk;
458 power-domains = <&power RK3399_PD_USB3>;
459 status = "disabled";
460 };
461 };
462
463 cdn_dp: dp@fec00000 {
464 compatible = "rockchip,rk3399-cdn-dp";
465 reg = <0x0 0xfec00000 0x0 0x100000>;
466 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
467 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
468 assigned-clock-rates = <100000000>, <200000000>;
469 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
470 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
471 clock-names = "core-clk", "pclk", "spdif", "grf";
472 phys = <&tcphy0_dp>, <&tcphy1_dp>;
473 power-domains = <&power RK3399_PD_HDCP>;
474 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
475 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
476 reset-names = "spdif", "dptx", "apb", "core";
477 rockchip,grf = <&grf>;
478 #sound-dai-cells = <1>;
479 status = "disabled";
480
481 ports {
482 dp_in: port {
483 #address-cells = <1>;
484 #size-cells = <0>;
485
486 dp_in_vopb: endpoint@0 {
487 reg = <0>;
488 remote-endpoint = <&vopb_out_dp>;
489 };
490
491 dp_in_vopl: endpoint@1 {
492 reg = <1>;
493 remote-endpoint = <&vopl_out_dp>;
494 };
495 };
496 };
497 };
498
499 gic: interrupt-controller@fee00000 {
500 compatible = "arm,gic-v3";
501 #interrupt-cells = <4>;
502 #address-cells = <2>;
503 #size-cells = <2>;
504 ranges;
505 interrupt-controller;
506
507 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
508 <0x0 0xfef00000 0 0xc0000>, /* GICR */
509 <0x0 0xfff00000 0 0x10000>, /* GICC */
510 <0x0 0xfff10000 0 0x10000>, /* GICH */
511 <0x0 0xfff20000 0 0x10000>; /* GICV */
512 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
513 its: interrupt-controller@fee20000 {
514 compatible = "arm,gic-v3-its";
515 msi-controller;
516 #msi-cells = <1>;
517 reg = <0x0 0xfee20000 0x0 0x20000>;
518 };
519
520 ppi-partitions {
521 ppi_cluster0: interrupt-partition-0 {
522 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
523 };
524
525 ppi_cluster1: interrupt-partition-1 {
526 affinity = <&cpu_b0 &cpu_b1>;
527 };
528 };
529 };
530
531 saradc: saradc@ff100000 {
532 compatible = "rockchip,rk3399-saradc";
533 reg = <0x0 0xff100000 0x0 0x100>;
534 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
535 #io-channel-cells = <1>;
536 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
537 clock-names = "saradc", "apb_pclk";
538 resets = <&cru SRST_P_SARADC>;
539 reset-names = "saradc-apb";
540 status = "disabled";
541 };
542
543 i2c1: i2c@ff110000 {
544 compatible = "rockchip,rk3399-i2c";
545 reg = <0x0 0xff110000 0x0 0x1000>;
546 assigned-clocks = <&cru SCLK_I2C1>;
547 assigned-clock-rates = <200000000>;
548 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
549 clock-names = "i2c", "pclk";
550 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&i2c1_xfer>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 status = "disabled";
556 };
557
558 i2c2: i2c@ff120000 {
559 compatible = "rockchip,rk3399-i2c";
560 reg = <0x0 0xff120000 0x0 0x1000>;
561 assigned-clocks = <&cru SCLK_I2C2>;
562 assigned-clock-rates = <200000000>;
563 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
564 clock-names = "i2c", "pclk";
565 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c2_xfer>;
568 #address-cells = <1>;
569 #size-cells = <0>;
570 status = "disabled";
571 };
572
573 i2c3: i2c@ff130000 {
574 compatible = "rockchip,rk3399-i2c";
575 reg = <0x0 0xff130000 0x0 0x1000>;
576 assigned-clocks = <&cru SCLK_I2C3>;
577 assigned-clock-rates = <200000000>;
578 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
579 clock-names = "i2c", "pclk";
580 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&i2c3_xfer>;
583 #address-cells = <1>;
584 #size-cells = <0>;
585 status = "disabled";
586 };
587
588 i2c5: i2c@ff140000 {
589 compatible = "rockchip,rk3399-i2c";
590 reg = <0x0 0xff140000 0x0 0x1000>;
591 assigned-clocks = <&cru SCLK_I2C5>;
592 assigned-clock-rates = <200000000>;
593 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
594 clock-names = "i2c", "pclk";
595 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&i2c5_xfer>;
598 #address-cells = <1>;
599 #size-cells = <0>;
600 status = "disabled";
601 };
602
603 i2c6: i2c@ff150000 {
604 compatible = "rockchip,rk3399-i2c";
605 reg = <0x0 0xff150000 0x0 0x1000>;
606 assigned-clocks = <&cru SCLK_I2C6>;
607 assigned-clock-rates = <200000000>;
608 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
609 clock-names = "i2c", "pclk";
610 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
611 pinctrl-names = "default";
612 pinctrl-0 = <&i2c6_xfer>;
613 #address-cells = <1>;
614 #size-cells = <0>;
615 status = "disabled";
616 };
617
618 i2c7: i2c@ff160000 {
619 compatible = "rockchip,rk3399-i2c";
620 reg = <0x0 0xff160000 0x0 0x1000>;
621 assigned-clocks = <&cru SCLK_I2C7>;
622 assigned-clock-rates = <200000000>;
623 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
624 clock-names = "i2c", "pclk";
625 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&i2c7_xfer>;
628 #address-cells = <1>;
629 #size-cells = <0>;
630 status = "disabled";
631 };
632
633 uart0: serial@ff180000 {
634 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
635 reg = <0x0 0xff180000 0x0 0x100>;
636 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
637 clock-names = "baudclk", "apb_pclk";
638 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
639 reg-shift = <2>;
640 reg-io-width = <4>;
641 pinctrl-names = "default";
642 pinctrl-0 = <&uart0_xfer>;
643 status = "disabled";
644 };
645
646 uart1: serial@ff190000 {
647 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
648 reg = <0x0 0xff190000 0x0 0x100>;
649 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
650 clock-names = "baudclk", "apb_pclk";
651 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
652 reg-shift = <2>;
653 reg-io-width = <4>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&uart1_xfer>;
656 status = "disabled";
657 };
658
659 uart2: serial@ff1a0000 {
660 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
661 reg = <0x0 0xff1a0000 0x0 0x100>;
662 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
663 clock-names = "baudclk", "apb_pclk";
664 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
665 reg-shift = <2>;
666 reg-io-width = <4>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&uart2c_xfer>;
669 status = "disabled";
670 };
671
672 uart3: serial@ff1b0000 {
673 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
674 reg = <0x0 0xff1b0000 0x0 0x100>;
675 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
676 clock-names = "baudclk", "apb_pclk";
677 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
678 reg-shift = <2>;
679 reg-io-width = <4>;
680 pinctrl-names = "default";
681 pinctrl-0 = <&uart3_xfer>;
682 status = "disabled";
683 };
684
685 spi0: spi@ff1c0000 {
686 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
687 reg = <0x0 0xff1c0000 0x0 0x1000>;
688 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
689 clock-names = "spiclk", "apb_pclk";
690 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
691 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
692 dma-names = "tx", "rx";
693 pinctrl-names = "default";
694 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
695 #address-cells = <1>;
696 #size-cells = <0>;
697 status = "disabled";
698 };
699
700 spi1: spi@ff1d0000 {
701 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
702 reg = <0x0 0xff1d0000 0x0 0x1000>;
703 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
704 clock-names = "spiclk", "apb_pclk";
705 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
706 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
707 dma-names = "tx", "rx";
708 pinctrl-names = "default";
709 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
710 #address-cells = <1>;
711 #size-cells = <0>;
712 status = "disabled";
713 };
714
715 spi2: spi@ff1e0000 {
716 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
717 reg = <0x0 0xff1e0000 0x0 0x1000>;
718 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
719 clock-names = "spiclk", "apb_pclk";
720 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
721 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
722 dma-names = "tx", "rx";
723 pinctrl-names = "default";
724 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
725 #address-cells = <1>;
726 #size-cells = <0>;
727 status = "disabled";
728 };
729
730 spi4: spi@ff1f0000 {
731 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
732 reg = <0x0 0xff1f0000 0x0 0x1000>;
733 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
734 clock-names = "spiclk", "apb_pclk";
735 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
736 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
737 dma-names = "tx", "rx";
738 pinctrl-names = "default";
739 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
740 #address-cells = <1>;
741 #size-cells = <0>;
742 status = "disabled";
743 };
744
745 spi5: spi@ff200000 {
746 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
747 reg = <0x0 0xff200000 0x0 0x1000>;
748 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
749 clock-names = "spiclk", "apb_pclk";
750 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
751 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
752 dma-names = "tx", "rx";
753 pinctrl-names = "default";
754 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
755 power-domains = <&power RK3399_PD_SDIOAUDIO>;
756 #address-cells = <1>;
757 #size-cells = <0>;
758 status = "disabled";
759 };
760
761 thermal_zones: thermal-zones {
762 cpu_thermal: cpu {
763 polling-delay-passive = <100>;
764 polling-delay = <1000>;
765
766 thermal-sensors = <&tsadc 0>;
767
768 trips {
769 cpu_alert0: cpu_alert0 {
770 temperature = <70000>;
771 hysteresis = <2000>;
772 type = "passive";
773 };
774 cpu_alert1: cpu_alert1 {
775 temperature = <75000>;
776 hysteresis = <2000>;
777 type = "passive";
778 };
779 cpu_crit: cpu_crit {
780 temperature = <95000>;
781 hysteresis = <2000>;
782 type = "critical";
783 };
784 };
785
786 cooling-maps {
787 map0 {
788 trip = <&cpu_alert0>;
789 cooling-device =
790 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
791 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
792 };
793 map1 {
794 trip = <&cpu_alert1>;
795 cooling-device =
796 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
797 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
798 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
799 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
800 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
801 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
802 };
803 };
804 };
805
806 gpu_thermal: gpu {
807 polling-delay-passive = <100>;
808 polling-delay = <1000>;
809
810 thermal-sensors = <&tsadc 1>;
811
812 trips {
813 gpu_alert0: gpu_alert0 {
814 temperature = <75000>;
815 hysteresis = <2000>;
816 type = "passive";
817 };
818 gpu_crit: gpu_crit {
819 temperature = <95000>;
820 hysteresis = <2000>;
821 type = "critical";
822 };
823 };
824
825 cooling-maps {
826 map0 {
827 trip = <&gpu_alert0>;
828 cooling-device =
829 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
830 };
831 };
832 };
833 };
834
835 tsadc: tsadc@ff260000 {
836 compatible = "rockchip,rk3399-tsadc";
837 reg = <0x0 0xff260000 0x0 0x100>;
838 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
839 assigned-clocks = <&cru SCLK_TSADC>;
840 assigned-clock-rates = <750000>;
841 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
842 clock-names = "tsadc", "apb_pclk";
843 resets = <&cru SRST_TSADC>;
844 reset-names = "tsadc-apb";
845 rockchip,grf = <&grf>;
846 rockchip,hw-tshut-temp = <95000>;
847 pinctrl-names = "init", "default", "sleep";
848 pinctrl-0 = <&otp_gpio>;
849 pinctrl-1 = <&otp_out>;
850 pinctrl-2 = <&otp_gpio>;
851 #thermal-sensor-cells = <1>;
852 status = "disabled";
853 };
854
855 qos_emmc: qos@ffa58000 {
856 compatible = "syscon";
857 reg = <0x0 0xffa58000 0x0 0x20>;
858 };
859
860 qos_gmac: qos@ffa5c000 {
861 compatible = "syscon";
862 reg = <0x0 0xffa5c000 0x0 0x20>;
863 };
864
865 qos_pcie: qos@ffa60080 {
866 compatible = "syscon";
867 reg = <0x0 0xffa60080 0x0 0x20>;
868 };
869
870 qos_usb_host0: qos@ffa60100 {
871 compatible = "syscon";
872 reg = <0x0 0xffa60100 0x0 0x20>;
873 };
874
875 qos_usb_host1: qos@ffa60180 {
876 compatible = "syscon";
877 reg = <0x0 0xffa60180 0x0 0x20>;
878 };
879
880 qos_usb_otg0: qos@ffa70000 {
881 compatible = "syscon";
882 reg = <0x0 0xffa70000 0x0 0x20>;
883 };
884
885 qos_usb_otg1: qos@ffa70080 {
886 compatible = "syscon";
887 reg = <0x0 0xffa70080 0x0 0x20>;
888 };
889
890 qos_sd: qos@ffa74000 {
891 compatible = "syscon";
892 reg = <0x0 0xffa74000 0x0 0x20>;
893 };
894
895 qos_sdioaudio: qos@ffa76000 {
896 compatible = "syscon";
897 reg = <0x0 0xffa76000 0x0 0x20>;
898 };
899
900 qos_hdcp: qos@ffa90000 {
901 compatible = "syscon";
902 reg = <0x0 0xffa90000 0x0 0x20>;
903 };
904
905 qos_iep: qos@ffa98000 {
906 compatible = "syscon";
907 reg = <0x0 0xffa98000 0x0 0x20>;
908 };
909
910 qos_isp0_m0: qos@ffaa0000 {
911 compatible = "syscon";
912 reg = <0x0 0xffaa0000 0x0 0x20>;
913 };
914
915 qos_isp0_m1: qos@ffaa0080 {
916 compatible = "syscon";
917 reg = <0x0 0xffaa0080 0x0 0x20>;
918 };
919
920 qos_isp1_m0: qos@ffaa8000 {
921 compatible = "syscon";
922 reg = <0x0 0xffaa8000 0x0 0x20>;
923 };
924
925 qos_isp1_m1: qos@ffaa8080 {
926 compatible = "syscon";
927 reg = <0x0 0xffaa8080 0x0 0x20>;
928 };
929
930 qos_rga_r: qos@ffab0000 {
931 compatible = "syscon";
932 reg = <0x0 0xffab0000 0x0 0x20>;
933 };
934
935 qos_rga_w: qos@ffab0080 {
936 compatible = "syscon";
937 reg = <0x0 0xffab0080 0x0 0x20>;
938 };
939
940 qos_video_m0: qos@ffab8000 {
941 compatible = "syscon";
942 reg = <0x0 0xffab8000 0x0 0x20>;
943 };
944
945 qos_video_m1_r: qos@ffac0000 {
946 compatible = "syscon";
947 reg = <0x0 0xffac0000 0x0 0x20>;
948 };
949
950 qos_video_m1_w: qos@ffac0080 {
951 compatible = "syscon";
952 reg = <0x0 0xffac0080 0x0 0x20>;
953 };
954
955 qos_vop_big_r: qos@ffac8000 {
956 compatible = "syscon";
957 reg = <0x0 0xffac8000 0x0 0x20>;
958 };
959
960 qos_vop_big_w: qos@ffac8080 {
961 compatible = "syscon";
962 reg = <0x0 0xffac8080 0x0 0x20>;
963 };
964
965 qos_vop_little: qos@ffad0000 {
966 compatible = "syscon";
967 reg = <0x0 0xffad0000 0x0 0x20>;
968 };
969
970 qos_perihp: qos@ffad8080 {
971 compatible = "syscon";
972 reg = <0x0 0xffad8080 0x0 0x20>;
973 };
974
975 qos_gpu: qos@ffae0000 {
976 compatible = "syscon";
977 reg = <0x0 0xffae0000 0x0 0x20>;
978 };
979
980 pmu: power-management@ff310000 {
981 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
982 reg = <0x0 0xff310000 0x0 0x1000>;
983
984 /*
985 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
986 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
987 * Some of the power domains are grouped together for every
988 * voltage domain.
989 * The detail contents as below.
990 */
991 power: power-controller {
992 compatible = "rockchip,rk3399-power-controller";
993 #power-domain-cells = <1>;
994 #address-cells = <1>;
995 #size-cells = <0>;
996
997 /* These power domains are grouped by VD_CENTER */
998 pd_iep@RK3399_PD_IEP {
999 reg = <RK3399_PD_IEP>;
1000 clocks = <&cru ACLK_IEP>,
1001 <&cru HCLK_IEP>;
1002 pm_qos = <&qos_iep>;
1003 };
1004 pd_rga@RK3399_PD_RGA {
1005 reg = <RK3399_PD_RGA>;
1006 clocks = <&cru ACLK_RGA>,
1007 <&cru HCLK_RGA>;
1008 pm_qos = <&qos_rga_r>,
1009 <&qos_rga_w>;
1010 };
1011 pd_vcodec@RK3399_PD_VCODEC {
1012 reg = <RK3399_PD_VCODEC>;
1013 clocks = <&cru ACLK_VCODEC>,
1014 <&cru HCLK_VCODEC>;
1015 pm_qos = <&qos_video_m0>;
1016 };
1017 pd_vdu@RK3399_PD_VDU {
1018 reg = <RK3399_PD_VDU>;
1019 clocks = <&cru ACLK_VDU>,
1020 <&cru HCLK_VDU>;
1021 pm_qos = <&qos_video_m1_r>,
1022 <&qos_video_m1_w>;
1023 };
1024
1025 /* These power domains are grouped by VD_GPU */
1026 pd_gpu@RK3399_PD_GPU {
1027 reg = <RK3399_PD_GPU>;
1028 clocks = <&cru ACLK_GPU>;
1029 pm_qos = <&qos_gpu>;
1030 };
1031
1032 /* These power domains are grouped by VD_LOGIC */
1033 pd_edp@RK3399_PD_EDP {
1034 reg = <RK3399_PD_EDP>;
1035 clocks = <&cru PCLK_EDP_CTRL>;
1036 };
1037 pd_emmc@RK3399_PD_EMMC {
1038 reg = <RK3399_PD_EMMC>;
1039 clocks = <&cru ACLK_EMMC>;
1040 pm_qos = <&qos_emmc>;
1041 };
1042 pd_gmac@RK3399_PD_GMAC {
1043 reg = <RK3399_PD_GMAC>;
1044 clocks = <&cru ACLK_GMAC>,
1045 <&cru PCLK_GMAC>;
1046 pm_qos = <&qos_gmac>;
1047 };
1048 pd_sd@RK3399_PD_SD {
1049 reg = <RK3399_PD_SD>;
1050 clocks = <&cru HCLK_SDMMC>,
1051 <&cru SCLK_SDMMC>;
1052 pm_qos = <&qos_sd>;
1053 };
1054 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1055 reg = <RK3399_PD_SDIOAUDIO>;
1056 clocks = <&cru HCLK_SDIO>;
1057 pm_qos = <&qos_sdioaudio>;
1058 };
1059 pd_usb3@RK3399_PD_USB3 {
1060 reg = <RK3399_PD_USB3>;
1061 clocks = <&cru ACLK_USB3>;
1062 pm_qos = <&qos_usb_otg0>,
1063 <&qos_usb_otg1>;
1064 };
1065 pd_vio@RK3399_PD_VIO {
1066 reg = <RK3399_PD_VIO>;
1067 #address-cells = <1>;
1068 #size-cells = <0>;
1069
1070 pd_hdcp@RK3399_PD_HDCP {
1071 reg = <RK3399_PD_HDCP>;
1072 clocks = <&cru ACLK_HDCP>,
1073 <&cru HCLK_HDCP>,
1074 <&cru PCLK_HDCP>;
1075 pm_qos = <&qos_hdcp>;
1076 };
1077 pd_isp0@RK3399_PD_ISP0 {
1078 reg = <RK3399_PD_ISP0>;
1079 clocks = <&cru ACLK_ISP0>,
1080 <&cru HCLK_ISP0>;
1081 pm_qos = <&qos_isp0_m0>,
1082 <&qos_isp0_m1>;
1083 };
1084 pd_isp1@RK3399_PD_ISP1 {
1085 reg = <RK3399_PD_ISP1>;
1086 clocks = <&cru ACLK_ISP1>,
1087 <&cru HCLK_ISP1>;
1088 pm_qos = <&qos_isp1_m0>,
1089 <&qos_isp1_m1>;
1090 };
1091 pd_tcpc0@RK3399_PD_TCPC0 {
1092 reg = <RK3399_PD_TCPD0>;
1093 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1094 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1095 };
1096 pd_tcpc1@RK3399_PD_TCPC1 {
1097 reg = <RK3399_PD_TCPD1>;
1098 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1099 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1100 };
1101 pd_vo@RK3399_PD_VO {
1102 reg = <RK3399_PD_VO>;
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1105
1106 pd_vopb@RK3399_PD_VOPB {
1107 reg = <RK3399_PD_VOPB>;
1108 clocks = <&cru ACLK_VOP0>,
1109 <&cru HCLK_VOP0>;
1110 pm_qos = <&qos_vop_big_r>,
1111 <&qos_vop_big_w>;
1112 };
1113 pd_vopl@RK3399_PD_VOPL {
1114 reg = <RK3399_PD_VOPL>;
1115 clocks = <&cru ACLK_VOP1>,
1116 <&cru HCLK_VOP1>;
1117 pm_qos = <&qos_vop_little>;
1118 };
1119 };
1120 };
1121 };
1122 };
1123
1124 pmugrf: syscon@ff320000 {
1125 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1126 reg = <0x0 0xff320000 0x0 0x1000>;
1127 #address-cells = <1>;
1128 #size-cells = <1>;
1129
1130 pmu_io_domains: io-domains {
1131 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1132 status = "disabled";
1133 };
1134 };
1135
1136 spi3: spi@ff350000 {
1137 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1138 reg = <0x0 0xff350000 0x0 0x1000>;
1139 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1140 clock-names = "spiclk", "apb_pclk";
1141 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1142 pinctrl-names = "default";
1143 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1146 status = "disabled";
1147 };
1148
1149 uart4: serial@ff370000 {
1150 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1151 reg = <0x0 0xff370000 0x0 0x100>;
1152 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1153 clock-names = "baudclk", "apb_pclk";
1154 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1155 reg-shift = <2>;
1156 reg-io-width = <4>;
1157 pinctrl-names = "default";
1158 pinctrl-0 = <&uart4_xfer>;
1159 status = "disabled";
1160 };
1161
1162 i2c0: i2c@ff3c0000 {
1163 compatible = "rockchip,rk3399-i2c";
1164 reg = <0x0 0xff3c0000 0x0 0x1000>;
1165 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1166 assigned-clock-rates = <200000000>;
1167 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1168 clock-names = "i2c", "pclk";
1169 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1170 pinctrl-names = "default";
1171 pinctrl-0 = <&i2c0_xfer>;
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1174 status = "disabled";
1175 };
1176
1177 i2c4: i2c@ff3d0000 {
1178 compatible = "rockchip,rk3399-i2c";
1179 reg = <0x0 0xff3d0000 0x0 0x1000>;
1180 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1181 assigned-clock-rates = <200000000>;
1182 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1183 clock-names = "i2c", "pclk";
1184 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1185 pinctrl-names = "default";
1186 pinctrl-0 = <&i2c4_xfer>;
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1189 status = "disabled";
1190 };
1191
1192 i2c8: i2c@ff3e0000 {
1193 compatible = "rockchip,rk3399-i2c";
1194 reg = <0x0 0xff3e0000 0x0 0x1000>;
1195 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1196 assigned-clock-rates = <200000000>;
1197 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1198 clock-names = "i2c", "pclk";
1199 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1200 pinctrl-names = "default";
1201 pinctrl-0 = <&i2c8_xfer>;
1202 #address-cells = <1>;
1203 #size-cells = <0>;
1204 status = "disabled";
1205 };
1206
1207 pwm0: pwm@ff420000 {
1208 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1209 reg = <0x0 0xff420000 0x0 0x10>;
1210 #pwm-cells = <3>;
1211 pinctrl-names = "default";
1212 pinctrl-0 = <&pwm0_pin>;
1213 clocks = <&pmucru PCLK_RKPWM_PMU>;
1214 clock-names = "pwm";
1215 status = "disabled";
1216 };
1217
1218 pwm1: pwm@ff420010 {
1219 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1220 reg = <0x0 0xff420010 0x0 0x10>;
1221 #pwm-cells = <3>;
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&pwm1_pin>;
1224 clocks = <&pmucru PCLK_RKPWM_PMU>;
1225 clock-names = "pwm";
1226 status = "disabled";
1227 };
1228
1229 pwm2: pwm@ff420020 {
1230 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1231 reg = <0x0 0xff420020 0x0 0x10>;
1232 #pwm-cells = <3>;
1233 pinctrl-names = "default";
1234 pinctrl-0 = <&pwm2_pin>;
1235 clocks = <&pmucru PCLK_RKPWM_PMU>;
1236 clock-names = "pwm";
1237 status = "disabled";
1238 };
1239
1240 pwm3: pwm@ff420030 {
1241 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1242 reg = <0x0 0xff420030 0x0 0x10>;
1243 #pwm-cells = <3>;
1244 pinctrl-names = "default";
1245 pinctrl-0 = <&pwm3a_pin>;
1246 clocks = <&pmucru PCLK_RKPWM_PMU>;
1247 clock-names = "pwm";
1248 status = "disabled";
1249 };
1250
1251 vpu: video-codec@ff650000 {
1252 compatible = "rockchip,rk3399-vpu";
1253 reg = <0x0 0xff650000 0x0 0x800>;
1254 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1255 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1256 interrupt-names = "vepu", "vdpu";
1257 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1258 clock-names = "aclk", "hclk";
1259 iommus = <&vpu_mmu>;
1260 power-domains = <&power RK3399_PD_VCODEC>;
1261 };
1262
1263 vpu_mmu: iommu@ff650800 {
1264 compatible = "rockchip,iommu";
1265 reg = <0x0 0xff650800 0x0 0x40>;
1266 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1267 interrupt-names = "vpu_mmu";
1268 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1269 clock-names = "aclk", "iface";
1270 #iommu-cells = <0>;
1271 power-domains = <&power RK3399_PD_VCODEC>;
1272 };
1273
1274 vdec_mmu: iommu@ff660480 {
1275 compatible = "rockchip,iommu";
1276 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1277 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1278 interrupt-names = "vdec_mmu";
1279 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1280 clock-names = "aclk", "iface";
1281 #iommu-cells = <0>;
1282 status = "disabled";
1283 };
1284
1285 iep_mmu: iommu@ff670800 {
1286 compatible = "rockchip,iommu";
1287 reg = <0x0 0xff670800 0x0 0x40>;
1288 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1289 interrupt-names = "iep_mmu";
1290 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1291 clock-names = "aclk", "iface";
1292 #iommu-cells = <0>;
1293 status = "disabled";
1294 };
1295
1296 rga: rga@ff680000 {
1297 compatible = "rockchip,rk3399-rga";
1298 reg = <0x0 0xff680000 0x0 0x10000>;
1299 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1300 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1301 clock-names = "aclk", "hclk", "sclk";
1302 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1303 reset-names = "core", "axi", "ahb";
1304 power-domains = <&power RK3399_PD_RGA>;
1305 };
1306
1307 efuse0: efuse@ff690000 {
1308 compatible = "rockchip,rk3399-efuse";
1309 reg = <0x0 0xff690000 0x0 0x80>;
1310 #address-cells = <1>;
1311 #size-cells = <1>;
1312 clocks = <&cru PCLK_EFUSE1024NS>;
1313 clock-names = "pclk_efuse";
1314
1315 /* Data cells */
1316 cpu_id: cpu-id@7 {
1317 reg = <0x07 0x10>;
1318 };
1319 cpub_leakage: cpu-leakage@17 {
1320 reg = <0x17 0x1>;
1321 };
1322 gpu_leakage: gpu-leakage@18 {
1323 reg = <0x18 0x1>;
1324 };
1325 center_leakage: center-leakage@19 {
1326 reg = <0x19 0x1>;
1327 };
1328 cpul_leakage: cpu-leakage@1a {
1329 reg = <0x1a 0x1>;
1330 };
1331 logic_leakage: logic-leakage@1b {
1332 reg = <0x1b 0x1>;
1333 };
1334 wafer_info: wafer-info@1c {
1335 reg = <0x1c 0x1>;
1336 };
1337 };
1338
1339 pmucru: pmu-clock-controller@ff750000 {
1340 compatible = "rockchip,rk3399-pmucru";
1341 reg = <0x0 0xff750000 0x0 0x1000>;
1342 rockchip,grf = <&pmugrf>;
1343 #clock-cells = <1>;
1344 #reset-cells = <1>;
1345 assigned-clocks = <&pmucru PLL_PPLL>;
1346 assigned-clock-rates = <676000000>;
1347 };
1348
1349 cru: clock-controller@ff760000 {
1350 compatible = "rockchip,rk3399-cru";
1351 reg = <0x0 0xff760000 0x0 0x1000>;
1352 rockchip,grf = <&grf>;
1353 #clock-cells = <1>;
1354 #reset-cells = <1>;
1355 assigned-clocks =
1356 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1357 <&cru PLL_NPLL>,
1358 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1359 <&cru PCLK_PERIHP>,
1360 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1361 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1362 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1363 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1364 <&cru ACLK_GIC_PRE>,
1365 <&cru PCLK_DDR>;
1366 assigned-clock-rates =
1367 <594000000>, <800000000>,
1368 <1000000000>,
1369 <150000000>, <75000000>,
1370 <37500000>,
1371 <100000000>, <100000000>,
1372 <50000000>, <600000000>,
1373 <100000000>, <50000000>,
1374 <400000000>, <400000000>,
1375 <200000000>,
1376 <200000000>;
1377 };
1378
1379 grf: syscon@ff770000 {
1380 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1381 reg = <0x0 0xff770000 0x0 0x10000>;
1382 #address-cells = <1>;
1383 #size-cells = <1>;
1384
1385 io_domains: io-domains {
1386 compatible = "rockchip,rk3399-io-voltage-domain";
1387 status = "disabled";
1388 };
1389
1390 u2phy0: usb2-phy@e450 {
1391 compatible = "rockchip,rk3399-usb2phy";
1392 reg = <0xe450 0x10>;
1393 clocks = <&cru SCLK_USB2PHY0_REF>;
1394 clock-names = "phyclk";
1395 #clock-cells = <0>;
1396 clock-output-names = "clk_usbphy0_480m";
1397 status = "disabled";
1398
1399 u2phy0_host: host-port {
1400 #phy-cells = <0>;
1401 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1402 interrupt-names = "linestate";
1403 status = "disabled";
1404 };
1405
1406 u2phy0_otg: otg-port {
1407 #phy-cells = <0>;
1408 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1409 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1410 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1411 interrupt-names = "otg-bvalid", "otg-id",
1412 "linestate";
1413 status = "disabled";
1414 };
1415 };
1416
1417 u2phy1: usb2-phy@e460 {
1418 compatible = "rockchip,rk3399-usb2phy";
1419 reg = <0xe460 0x10>;
1420 clocks = <&cru SCLK_USB2PHY1_REF>;
1421 clock-names = "phyclk";
1422 #clock-cells = <0>;
1423 clock-output-names = "clk_usbphy1_480m";
1424 status = "disabled";
1425
1426 u2phy1_host: host-port {
1427 #phy-cells = <0>;
1428 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1429 interrupt-names = "linestate";
1430 status = "disabled";
1431 };
1432
1433 u2phy1_otg: otg-port {
1434 #phy-cells = <0>;
1435 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1436 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1437 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1438 interrupt-names = "otg-bvalid", "otg-id",
1439 "linestate";
1440 status = "disabled";
1441 };
1442 };
1443
1444 emmc_phy: phy@f780 {
1445 compatible = "rockchip,rk3399-emmc-phy";
1446 reg = <0xf780 0x24>;
1447 clocks = <&sdhci>;
1448 clock-names = "emmcclk";
1449 #phy-cells = <0>;
1450 status = "disabled";
1451 };
1452
1453 pcie_phy: pcie-phy {
1454 compatible = "rockchip,rk3399-pcie-phy";
1455 clocks = <&cru SCLK_PCIEPHY_REF>;
1456 clock-names = "refclk";
1457 #phy-cells = <1>;
1458 resets = <&cru SRST_PCIEPHY>;
1459 drive-impedance-ohm = <50>;
1460 reset-names = "phy";
1461 status = "disabled";
1462 };
1463 };
1464
1465 tcphy0: phy@ff7c0000 {
1466 compatible = "rockchip,rk3399-typec-phy";
1467 reg = <0x0 0xff7c0000 0x0 0x40000>;
1468 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1469 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1470 clock-names = "tcpdcore", "tcpdphy-ref";
1471 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1472 assigned-clock-rates = <50000000>;
1473 power-domains = <&power RK3399_PD_TCPD0>;
1474 resets = <&cru SRST_UPHY0>,
1475 <&cru SRST_UPHY0_PIPE_L00>,
1476 <&cru SRST_P_UPHY0_TCPHY>;
1477 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1478 rockchip,grf = <&grf>;
1479 status = "disabled";
1480
1481 tcphy0_dp: dp-port {
1482 #phy-cells = <0>;
1483 };
1484
1485 tcphy0_usb3: usb3-port {
1486 #phy-cells = <0>;
1487 };
1488 };
1489
1490 tcphy1: phy@ff800000 {
1491 compatible = "rockchip,rk3399-typec-phy";
1492 reg = <0x0 0xff800000 0x0 0x40000>;
1493 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1494 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1495 clock-names = "tcpdcore", "tcpdphy-ref";
1496 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1497 assigned-clock-rates = <50000000>;
1498 power-domains = <&power RK3399_PD_TCPD1>;
1499 resets = <&cru SRST_UPHY1>,
1500 <&cru SRST_UPHY1_PIPE_L00>,
1501 <&cru SRST_P_UPHY1_TCPHY>;
1502 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1503 rockchip,grf = <&grf>;
1504 status = "disabled";
1505
1506 tcphy1_dp: dp-port {
1507 #phy-cells = <0>;
1508 };
1509
1510 tcphy1_usb3: usb3-port {
1511 #phy-cells = <0>;
1512 };
1513 };
1514
1515 watchdog@ff848000 {
1516 compatible = "snps,dw-wdt";
1517 reg = <0x0 0xff848000 0x0 0x100>;
1518 clocks = <&cru PCLK_WDT>;
1519 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1520 };
1521
1522 rktimer: rktimer@ff850000 {
1523 compatible = "rockchip,rk3399-timer";
1524 reg = <0x0 0xff850000 0x0 0x1000>;
1525 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1526 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1527 clock-names = "pclk", "timer";
1528 };
1529
1530 spdif: spdif@ff870000 {
1531 compatible = "rockchip,rk3399-spdif";
1532 reg = <0x0 0xff870000 0x0 0x1000>;
1533 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1534 dmas = <&dmac_bus 7>;
1535 dma-names = "tx";
1536 clock-names = "mclk", "hclk";
1537 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1538 pinctrl-names = "default";
1539 pinctrl-0 = <&spdif_bus>;
1540 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1541 #sound-dai-cells = <0>;
1542 status = "disabled";
1543 };
1544
1545 i2s0: i2s@ff880000 {
1546 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1547 reg = <0x0 0xff880000 0x0 0x1000>;
1548 rockchip,grf = <&grf>;
1549 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1550 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1551 dma-names = "tx", "rx";
1552 clock-names = "i2s_clk", "i2s_hclk";
1553 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1554 pinctrl-names = "default";
1555 pinctrl-0 = <&i2s0_8ch_bus>;
1556 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1557 #sound-dai-cells = <0>;
1558 status = "disabled";
1559 };
1560
1561 i2s1: i2s@ff890000 {
1562 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1563 reg = <0x0 0xff890000 0x0 0x1000>;
1564 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1565 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1566 dma-names = "tx", "rx";
1567 clock-names = "i2s_clk", "i2s_hclk";
1568 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1569 pinctrl-names = "default";
1570 pinctrl-0 = <&i2s1_2ch_bus>;
1571 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1572 #sound-dai-cells = <0>;
1573 status = "disabled";
1574 };
1575
1576 i2s2: i2s@ff8a0000 {
1577 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1578 reg = <0x0 0xff8a0000 0x0 0x1000>;
1579 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1580 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1581 dma-names = "tx", "rx";
1582 clock-names = "i2s_clk", "i2s_hclk";
1583 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1584 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1585 #sound-dai-cells = <0>;
1586 status = "disabled";
1587 };
1588
1589 vopl: vop@ff8f0000 {
1590 compatible = "rockchip,rk3399-vop-lit";
1591 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1592 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1593 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1594 assigned-clock-rates = <400000000>, <100000000>;
1595 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1596 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1597 iommus = <&vopl_mmu>;
1598 power-domains = <&power RK3399_PD_VOPL>;
1599 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1600 reset-names = "axi", "ahb", "dclk";
1601 status = "disabled";
1602
1603 vopl_out: port {
1604 #address-cells = <1>;
1605 #size-cells = <0>;
1606
1607 vopl_out_mipi: endpoint@0 {
1608 reg = <0>;
1609 remote-endpoint = <&mipi_in_vopl>;
1610 };
1611
1612 vopl_out_edp: endpoint@1 {
1613 reg = <1>;
1614 remote-endpoint = <&edp_in_vopl>;
1615 };
1616
1617 vopl_out_hdmi: endpoint@2 {
1618 reg = <2>;
1619 remote-endpoint = <&hdmi_in_vopl>;
1620 };
1621
1622 vopl_out_mipi1: endpoint@3 {
1623 reg = <3>;
1624 remote-endpoint = <&mipi1_in_vopl>;
1625 };
1626
1627 vopl_out_dp: endpoint@4 {
1628 reg = <4>;
1629 remote-endpoint = <&dp_in_vopl>;
1630 };
1631 };
1632 };
1633
1634 vopl_mmu: iommu@ff8f3f00 {
1635 compatible = "rockchip,iommu";
1636 reg = <0x0 0xff8f3f00 0x0 0x100>;
1637 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1638 interrupt-names = "vopl_mmu";
1639 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1640 clock-names = "aclk", "iface";
1641 power-domains = <&power RK3399_PD_VOPL>;
1642 #iommu-cells = <0>;
1643 status = "disabled";
1644 };
1645
1646 vopb: vop@ff900000 {
1647 compatible = "rockchip,rk3399-vop-big";
1648 reg = <0x0 0xff900000 0x0 0x3efc>;
1649 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1650 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1651 assigned-clock-rates = <400000000>, <100000000>;
1652 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1653 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1654 iommus = <&vopb_mmu>;
1655 power-domains = <&power RK3399_PD_VOPB>;
1656 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1657 reset-names = "axi", "ahb", "dclk";
1658 status = "disabled";
1659
1660 vopb_out: port {
1661 #address-cells = <1>;
1662 #size-cells = <0>;
1663
1664 vopb_out_edp: endpoint@0 {
1665 reg = <0>;
1666 remote-endpoint = <&edp_in_vopb>;
1667 };
1668
1669 vopb_out_mipi: endpoint@1 {
1670 reg = <1>;
1671 remote-endpoint = <&mipi_in_vopb>;
1672 };
1673
1674 vopb_out_hdmi: endpoint@2 {
1675 reg = <2>;
1676 remote-endpoint = <&hdmi_in_vopb>;
1677 };
1678
1679 vopb_out_mipi1: endpoint@3 {
1680 reg = <3>;
1681 remote-endpoint = <&mipi1_in_vopb>;
1682 };
1683
1684 vopb_out_dp: endpoint@4 {
1685 reg = <4>;
1686 remote-endpoint = <&dp_in_vopb>;
1687 };
1688 };
1689 };
1690
1691 vopb_mmu: iommu@ff903f00 {
1692 compatible = "rockchip,iommu";
1693 reg = <0x0 0xff903f00 0x0 0x100>;
1694 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1695 interrupt-names = "vopb_mmu";
1696 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1697 clock-names = "aclk", "iface";
1698 power-domains = <&power RK3399_PD_VOPB>;
1699 #iommu-cells = <0>;
1700 status = "disabled";
1701 };
1702
1703 isp0_mmu: iommu@ff914000 {
1704 compatible = "rockchip,iommu";
1705 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1706 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1707 interrupt-names = "isp0_mmu";
1708 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1709 clock-names = "aclk", "iface";
1710 #iommu-cells = <0>;
1711 power-domains = <&power RK3399_PD_ISP0>;
1712 rockchip,disable-mmu-reset;
1713 };
1714
1715 isp1_mmu: iommu@ff924000 {
1716 compatible = "rockchip,iommu";
1717 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1718 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1719 interrupt-names = "isp1_mmu";
1720 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1721 clock-names = "aclk", "iface";
1722 #iommu-cells = <0>;
1723 power-domains = <&power RK3399_PD_ISP1>;
1724 rockchip,disable-mmu-reset;
1725 };
1726
1727 hdmi_sound: hdmi-sound {
1728 compatible = "simple-audio-card";
1729 simple-audio-card,format = "i2s";
1730 simple-audio-card,mclk-fs = <256>;
1731 simple-audio-card,name = "hdmi-sound";
1732 status = "disabled";
1733
1734 simple-audio-card,cpu {
1735 sound-dai = <&i2s2>;
1736 };
1737 simple-audio-card,codec {
1738 sound-dai = <&hdmi>;
1739 };
1740 };
1741
1742 hdmi: hdmi@ff940000 {
1743 compatible = "rockchip,rk3399-dw-hdmi";
1744 reg = <0x0 0xff940000 0x0 0x20000>;
1745 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1746 clocks = <&cru PCLK_HDMI_CTRL>,
1747 <&cru SCLK_HDMI_SFR>,
1748 <&cru PLL_VPLL>,
1749 <&cru PCLK_VIO_GRF>,
1750 <&cru SCLK_HDMI_CEC>;
1751 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1752 power-domains = <&power RK3399_PD_HDCP>;
1753 reg-io-width = <4>;
1754 rockchip,grf = <&grf>;
1755 #sound-dai-cells = <0>;
1756 status = "disabled";
1757
1758 ports {
1759 hdmi_in: port {
1760 #address-cells = <1>;
1761 #size-cells = <0>;
1762
1763 hdmi_in_vopb: endpoint@0 {
1764 reg = <0>;
1765 remote-endpoint = <&vopb_out_hdmi>;
1766 };
1767 hdmi_in_vopl: endpoint@1 {
1768 reg = <1>;
1769 remote-endpoint = <&vopl_out_hdmi>;
1770 };
1771 };
1772 };
1773 };
1774
1775 mipi_dsi: mipi@ff960000 {
1776 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1777 reg = <0x0 0xff960000 0x0 0x8000>;
1778 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1779 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1780 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1781 clock-names = "ref", "pclk", "phy_cfg", "grf";
1782 power-domains = <&power RK3399_PD_VIO>;
1783 resets = <&cru SRST_P_MIPI_DSI0>;
1784 reset-names = "apb";
1785 rockchip,grf = <&grf>;
1786 #address-cells = <1>;
1787 #size-cells = <0>;
1788 status = "disabled";
1789
1790 ports {
1791 #address-cells = <1>;
1792 #size-cells = <0>;
1793
1794 mipi_in: port@0 {
1795 reg = <0>;
1796 #address-cells = <1>;
1797 #size-cells = <0>;
1798
1799 mipi_in_vopb: endpoint@0 {
1800 reg = <0>;
1801 remote-endpoint = <&vopb_out_mipi>;
1802 };
1803 mipi_in_vopl: endpoint@1 {
1804 reg = <1>;
1805 remote-endpoint = <&vopl_out_mipi>;
1806 };
1807 };
1808 };
1809 };
1810
1811 mipi_dsi1: mipi@ff968000 {
1812 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1813 reg = <0x0 0xff968000 0x0 0x8000>;
1814 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1815 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1816 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1817 clock-names = "ref", "pclk", "phy_cfg", "grf";
1818 power-domains = <&power RK3399_PD_VIO>;
1819 resets = <&cru SRST_P_MIPI_DSI1>;
1820 reset-names = "apb";
1821 rockchip,grf = <&grf>;
1822 #address-cells = <1>;
1823 #size-cells = <0>;
1824 status = "disabled";
1825
1826 ports {
1827 #address-cells = <1>;
1828 #size-cells = <0>;
1829
1830 mipi1_in: port@0 {
1831 reg = <0>;
1832 #address-cells = <1>;
1833 #size-cells = <0>;
1834
1835 mipi1_in_vopb: endpoint@0 {
1836 reg = <0>;
1837 remote-endpoint = <&vopb_out_mipi1>;
1838 };
1839
1840 mipi1_in_vopl: endpoint@1 {
1841 reg = <1>;
1842 remote-endpoint = <&vopl_out_mipi1>;
1843 };
1844 };
1845 };
1846 };
1847
1848 edp: edp@ff970000 {
1849 compatible = "rockchip,rk3399-edp";
1850 reg = <0x0 0xff970000 0x0 0x8000>;
1851 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1852 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1853 clock-names = "dp", "pclk", "grf";
1854 pinctrl-names = "default";
1855 pinctrl-0 = <&edp_hpd>;
1856 power-domains = <&power RK3399_PD_EDP>;
1857 resets = <&cru SRST_P_EDP_CTRL>;
1858 reset-names = "dp";
1859 rockchip,grf = <&grf>;
1860 status = "disabled";
1861
1862 ports {
1863 #address-cells = <1>;
1864 #size-cells = <0>;
1865 edp_in: port@0 {
1866 reg = <0>;
1867 #address-cells = <1>;
1868 #size-cells = <0>;
1869
1870 edp_in_vopb: endpoint@0 {
1871 reg = <0>;
1872 remote-endpoint = <&vopb_out_edp>;
1873 };
1874
1875 edp_in_vopl: endpoint@1 {
1876 reg = <1>;
1877 remote-endpoint = <&vopl_out_edp>;
1878 };
1879 };
1880 };
1881 };
1882
1883 gpu: gpu@ff9a0000 {
1884 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1885 reg = <0x0 0xff9a0000 0x0 0x10000>;
1886 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1887 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1888 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1889 interrupt-names = "gpu", "job", "mmu";
1890 clocks = <&cru ACLK_GPU>;
1891 #cooling-cells = <2>;
1892 power-domains = <&power RK3399_PD_GPU>;
1893 status = "disabled";
1894 };
1895
1896 pinctrl: pinctrl {
1897 compatible = "rockchip,rk3399-pinctrl";
1898 rockchip,grf = <&grf>;
1899 rockchip,pmu = <&pmugrf>;
1900 #address-cells = <2>;
1901 #size-cells = <2>;
1902 ranges;
1903
1904 gpio0: gpio0@ff720000 {
1905 compatible = "rockchip,gpio-bank";
1906 reg = <0x0 0xff720000 0x0 0x100>;
1907 clocks = <&pmucru PCLK_GPIO0_PMU>;
1908 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1909
1910 gpio-controller;
1911 #gpio-cells = <0x2>;
1912
1913 interrupt-controller;
1914 #interrupt-cells = <0x2>;
1915 };
1916
1917 gpio1: gpio1@ff730000 {
1918 compatible = "rockchip,gpio-bank";
1919 reg = <0x0 0xff730000 0x0 0x100>;
1920 clocks = <&pmucru PCLK_GPIO1_PMU>;
1921 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1922
1923 gpio-controller;
1924 #gpio-cells = <0x2>;
1925
1926 interrupt-controller;
1927 #interrupt-cells = <0x2>;
1928 };
1929
1930 gpio2: gpio2@ff780000 {
1931 compatible = "rockchip,gpio-bank";
1932 reg = <0x0 0xff780000 0x0 0x100>;
1933 clocks = <&cru PCLK_GPIO2>;
1934 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1935
1936 gpio-controller;
1937 #gpio-cells = <0x2>;
1938
1939 interrupt-controller;
1940 #interrupt-cells = <0x2>;
1941 };
1942
1943 gpio3: gpio3@ff788000 {
1944 compatible = "rockchip,gpio-bank";
1945 reg = <0x0 0xff788000 0x0 0x100>;
1946 clocks = <&cru PCLK_GPIO3>;
1947 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1948
1949 gpio-controller;
1950 #gpio-cells = <0x2>;
1951
1952 interrupt-controller;
1953 #interrupt-cells = <0x2>;
1954 };
1955
1956 gpio4: gpio4@ff790000 {
1957 compatible = "rockchip,gpio-bank";
1958 reg = <0x0 0xff790000 0x0 0x100>;
1959 clocks = <&cru PCLK_GPIO4>;
1960 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1961
1962 gpio-controller;
1963 #gpio-cells = <0x2>;
1964
1965 interrupt-controller;
1966 #interrupt-cells = <0x2>;
1967 };
1968
1969 pcfg_pull_up: pcfg-pull-up {
1970 bias-pull-up;
1971 };
1972
1973 pcfg_pull_down: pcfg-pull-down {
1974 bias-pull-down;
1975 };
1976
1977 pcfg_pull_none: pcfg-pull-none {
1978 bias-disable;
1979 };
1980
1981 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1982 bias-disable;
1983 drive-strength = <12>;
1984 };
1985
1986 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1987 bias-disable;
1988 drive-strength = <13>;
1989 };
1990
1991 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1992 bias-disable;
1993 drive-strength = <18>;
1994 };
1995
1996 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1997 bias-disable;
1998 drive-strength = <20>;
1999 };
2000
2001 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2002 bias-pull-up;
2003 drive-strength = <2>;
2004 };
2005
2006 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2007 bias-pull-up;
2008 drive-strength = <8>;
2009 };
2010
2011 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2012 bias-pull-up;
2013 drive-strength = <18>;
2014 };
2015
2016 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2017 bias-pull-up;
2018 drive-strength = <20>;
2019 };
2020
2021 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2022 bias-pull-down;
2023 drive-strength = <4>;
2024 };
2025
2026 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2027 bias-pull-down;
2028 drive-strength = <8>;
2029 };
2030
2031 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2032 bias-pull-down;
2033 drive-strength = <12>;
2034 };
2035
2036 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2037 bias-pull-down;
2038 drive-strength = <18>;
2039 };
2040
2041 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2042 bias-pull-down;
2043 drive-strength = <20>;
2044 };
2045
2046 pcfg_output_high: pcfg-output-high {
2047 output-high;
2048 };
2049
2050 pcfg_output_low: pcfg-output-low {
2051 output-low;
2052 };
2053
2054 clock {
2055 clk_32k: clk-32k {
2056 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
2057 };
2058 };
2059
2060 edp {
2061 edp_hpd: edp-hpd {
2062 rockchip,pins =
2063 <4 RK_PC7 2 &pcfg_pull_none>;
2064 };
2065 };
2066
2067 gmac {
2068 rgmii_pins: rgmii-pins {
2069 rockchip,pins =
2070 /* mac_txclk */
2071 <3 RK_PC1 1 &pcfg_pull_none_13ma>,
2072 /* mac_rxclk */
2073 <3 RK_PB6 1 &pcfg_pull_none>,
2074 /* mac_mdio */
2075 <3 RK_PB5 1 &pcfg_pull_none>,
2076 /* mac_txen */
2077 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2078 /* mac_clk */
2079 <3 RK_PB3 1 &pcfg_pull_none>,
2080 /* mac_rxdv */
2081 <3 RK_PB1 1 &pcfg_pull_none>,
2082 /* mac_mdc */
2083 <3 RK_PB0 1 &pcfg_pull_none>,
2084 /* mac_rxd1 */
2085 <3 RK_PA7 1 &pcfg_pull_none>,
2086 /* mac_rxd0 */
2087 <3 RK_PA6 1 &pcfg_pull_none>,
2088 /* mac_txd1 */
2089 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2090 /* mac_txd0 */
2091 <3 RK_PA4 1 &pcfg_pull_none_13ma>,
2092 /* mac_rxd3 */
2093 <3 RK_PA3 1 &pcfg_pull_none>,
2094 /* mac_rxd2 */
2095 <3 RK_PA2 1 &pcfg_pull_none>,
2096 /* mac_txd3 */
2097 <3 RK_PA1 1 &pcfg_pull_none_13ma>,
2098 /* mac_txd2 */
2099 <3 RK_PA0 1 &pcfg_pull_none_13ma>;
2100 };
2101
2102 rmii_pins: rmii-pins {
2103 rockchip,pins =
2104 /* mac_mdio */
2105 <3 RK_PB5 1 &pcfg_pull_none>,
2106 /* mac_txen */
2107 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2108 /* mac_clk */
2109 <3 RK_PB3 1 &pcfg_pull_none>,
2110 /* mac_rxer */
2111 <3 RK_PB2 1 &pcfg_pull_none>,
2112 /* mac_rxdv */
2113 <3 RK_PB1 1 &pcfg_pull_none>,
2114 /* mac_mdc */
2115 <3 RK_PB0 1 &pcfg_pull_none>,
2116 /* mac_rxd1 */
2117 <3 RK_PA7 1 &pcfg_pull_none>,
2118 /* mac_rxd0 */
2119 <3 RK_PA6 1 &pcfg_pull_none>,
2120 /* mac_txd1 */
2121 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2122 /* mac_txd0 */
2123 <3 RK_PA4 1 &pcfg_pull_none_13ma>;
2124 };
2125 };
2126
2127 i2c0 {
2128 i2c0_xfer: i2c0-xfer {
2129 rockchip,pins =
2130 <1 RK_PB7 2 &pcfg_pull_none>,
2131 <1 RK_PC0 2 &pcfg_pull_none>;
2132 };
2133 };
2134
2135 i2c1 {
2136 i2c1_xfer: i2c1-xfer {
2137 rockchip,pins =
2138 <4 RK_PA2 1 &pcfg_pull_none>,
2139 <4 RK_PA1 1 &pcfg_pull_none>;
2140 };
2141 };
2142
2143 i2c2 {
2144 i2c2_xfer: i2c2-xfer {
2145 rockchip,pins =
2146 <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2147 <2 RK_PA0 2 &pcfg_pull_none_12ma>;
2148 };
2149 };
2150
2151 i2c3 {
2152 i2c3_xfer: i2c3-xfer {
2153 rockchip,pins =
2154 <4 RK_PC1 1 &pcfg_pull_none>,
2155 <4 RK_PC0 1 &pcfg_pull_none>;
2156 };
2157 };
2158
2159 i2c4 {
2160 i2c4_xfer: i2c4-xfer {
2161 rockchip,pins =
2162 <1 RK_PB4 1 &pcfg_pull_none>,
2163 <1 RK_PB3 1 &pcfg_pull_none>;
2164 };
2165 };
2166
2167 i2c5 {
2168 i2c5_xfer: i2c5-xfer {
2169 rockchip,pins =
2170 <3 RK_PB3 2 &pcfg_pull_none>,
2171 <3 RK_PB2 2 &pcfg_pull_none>;
2172 };
2173 };
2174
2175 i2c6 {
2176 i2c6_xfer: i2c6-xfer {
2177 rockchip,pins =
2178 <2 RK_PB2 2 &pcfg_pull_none>,
2179 <2 RK_PB1 2 &pcfg_pull_none>;
2180 };
2181 };
2182
2183 i2c7 {
2184 i2c7_xfer: i2c7-xfer {
2185 rockchip,pins =
2186 <2 RK_PB0 2 &pcfg_pull_none>,
2187 <2 RK_PA7 2 &pcfg_pull_none>;
2188 };
2189 };
2190
2191 i2c8 {
2192 i2c8_xfer: i2c8-xfer {
2193 rockchip,pins =
2194 <1 RK_PC5 1 &pcfg_pull_none>,
2195 <1 RK_PC4 1 &pcfg_pull_none>;
2196 };
2197 };
2198
2199 i2s0 {
2200 i2s0_2ch_bus: i2s0-2ch-bus {
2201 rockchip,pins =
2202 <3 RK_PD0 1 &pcfg_pull_none>,
2203 <3 RK_PD1 1 &pcfg_pull_none>,
2204 <3 RK_PD2 1 &pcfg_pull_none>,
2205 <3 RK_PD3 1 &pcfg_pull_none>,
2206 <3 RK_PD7 1 &pcfg_pull_none>,
2207 <4 RK_PA0 1 &pcfg_pull_none>;
2208 };
2209
2210 i2s0_8ch_bus: i2s0-8ch-bus {
2211 rockchip,pins =
2212 <3 RK_PD0 1 &pcfg_pull_none>,
2213 <3 RK_PD1 1 &pcfg_pull_none>,
2214 <3 RK_PD2 1 &pcfg_pull_none>,
2215 <3 RK_PD3 1 &pcfg_pull_none>,
2216 <3 RK_PD4 1 &pcfg_pull_none>,
2217 <3 RK_PD5 1 &pcfg_pull_none>,
2218 <3 RK_PD6 1 &pcfg_pull_none>,
2219 <3 RK_PD7 1 &pcfg_pull_none>,
2220 <4 RK_PA0 1 &pcfg_pull_none>;
2221 };
2222 };
2223
2224 i2s1 {
2225 i2s1_2ch_bus: i2s1-2ch-bus {
2226 rockchip,pins =
2227 <4 RK_PA3 1 &pcfg_pull_none>,
2228 <4 RK_PA4 1 &pcfg_pull_none>,
2229 <4 RK_PA5 1 &pcfg_pull_none>,
2230 <4 RK_PA6 1 &pcfg_pull_none>,
2231 <4 RK_PA7 1 &pcfg_pull_none>;
2232 };
2233 };
2234
2235 sdio0 {
2236 sdio0_bus1: sdio0-bus1 {
2237 rockchip,pins =
2238 <2 RK_PC4 1 &pcfg_pull_up>;
2239 };
2240
2241 sdio0_bus4: sdio0-bus4 {
2242 rockchip,pins =
2243 <2 RK_PC4 1 &pcfg_pull_up>,
2244 <2 RK_PC5 1 &pcfg_pull_up>,
2245 <2 RK_PC6 1 &pcfg_pull_up>,
2246 <2 RK_PC7 1 &pcfg_pull_up>;
2247 };
2248
2249 sdio0_cmd: sdio0-cmd {
2250 rockchip,pins =
2251 <2 RK_PD0 1 &pcfg_pull_up>;
2252 };
2253
2254 sdio0_clk: sdio0-clk {
2255 rockchip,pins =
2256 <2 RK_PD1 1 &pcfg_pull_none>;
2257 };
2258
2259 sdio0_cd: sdio0-cd {
2260 rockchip,pins =
2261 <2 RK_PD2 1 &pcfg_pull_up>;
2262 };
2263
2264 sdio0_pwr: sdio0-pwr {
2265 rockchip,pins =
2266 <2 RK_PD3 1 &pcfg_pull_up>;
2267 };
2268
2269 sdio0_bkpwr: sdio0-bkpwr {
2270 rockchip,pins =
2271 <2 RK_PD4 1 &pcfg_pull_up>;
2272 };
2273
2274 sdio0_wp: sdio0-wp {
2275 rockchip,pins =
2276 <0 RK_PA3 1 &pcfg_pull_up>;
2277 };
2278
2279 sdio0_int: sdio0-int {
2280 rockchip,pins =
2281 <0 RK_PA4 1 &pcfg_pull_up>;
2282 };
2283 };
2284
2285 sdmmc {
2286 sdmmc_bus1: sdmmc-bus1 {
2287 rockchip,pins =
2288 <4 RK_PB0 1 &pcfg_pull_up>;
2289 };
2290
2291 sdmmc_bus4: sdmmc-bus4 {
2292 rockchip,pins =
2293 <4 RK_PB0 1 &pcfg_pull_up>,
2294 <4 RK_PB1 1 &pcfg_pull_up>,
2295 <4 RK_PB2 1 &pcfg_pull_up>,
2296 <4 RK_PB3 1 &pcfg_pull_up>;
2297 };
2298
2299 sdmmc_clk: sdmmc-clk {
2300 rockchip,pins =
2301 <4 RK_PB4 1 &pcfg_pull_none>;
2302 };
2303
2304 sdmmc_cmd: sdmmc-cmd {
2305 rockchip,pins =
2306 <4 RK_PB5 1 &pcfg_pull_up>;
2307 };
2308
2309 sdmmc_cd: sdmmc-cd {
2310 rockchip,pins =
2311 <0 RK_PA7 1 &pcfg_pull_up>;
2312 };
2313
2314 sdmmc_wp: sdmmc-wp {
2315 rockchip,pins =
2316 <0 RK_PB0 1 &pcfg_pull_up>;
2317 };
2318 };
2319
2320 sleep {
2321 ap_pwroff: ap-pwroff {
2322 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
2323 };
2324
2325 ddrio_pwroff: ddrio-pwroff {
2326 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
2327 };
2328 };
2329
2330 spdif {
2331 spdif_bus: spdif-bus {
2332 rockchip,pins =
2333 <4 RK_PC5 1 &pcfg_pull_none>;
2334 };
2335
2336 spdif_bus_1: spdif-bus-1 {
2337 rockchip,pins =
2338 <3 RK_PC0 3 &pcfg_pull_none>;
2339 };
2340 };
2341
2342 spi0 {
2343 spi0_clk: spi0-clk {
2344 rockchip,pins =
2345 <3 RK_PA6 2 &pcfg_pull_up>;
2346 };
2347 spi0_cs0: spi0-cs0 {
2348 rockchip,pins =
2349 <3 RK_PA7 2 &pcfg_pull_up>;
2350 };
2351 spi0_cs1: spi0-cs1 {
2352 rockchip,pins =
2353 <3 RK_PB0 2 &pcfg_pull_up>;
2354 };
2355 spi0_tx: spi0-tx {
2356 rockchip,pins =
2357 <3 RK_PA5 2 &pcfg_pull_up>;
2358 };
2359 spi0_rx: spi0-rx {
2360 rockchip,pins =
2361 <3 RK_PA4 2 &pcfg_pull_up>;
2362 };
2363 };
2364
2365 spi1 {
2366 spi1_clk: spi1-clk {
2367 rockchip,pins =
2368 <1 RK_PB1 2 &pcfg_pull_up>;
2369 };
2370 spi1_cs0: spi1-cs0 {
2371 rockchip,pins =
2372 <1 RK_PB2 2 &pcfg_pull_up>;
2373 };
2374 spi1_rx: spi1-rx {
2375 rockchip,pins =
2376 <1 RK_PA7 2 &pcfg_pull_up>;
2377 };
2378 spi1_tx: spi1-tx {
2379 rockchip,pins =
2380 <1 RK_PB0 2 &pcfg_pull_up>;
2381 };
2382 };
2383
2384 spi2 {
2385 spi2_clk: spi2-clk {
2386 rockchip,pins =
2387 <2 RK_PB3 1 &pcfg_pull_up>;
2388 };
2389 spi2_cs0: spi2-cs0 {
2390 rockchip,pins =
2391 <2 RK_PB4 1 &pcfg_pull_up>;
2392 };
2393 spi2_rx: spi2-rx {
2394 rockchip,pins =
2395 <2 RK_PB1 1 &pcfg_pull_up>;
2396 };
2397 spi2_tx: spi2-tx {
2398 rockchip,pins =
2399 <2 RK_PB2 1 &pcfg_pull_up>;
2400 };
2401 };
2402
2403 spi3 {
2404 spi3_clk: spi3-clk {
2405 rockchip,pins =
2406 <1 RK_PC1 1 &pcfg_pull_up>;
2407 };
2408 spi3_cs0: spi3-cs0 {
2409 rockchip,pins =
2410 <1 RK_PC2 1 &pcfg_pull_up>;
2411 };
2412 spi3_rx: spi3-rx {
2413 rockchip,pins =
2414 <1 RK_PB7 1 &pcfg_pull_up>;
2415 };
2416 spi3_tx: spi3-tx {
2417 rockchip,pins =
2418 <1 RK_PC0 1 &pcfg_pull_up>;
2419 };
2420 };
2421
2422 spi4 {
2423 spi4_clk: spi4-clk {
2424 rockchip,pins =
2425 <3 RK_PA2 2 &pcfg_pull_up>;
2426 };
2427 spi4_cs0: spi4-cs0 {
2428 rockchip,pins =
2429 <3 RK_PA3 2 &pcfg_pull_up>;
2430 };
2431 spi4_rx: spi4-rx {
2432 rockchip,pins =
2433 <3 RK_PA0 2 &pcfg_pull_up>;
2434 };
2435 spi4_tx: spi4-tx {
2436 rockchip,pins =
2437 <3 RK_PA1 2 &pcfg_pull_up>;
2438 };
2439 };
2440
2441 spi5 {
2442 spi5_clk: spi5-clk {
2443 rockchip,pins =
2444 <2 RK_PC6 2 &pcfg_pull_up>;
2445 };
2446 spi5_cs0: spi5-cs0 {
2447 rockchip,pins =
2448 <2 RK_PC7 2 &pcfg_pull_up>;
2449 };
2450 spi5_rx: spi5-rx {
2451 rockchip,pins =
2452 <2 RK_PC4 2 &pcfg_pull_up>;
2453 };
2454 spi5_tx: spi5-tx {
2455 rockchip,pins =
2456 <2 RK_PC5 2 &pcfg_pull_up>;
2457 };
2458 };
2459
2460 testclk {
2461 test_clkout0: test-clkout0 {
2462 rockchip,pins =
2463 <0 RK_PA0 1 &pcfg_pull_none>;
2464 };
2465
2466 test_clkout1: test-clkout1 {
2467 rockchip,pins =
2468 <2 RK_PD1 2 &pcfg_pull_none>;
2469 };
2470
2471 test_clkout2: test-clkout2 {
2472 rockchip,pins =
2473 <0 RK_PB0 3 &pcfg_pull_none>;
2474 };
2475 };
2476
2477 tsadc {
2478 otp_gpio: otp-gpio {
2479 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2480 };
2481
2482 otp_out: otp-out {
2483 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
2484 };
2485 };
2486
2487 uart0 {
2488 uart0_xfer: uart0-xfer {
2489 rockchip,pins =
2490 <2 RK_PC0 1 &pcfg_pull_up>,
2491 <2 RK_PC1 1 &pcfg_pull_none>;
2492 };
2493
2494 uart0_cts: uart0-cts {
2495 rockchip,pins =
2496 <2 RK_PC2 1 &pcfg_pull_none>;
2497 };
2498
2499 uart0_rts: uart0-rts {
2500 rockchip,pins =
2501 <2 RK_PC3 1 &pcfg_pull_none>;
2502 };
2503 };
2504
2505 uart1 {
2506 uart1_xfer: uart1-xfer {
2507 rockchip,pins =
2508 <3 RK_PB4 2 &pcfg_pull_up>,
2509 <3 RK_PB5 2 &pcfg_pull_none>;
2510 };
2511 };
2512
2513 uart2a {
2514 uart2a_xfer: uart2a-xfer {
2515 rockchip,pins =
2516 <4 RK_PB0 2 &pcfg_pull_up>,
2517 <4 RK_PB1 2 &pcfg_pull_none>;
2518 };
2519 };
2520
2521 uart2b {
2522 uart2b_xfer: uart2b-xfer {
2523 rockchip,pins =
2524 <4 RK_PC0 2 &pcfg_pull_up>,
2525 <4 RK_PC1 2 &pcfg_pull_none>;
2526 };
2527 };
2528
2529 uart2c {
2530 uart2c_xfer: uart2c-xfer {
2531 rockchip,pins =
2532 <4 RK_PC3 1 &pcfg_pull_up>,
2533 <4 RK_PC4 1 &pcfg_pull_none>;
2534 };
2535 };
2536
2537 uart3 {
2538 uart3_xfer: uart3-xfer {
2539 rockchip,pins =
2540 <3 RK_PB6 2 &pcfg_pull_up>,
2541 <3 RK_PB7 2 &pcfg_pull_none>;
2542 };
2543
2544 uart3_cts: uart3-cts {
2545 rockchip,pins =
2546 <3 RK_PC0 2 &pcfg_pull_none>;
2547 };
2548
2549 uart3_rts: uart3-rts {
2550 rockchip,pins =
2551 <3 RK_PC1 2 &pcfg_pull_none>;
2552 };
2553 };
2554
2555 uart4 {
2556 uart4_xfer: uart4-xfer {
2557 rockchip,pins =
2558 <1 RK_PA7 1 &pcfg_pull_up>,
2559 <1 RK_PB0 1 &pcfg_pull_none>;
2560 };
2561 };
2562
2563 uarthdcp {
2564 uarthdcp_xfer: uarthdcp-xfer {
2565 rockchip,pins =
2566 <4 RK_PC5 2 &pcfg_pull_up>,
2567 <4 RK_PC6 2 &pcfg_pull_none>;
2568 };
2569 };
2570
2571 pwm0 {
2572 pwm0_pin: pwm0-pin {
2573 rockchip,pins =
2574 <4 RK_PC2 1 &pcfg_pull_none>;
2575 };
2576
2577 pwm0_pin_pull_down: pwm0-pin-pull-down {
2578 rockchip,pins =
2579 <4 RK_PC2 1 &pcfg_pull_down>;
2580 };
2581
2582 vop0_pwm_pin: vop0-pwm-pin {
2583 rockchip,pins =
2584 <4 RK_PC2 2 &pcfg_pull_none>;
2585 };
2586
2587 vop1_pwm_pin: vop1-pwm-pin {
2588 rockchip,pins =
2589 <4 RK_PC2 3 &pcfg_pull_none>;
2590 };
2591 };
2592
2593 pwm1 {
2594 pwm1_pin: pwm1-pin {
2595 rockchip,pins =
2596 <4 RK_PC6 1 &pcfg_pull_none>;
2597 };
2598
2599 pwm1_pin_pull_down: pwm1-pin-pull-down {
2600 rockchip,pins =
2601 <4 RK_PC6 1 &pcfg_pull_down>;
2602 };
2603 };
2604
2605 pwm2 {
2606 pwm2_pin: pwm2-pin {
2607 rockchip,pins =
2608 <1 RK_PC3 1 &pcfg_pull_none>;
2609 };
2610
2611 pwm2_pin_pull_down: pwm2-pin-pull-down {
2612 rockchip,pins =
2613 <1 RK_PC3 1 &pcfg_pull_down>;
2614 };
2615 };
2616
2617 pwm3a {
2618 pwm3a_pin: pwm3a-pin {
2619 rockchip,pins =
2620 <0 RK_PA6 1 &pcfg_pull_none>;
2621 };
2622 };
2623
2624 pwm3b {
2625 pwm3b_pin: pwm3b-pin {
2626 rockchip,pins =
2627 <1 RK_PB6 1 &pcfg_pull_none>;
2628 };
2629 };
2630
2631 hdmi {
2632 hdmi_i2c_xfer: hdmi-i2c-xfer {
2633 rockchip,pins =
2634 <4 RK_PC1 3 &pcfg_pull_none>,
2635 <4 RK_PC0 3 &pcfg_pull_none>;
2636 };
2637
2638 hdmi_cec: hdmi-cec {
2639 rockchip,pins =
2640 <4 RK_PC7 1 &pcfg_pull_none>;
2641 };
2642 };
2643
2644 pcie {
2645 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2646 rockchip,pins =
2647 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2648 };
2649
2650 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2651 rockchip,pins =
2652 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2653 };
2654 };
2655
2656 };
2657 };
A mirror of Linus' kernel repository