arch/arm64/include/asm/cputype.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2012 ARM Ltd.
   4  */
   5 #ifndef __ASM_CPUTYPE_H
   6 #define __ASM_CPUTYPE_H
   7
   8 #define INVALID_HWID            ULONG_MAX
   9
  10 #define MPIDR_UP_BITMASK        (0x1 << 30)
  11 #define MPIDR_MT_BITMASK        (0x1 << 24)
  12 #define MPIDR_HWID_BITMASK      UL(0xff00ffffff)
  13
  14 #define MPIDR_LEVEL_BITS_SHIFT  3
  15 #define MPIDR_LEVEL_BITS        (1 << MPIDR_LEVEL_BITS_SHIFT)
  16 #define MPIDR_LEVEL_MASK        ((1 << MPIDR_LEVEL_BITS) - 1)
  17
  18 #define MPIDR_LEVEL_SHIFT(level) \
  19         (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
  20
  21 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  22         ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
  23
  24 #define MIDR_REVISION_MASK      0xf
  25 #define MIDR_REVISION(midr)     ((midr) & MIDR_REVISION_MASK)
  26 #define MIDR_PARTNUM_SHIFT      4
  27 #define MIDR_PARTNUM_MASK       (0xfff << MIDR_PARTNUM_SHIFT)
  28 #define MIDR_PARTNUM(midr)      \
  29         (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
  30 #define MIDR_ARCHITECTURE_SHIFT 16
  31 #define MIDR_ARCHITECTURE_MASK  (0xf << MIDR_ARCHITECTURE_SHIFT)
  32 #define MIDR_ARCHITECTURE(midr) \
  33         (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
  34 #define MIDR_VARIANT_SHIFT      20
  35 #define MIDR_VARIANT_MASK       (0xf << MIDR_VARIANT_SHIFT)
  36 #define MIDR_VARIANT(midr)      \
  37         (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
  38 #define MIDR_IMPLEMENTOR_SHIFT  24
  39 #define MIDR_IMPLEMENTOR_MASK   (0xff << MIDR_IMPLEMENTOR_SHIFT)
  40 #define MIDR_IMPLEMENTOR(midr)  \
  41         (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
  42
  43 #define MIDR_CPU_MODEL(imp, partnum) \
  44         (((imp)                 << MIDR_IMPLEMENTOR_SHIFT) | \
  45         (0xf                    << MIDR_ARCHITECTURE_SHIFT) | \
  46         ((partnum)              << MIDR_PARTNUM_SHIFT))
  47
  48 #define MIDR_CPU_VAR_REV(var, rev) \
  49         (((var) << MIDR_VARIANT_SHIFT) | (rev))
  50
  51 #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
  52                              MIDR_ARCHITECTURE_MASK)
  53
  54 #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max)            \
  55 ({                                                                      \
  56         u32 _model = (midr) & MIDR_CPU_MODEL_MASK;                      \
  57         u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK);     \
  58                                                                         \
  59         _model == (model) && rv >= (rv_min) && rv <= (rv_max);          \
  60  })
  61
  62 #define ARM_CPU_IMP_ARM                 0x41
  63 #define ARM_CPU_IMP_APM                 0x50
  64 #define ARM_CPU_IMP_CAVIUM              0x43
  65 #define ARM_CPU_IMP_BRCM                0x42
  66 #define ARM_CPU_IMP_QCOM                0x51
  67 #define ARM_CPU_IMP_NVIDIA              0x4E
  68 #define ARM_CPU_IMP_FUJITSU             0x46
  69 #define ARM_CPU_IMP_HISI                0x48
  70
  71 #define ARM_CPU_PART_AEM_V8             0xD0F
  72 #define ARM_CPU_PART_FOUNDATION         0xD00
  73 #define ARM_CPU_PART_CORTEX_A57         0xD07
  74 #define ARM_CPU_PART_CORTEX_A72         0xD08
  75 #define ARM_CPU_PART_CORTEX_A53         0xD03
  76 #define ARM_CPU_PART_CORTEX_A73         0xD09
  77 #define ARM_CPU_PART_CORTEX_A75         0xD0A
  78 #define ARM_CPU_PART_CORTEX_A35         0xD04
  79 #define ARM_CPU_PART_CORTEX_A55         0xD05
  80 #define ARM_CPU_PART_CORTEX_A76         0xD0B
  81 #define ARM_CPU_PART_NEOVERSE_N1        0xD0C
  82
  83 #define APM_CPU_PART_POTENZA            0x000
  84
  85 #define CAVIUM_CPU_PART_THUNDERX        0x0A1
  86 #define CAVIUM_CPU_PART_THUNDERX_81XX   0x0A2
  87 #define CAVIUM_CPU_PART_THUNDERX_83XX   0x0A3
  88 #define CAVIUM_CPU_PART_THUNDERX2       0x0AF
  89
  90 #define BRCM_CPU_PART_VULCAN            0x516
  91
  92 #define QCOM_CPU_PART_FALKOR_V1         0x800
  93 #define QCOM_CPU_PART_FALKOR            0xC00
  94 #define QCOM_CPU_PART_KRYO              0x200
  95
  96 #define NVIDIA_CPU_PART_DENVER          0x003
  97 #define NVIDIA_CPU_PART_CARMEL          0x004
  98
  99 #define FUJITSU_CPU_PART_A64FX          0x001
 100
 101 #define HISI_CPU_PART_TSV110            0xD01
 102
 103 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
 104 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
 105 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
 106 #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
 107 #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
 108 #define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
 109 #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
 110 #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
 111 #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
 112 #define MIDR_THUNDERX   MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 113 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 114 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
 115 #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
 116 #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
 117 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
 118 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
 119 #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
 120 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
 121 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
 122 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
 123 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
 124
 125 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
 126 #define MIDR_FUJITSU_ERRATUM_010001             MIDR_FUJITSU_A64FX
 127 #define MIDR_FUJITSU_ERRATUM_010001_MASK        (~MIDR_CPU_VAR_REV(1, 0))
 128 #define TCR_CLEAR_FUJITSU_ERRATUM_010001        (TCR_NFD1 | TCR_NFD0)
 129
 130 #ifndef __ASSEMBLY__
 131
 132 #include <asm/sysreg.h>
 133
 134 #define read_cpuid(reg)                 read_sysreg_s(SYS_ ## reg)
 135
 136 /*
 137  * Represent a range of MIDR values for a given CPU model and a
 138  * range of variant/revision values.
 139  *
 140  * @model       - CPU model as defined by MIDR_CPU_MODEL
 141  * @rv_min      - Minimum value for the revision/variant as defined by
 142  *                MIDR_CPU_VAR_REV
 143  * @rv_max      - Maximum value for the variant/revision for the range.
 144  */
 145 struct midr_range {
 146         u32 model;
 147         u32 rv_min;
 148         u32 rv_max;
 149 };
 150
 151 #define MIDR_RANGE(m, v_min, r_min, v_max, r_max)               \
 152         {                                                       \
 153                 .model = m,                                     \
 154                 .rv_min = MIDR_CPU_VAR_REV(v_min, r_min),       \
 155                 .rv_max = MIDR_CPU_VAR_REV(v_max, r_max),       \
 156         }
 157
 158 #define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
 159 #define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
 160 #define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
 161
 162 static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
 163 {
 164         return MIDR_IS_CPU_MODEL_RANGE(midr, range->model,
 165                                  range->rv_min, range->rv_max);
 166 }
 167
 168 static inline bool
 169 is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
 170 {
 171         while (ranges->model)
 172                 if (is_midr_in_range(midr, ranges++))
 173                         return true;
 174         return false;
 175 }
 176
 177 /*
 178  * The CPU ID never changes at run time, so we might as well tell the
 179  * compiler that it's constant.  Use this function to read the CPU ID
 180  * rather than directly reading processor_id or read_cpuid() directly.
 181  */
 182 static inline u32 __attribute_const__ read_cpuid_id(void)
 183 {
 184         return read_cpuid(MIDR_EL1);
 185 }
 186
 187 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
 188 {
 189         return read_cpuid(MPIDR_EL1);
 190 }
 191
 192 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 193 {
 194         return MIDR_IMPLEMENTOR(read_cpuid_id());
 195 }
 196
 197 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
 198 {
 199         return MIDR_PARTNUM(read_cpuid_id());
 200 }
 201
 202 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
 203 {
 204         return read_cpuid(CTR_EL0);
 205 }
 206 #endif /* __ASSEMBLY__ */
 207
 208 #endif