arch/arm64/kernel/entry.S

   1 /*
   2  * Low-level exception handling code
   3  *
   4  * Copyright (C) 2012 ARM Ltd.
   5  * Authors:     Catalin Marinas <catalin.marinas@arm.com>
   6  *              Will Deacon <will.deacon@arm.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <linux/arm-smccc.h>
  22 #include <linux/init.h>
  23 #include <linux/linkage.h>
  24
  25 #include <asm/alternative.h>
  26 #include <asm/assembler.h>
  27 #include <asm/asm-offsets.h>
  28 #include <asm/cpufeature.h>
  29 #include <asm/errno.h>
  30 #include <asm/esr.h>
  31 #include <asm/irq.h>
  32 #include <asm/memory.h>
  33 #include <asm/mmu.h>
  34 #include <asm/processor.h>
  35 #include <asm/ptrace.h>
  36 #include <asm/thread_info.h>
  37 #include <asm/asm-uaccess.h>
  38 #include <asm/unistd.h>
  39
  40 /*
  41  * Context tracking subsystem.  Used to instrument transitions
  42  * between user and kernel mode.
  43  */
  44         .macro ct_user_exit
  45 #ifdef CONFIG_CONTEXT_TRACKING
  46         bl      context_tracking_user_exit
  47 #endif
  48         .endm
  49
  50         .macro ct_user_enter
  51 #ifdef CONFIG_CONTEXT_TRACKING
  52         bl      context_tracking_user_enter
  53 #endif
  54         .endm
  55
  56         .macro  clear_gp_regs
  57         .irp    n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
  58         mov     x\n, xzr
  59         .endr
  60         .endm
  61
  62 /*
  63  * Bad Abort numbers
  64  *-----------------
  65  */
  66 #define BAD_SYNC        0
  67 #define BAD_IRQ         1
  68 #define BAD_FIQ         2
  69 #define BAD_ERROR       3
  70
  71         .macro kernel_ventry, el, label, regsize = 64
  72         .align 7
  73 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
  74 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
  75         .if     \el == 0
  76         .if     \regsize == 64
  77         mrs     x30, tpidrro_el0
  78         msr     tpidrro_el0, xzr
  79         .else
  80         mov     x30, xzr
  81         .endif
  82         .endif
  83 alternative_else_nop_endif
  84 #endif
  85
  86         sub     sp, sp, #S_FRAME_SIZE
  87 #ifdef CONFIG_VMAP_STACK
  88         /*
  89          * Test whether the SP has overflowed, without corrupting a GPR.
  90          * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT).
  91          */
  92         add     sp, sp, x0                      // sp' = sp + x0
  93         sub     x0, sp, x0                      // x0' = sp' - x0 = (sp + x0) - x0 = sp
  94         tbnz    x0, #THREAD_SHIFT, 0f
  95         sub     x0, sp, x0                      // x0'' = sp' - x0' = (sp + x0) - sp = x0
  96         sub     sp, sp, x0                      // sp'' = sp' - x0 = (sp + x0) - x0 = sp
  97         b       el\()\el\()_\label
  98
  99 0:
 100         /*
 101          * Either we've just detected an overflow, or we've taken an exception
 102          * while on the overflow stack. Either way, we won't return to
 103          * userspace, and can clobber EL0 registers to free up GPRs.
 104          */
 105
 106         /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
 107         msr     tpidr_el0, x0
 108
 109         /* Recover the original x0 value and stash it in tpidrro_el0 */
 110         sub     x0, sp, x0
 111         msr     tpidrro_el0, x0
 112
 113         /* Switch to the overflow stack */
 114         adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
 115
 116         /*
 117          * Check whether we were already on the overflow stack. This may happen
 118          * after panic() re-enables interrupts.
 119          */
 120         mrs     x0, tpidr_el0                   // sp of interrupted context
 121         sub     x0, sp, x0                      // delta with top of overflow stack
 122         tst     x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
 123         b.ne    __bad_stack                     // no? -> bad stack pointer
 124
 125         /* We were already on the overflow stack. Restore sp/x0 and carry on. */
 126         sub     sp, sp, x0
 127         mrs     x0, tpidrro_el0
 128 #endif
 129         b       el\()\el\()_\label
 130         .endm
 131
 132         .macro tramp_alias, dst, sym
 133         mov_q   \dst, TRAMP_VALIAS
 134         add     \dst, \dst, #(\sym - .entry.tramp.text)
 135         .endm
 136
 137         // This macro corrupts x0-x3. It is the caller's duty
 138         // to save/restore them if required.
 139         .macro  apply_ssbd, state, tmp1, tmp2
 140 #ifdef CONFIG_ARM64_SSBD
 141 alternative_cb  arm64_enable_wa2_handling
 142         b       .L__asm_ssbd_skip\@
 143 alternative_cb_end
 144         ldr_this_cpu    \tmp2, arm64_ssbd_callback_required, \tmp1
 145         cbz     \tmp2,  .L__asm_ssbd_skip\@
 146         ldr     \tmp2, [tsk, #TSK_TI_FLAGS]
 147         tbnz    \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
 148         mov     w0, #ARM_SMCCC_ARCH_WORKAROUND_2
 149         mov     w1, #\state
 150 alternative_cb  arm64_update_smccc_conduit
 151         nop                                     // Patched to SMC/HVC #0
 152 alternative_cb_end
 153 .L__asm_ssbd_skip\@:
 154 #endif
 155         .endm
 156
 157         .macro  kernel_entry, el, regsize = 64
 158         .if     \regsize == 32
 159         mov     w0, w0                          // zero upper 32 bits of x0
 160         .endif
 161         stp     x0, x1, [sp, #16 * 0]
 162         stp     x2, x3, [sp, #16 * 1]
 163         stp     x4, x5, [sp, #16 * 2]
 164         stp     x6, x7, [sp, #16 * 3]
 165         stp     x8, x9, [sp, #16 * 4]
 166         stp     x10, x11, [sp, #16 * 5]
 167         stp     x12, x13, [sp, #16 * 6]
 168         stp     x14, x15, [sp, #16 * 7]
 169         stp     x16, x17, [sp, #16 * 8]
 170         stp     x18, x19, [sp, #16 * 9]
 171         stp     x20, x21, [sp, #16 * 10]
 172         stp     x22, x23, [sp, #16 * 11]
 173         stp     x24, x25, [sp, #16 * 12]
 174         stp     x26, x27, [sp, #16 * 13]
 175         stp     x28, x29, [sp, #16 * 14]
 176
 177         .if     \el == 0
 178         clear_gp_regs
 179         mrs     x21, sp_el0
 180         ldr_this_cpu    tsk, __entry_task, x20  // Ensure MDSCR_EL1.SS is clear,
 181         ldr     x19, [tsk, #TSK_TI_FLAGS]       // since we can unmask debug
 182         disable_step_tsk x19, x20               // exceptions when scheduling.
 183
 184         apply_ssbd 1, x22, x23
 185
 186         .else
 187         add     x21, sp, #S_FRAME_SIZE
 188         get_current_task tsk
 189         /* Save the task's original addr_limit and set USER_DS */
 190         ldr     x20, [tsk, #TSK_TI_ADDR_LIMIT]
 191         str     x20, [sp, #S_ORIG_ADDR_LIMIT]
 192         mov     x20, #USER_DS
 193         str     x20, [tsk, #TSK_TI_ADDR_LIMIT]
 194         /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
 195         .endif /* \el == 0 */
 196         mrs     x22, elr_el1
 197         mrs     x23, spsr_el1
 198         stp     lr, x21, [sp, #S_LR]
 199
 200         /*
 201          * In order to be able to dump the contents of struct pt_regs at the
 202          * time the exception was taken (in case we attempt to walk the call
 203          * stack later), chain it together with the stack frames.
 204          */
 205         .if \el == 0
 206         stp     xzr, xzr, [sp, #S_STACKFRAME]
 207         .else
 208         stp     x29, x22, [sp, #S_STACKFRAME]
 209         .endif
 210         add     x29, sp, #S_STACKFRAME
 211
 212 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
 213         /*
 214          * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
 215          * EL0, there is no need to check the state of TTBR0_EL1 since
 216          * accesses are always enabled.
 217          * Note that the meaning of this bit differs from the ARMv8.1 PAN
 218          * feature as all TTBR0_EL1 accesses are disabled, not just those to
 219          * user mappings.
 220          */
 221 alternative_if ARM64_HAS_PAN
 222         b       1f                              // skip TTBR0 PAN
 223 alternative_else_nop_endif
 224
 225         .if     \el != 0
 226         mrs     x21, ttbr0_el1
 227         tst     x21, #TTBR_ASID_MASK            // Check for the reserved ASID
 228         orr     x23, x23, #PSR_PAN_BIT          // Set the emulated PAN in the saved SPSR
 229         b.eq    1f                              // TTBR0 access already disabled
 230         and     x23, x23, #~PSR_PAN_BIT         // Clear the emulated PAN in the saved SPSR
 231         .endif
 232
 233         __uaccess_ttbr0_disable x21
 234 1:
 235 #endif
 236
 237         stp     x22, x23, [sp, #S_PC]
 238
 239         /* Not in a syscall by default (el0_svc overwrites for real syscall) */
 240         .if     \el == 0
 241         mov     w21, #NO_SYSCALL
 242         str     w21, [sp, #S_SYSCALLNO]
 243         .endif
 244
 245         /*
 246          * Set sp_el0 to current thread_info.
 247          */
 248         .if     \el == 0
 249         msr     sp_el0, tsk
 250         .endif
 251
 252         /* Save pmr */
 253 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
 254         mrs_s   x20, SYS_ICC_PMR_EL1
 255         str     x20, [sp, #S_PMR_SAVE]
 256 alternative_else_nop_endif
 257
 258         /*
 259          * Registers that may be useful after this macro is invoked:
 260          *
 261          * x21 - aborted SP
 262          * x22 - aborted PC
 263          * x23 - aborted PSTATE
 264         */
 265         .endm
 266
 267         .macro  kernel_exit, el
 268         .if     \el != 0
 269         disable_daif
 270
 271         /* Restore the task's original addr_limit. */
 272         ldr     x20, [sp, #S_ORIG_ADDR_LIMIT]
 273         str     x20, [tsk, #TSK_TI_ADDR_LIMIT]
 274
 275         /* No need to restore UAO, it will be restored from SPSR_EL1 */
 276         .endif
 277
 278         /* Restore pmr */
 279 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
 280         ldr     x20, [sp, #S_PMR_SAVE]
 281         msr_s   SYS_ICC_PMR_EL1, x20
 282         /* Ensure priority change is seen by redistributor */
 283         dsb     sy
 284 alternative_else_nop_endif
 285
 286         ldp     x21, x22, [sp, #S_PC]           // load ELR, SPSR
 287         .if     \el == 0
 288         ct_user_enter
 289         .endif
 290
 291 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
 292         /*
 293          * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
 294          * PAN bit checking.
 295          */
 296 alternative_if ARM64_HAS_PAN
 297         b       2f                              // skip TTBR0 PAN
 298 alternative_else_nop_endif
 299
 300         .if     \el != 0
 301         tbnz    x22, #22, 1f                    // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
 302         .endif
 303
 304         __uaccess_ttbr0_enable x0, x1
 305
 306         .if     \el == 0
 307         /*
 308          * Enable errata workarounds only if returning to user. The only
 309          * workaround currently required for TTBR0_EL1 changes are for the
 310          * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
 311          * corruption).
 312          */
 313         bl      post_ttbr_update_workaround
 314         .endif
 315 1:
 316         .if     \el != 0
 317         and     x22, x22, #~PSR_PAN_BIT         // ARMv8.0 CPUs do not understand this bit
 318         .endif
 319 2:
 320 #endif
 321
 322         .if     \el == 0
 323         ldr     x23, [sp, #S_SP]                // load return stack pointer
 324         msr     sp_el0, x23
 325         tst     x22, #PSR_MODE32_BIT            // native task?
 326         b.eq    3f
 327
 328 #ifdef CONFIG_ARM64_ERRATUM_845719
 329 alternative_if ARM64_WORKAROUND_845719
 330 #ifdef CONFIG_PID_IN_CONTEXTIDR
 331         mrs     x29, contextidr_el1
 332         msr     contextidr_el1, x29
 333 #else
 334         msr contextidr_el1, xzr
 335 #endif
 336 alternative_else_nop_endif
 337 #endif
 338 3:
 339         apply_ssbd 0, x0, x1
 340         .endif
 341
 342         msr     elr_el1, x21                    // set up the return data
 343         msr     spsr_el1, x22
 344         ldp     x0, x1, [sp, #16 * 0]
 345         ldp     x2, x3, [sp, #16 * 1]
 346         ldp     x4, x5, [sp, #16 * 2]
 347         ldp     x6, x7, [sp, #16 * 3]
 348         ldp     x8, x9, [sp, #16 * 4]
 349         ldp     x10, x11, [sp, #16 * 5]
 350         ldp     x12, x13, [sp, #16 * 6]
 351         ldp     x14, x15, [sp, #16 * 7]
 352         ldp     x16, x17, [sp, #16 * 8]
 353         ldp     x18, x19, [sp, #16 * 9]
 354         ldp     x20, x21, [sp, #16 * 10]
 355         ldp     x22, x23, [sp, #16 * 11]
 356         ldp     x24, x25, [sp, #16 * 12]
 357         ldp     x26, x27, [sp, #16 * 13]
 358         ldp     x28, x29, [sp, #16 * 14]
 359         ldr     lr, [sp, #S_LR]
 360         add     sp, sp, #S_FRAME_SIZE           // restore sp
 361
 362         .if     \el == 0
 363 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
 364 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 365         bne     4f
 366         msr     far_el1, x30
 367         tramp_alias     x30, tramp_exit_native
 368         br      x30
 369 4:
 370         tramp_alias     x30, tramp_exit_compat
 371         br      x30
 372 #endif
 373         .else
 374         eret
 375         .endif
 376         sb
 377         .endm
 378
 379         .macro  irq_stack_entry
 380         mov     x19, sp                 // preserve the original sp
 381
 382         /*
 383          * Compare sp with the base of the task stack.
 384          * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
 385          * and should switch to the irq stack.
 386          */
 387         ldr     x25, [tsk, TSK_STACK]
 388         eor     x25, x25, x19
 389         and     x25, x25, #~(THREAD_SIZE - 1)
 390         cbnz    x25, 9998f
 391
 392         ldr_this_cpu x25, irq_stack_ptr, x26
 393         mov     x26, #IRQ_STACK_SIZE
 394         add     x26, x25, x26
 395
 396         /* switch to the irq stack */
 397         mov     sp, x26
 398 9998:
 399         .endm
 400
 401         /*
 402          * x19 should be preserved between irq_stack_entry and
 403          * irq_stack_exit.
 404          */
 405         .macro  irq_stack_exit
 406         mov     sp, x19
 407         .endm
 408
 409 /* GPRs used by entry code */
 410 tsk     .req    x28             // current thread_info
 411
 412 /*
 413  * Interrupt handling.
 414  */
 415         .macro  irq_handler
 416         ldr_l   x1, handle_arch_irq
 417         mov     x0, sp
 418         irq_stack_entry
 419         blr     x1
 420         irq_stack_exit
 421         .endm
 422
 423 #ifdef CONFIG_ARM64_PSEUDO_NMI
 424         /*
 425          * Set res to 0 if irqs were unmasked in interrupted context.
 426          * Otherwise set res to non-0 value.
 427          */
 428         .macro  test_irqs_unmasked res:req, pmr:req
 429 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
 430         sub     \res, \pmr, #GIC_PRIO_IRQON
 431 alternative_else
 432         mov     \res, xzr
 433 alternative_endif
 434         .endm
 435 #endif
 436
 437         .text
 438
 439 /*
 440  * Exception vectors.
 441  */
 442         .pushsection ".entry.text", "ax"
 443
 444         .align  11
 445 ENTRY(vectors)
 446         kernel_ventry   1, sync_invalid                 // Synchronous EL1t
 447         kernel_ventry   1, irq_invalid                  // IRQ EL1t
 448         kernel_ventry   1, fiq_invalid                  // FIQ EL1t
 449         kernel_ventry   1, error_invalid                // Error EL1t
 450
 451         kernel_ventry   1, sync                         // Synchronous EL1h
 452         kernel_ventry   1, irq                          // IRQ EL1h
 453         kernel_ventry   1, fiq_invalid                  // FIQ EL1h
 454         kernel_ventry   1, error                        // Error EL1h
 455
 456         kernel_ventry   0, sync                         // Synchronous 64-bit EL0
 457         kernel_ventry   0, irq                          // IRQ 64-bit EL0
 458         kernel_ventry   0, fiq_invalid                  // FIQ 64-bit EL0
 459         kernel_ventry   0, error                        // Error 64-bit EL0
 460
 461 #ifdef CONFIG_COMPAT
 462         kernel_ventry   0, sync_compat, 32              // Synchronous 32-bit EL0
 463         kernel_ventry   0, irq_compat, 32               // IRQ 32-bit EL0
 464         kernel_ventry   0, fiq_invalid_compat, 32       // FIQ 32-bit EL0
 465         kernel_ventry   0, error_compat, 32             // Error 32-bit EL0
 466 #else
 467         kernel_ventry   0, sync_invalid, 32             // Synchronous 32-bit EL0
 468         kernel_ventry   0, irq_invalid, 32              // IRQ 32-bit EL0
 469         kernel_ventry   0, fiq_invalid, 32              // FIQ 32-bit EL0
 470         kernel_ventry   0, error_invalid, 32            // Error 32-bit EL0
 471 #endif
 472 END(vectors)
 473
 474 #ifdef CONFIG_VMAP_STACK
 475         /*
 476          * We detected an overflow in kernel_ventry, which switched to the
 477          * overflow stack. Stash the exception regs, and head to our overflow
 478          * handler.
 479          */
 480 __bad_stack:
 481         /* Restore the original x0 value */
 482         mrs     x0, tpidrro_el0
 483
 484         /*
 485          * Store the original GPRs to the new stack. The orginal SP (minus
 486          * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
 487          */
 488         sub     sp, sp, #S_FRAME_SIZE
 489         kernel_entry 1
 490         mrs     x0, tpidr_el0
 491         add     x0, x0, #S_FRAME_SIZE
 492         str     x0, [sp, #S_SP]
 493
 494         /* Stash the regs for handle_bad_stack */
 495         mov     x0, sp
 496
 497         /* Time to die */
 498         bl      handle_bad_stack
 499         ASM_BUG()
 500 #endif /* CONFIG_VMAP_STACK */
 501
 502 /*
 503  * Invalid mode handlers
 504  */
 505         .macro  inv_entry, el, reason, regsize = 64
 506         kernel_entry \el, \regsize
 507         mov     x0, sp
 508         mov     x1, #\reason
 509         mrs     x2, esr_el1
 510         bl      bad_mode
 511         ASM_BUG()
 512         .endm
 513
 514 el0_sync_invalid:
 515         inv_entry 0, BAD_SYNC
 516 ENDPROC(el0_sync_invalid)
 517
 518 el0_irq_invalid:
 519         inv_entry 0, BAD_IRQ
 520 ENDPROC(el0_irq_invalid)
 521
 522 el0_fiq_invalid:
 523         inv_entry 0, BAD_FIQ
 524 ENDPROC(el0_fiq_invalid)
 525
 526 el0_error_invalid:
 527         inv_entry 0, BAD_ERROR
 528 ENDPROC(el0_error_invalid)
 529
 530 #ifdef CONFIG_COMPAT
 531 el0_fiq_invalid_compat:
 532         inv_entry 0, BAD_FIQ, 32
 533 ENDPROC(el0_fiq_invalid_compat)
 534 #endif
 535
 536 el1_sync_invalid:
 537         inv_entry 1, BAD_SYNC
 538 ENDPROC(el1_sync_invalid)
 539
 540 el1_irq_invalid:
 541         inv_entry 1, BAD_IRQ
 542 ENDPROC(el1_irq_invalid)
 543
 544 el1_fiq_invalid:
 545         inv_entry 1, BAD_FIQ
 546 ENDPROC(el1_fiq_invalid)
 547
 548 el1_error_invalid:
 549         inv_entry 1, BAD_ERROR
 550 ENDPROC(el1_error_invalid)
 551
 552 /*
 553  * EL1 mode handlers.
 554  */
 555         .align  6
 556 el1_sync:
 557         kernel_entry 1
 558         mrs     x1, esr_el1                     // read the syndrome register
 559         lsr     x24, x1, #ESR_ELx_EC_SHIFT      // exception class
 560         cmp     x24, #ESR_ELx_EC_DABT_CUR       // data abort in EL1
 561         b.eq    el1_da
 562         cmp     x24, #ESR_ELx_EC_IABT_CUR       // instruction abort in EL1
 563         b.eq    el1_ia
 564         cmp     x24, #ESR_ELx_EC_SYS64          // configurable trap
 565         b.eq    el1_undef
 566         cmp     x24, #ESR_ELx_EC_SP_ALIGN       // stack alignment exception
 567         b.eq    el1_sp_pc
 568         cmp     x24, #ESR_ELx_EC_PC_ALIGN       // pc alignment exception
 569         b.eq    el1_sp_pc
 570         cmp     x24, #ESR_ELx_EC_UNKNOWN        // unknown exception in EL1
 571         b.eq    el1_undef
 572         cmp     x24, #ESR_ELx_EC_BREAKPT_CUR    // debug exception in EL1
 573         b.ge    el1_dbg
 574         b       el1_inv
 575
 576 el1_ia:
 577         /*
 578          * Fall through to the Data abort case
 579          */
 580 el1_da:
 581         /*
 582          * Data abort handling
 583          */
 584         mrs     x3, far_el1
 585         inherit_daif    pstate=x23, tmp=x2
 586         clear_address_tag x0, x3
 587         mov     x2, sp                          // struct pt_regs
 588         bl      do_mem_abort
 589
 590         kernel_exit 1
 591 el1_sp_pc:
 592         /*
 593          * Stack or PC alignment exception handling
 594          */
 595         mrs     x0, far_el1
 596         inherit_daif    pstate=x23, tmp=x2
 597         mov     x2, sp
 598         bl      do_sp_pc_abort
 599         ASM_BUG()
 600 el1_undef:
 601         /*
 602          * Undefined instruction
 603          */
 604         inherit_daif    pstate=x23, tmp=x2
 605         mov     x0, sp
 606         bl      do_undefinstr
 607         kernel_exit 1
 608 el1_dbg:
 609         /*
 610          * Debug exception handling
 611          */
 612         cmp     x24, #ESR_ELx_EC_BRK64          // if BRK64
 613         cinc    x24, x24, eq                    // set bit '0'
 614         tbz     x24, #0, el1_inv                // EL1 only
 615         mrs     x0, far_el1
 616         mov     x2, sp                          // struct pt_regs
 617         bl      do_debug_exception
 618         kernel_exit 1
 619 el1_inv:
 620         // TODO: add support for undefined instructions in kernel mode
 621         inherit_daif    pstate=x23, tmp=x2
 622         mov     x0, sp
 623         mov     x2, x1
 624         mov     x1, #BAD_SYNC
 625         bl      bad_mode
 626         ASM_BUG()
 627 ENDPROC(el1_sync)
 628
 629         .align  6
 630 el1_irq:
 631         kernel_entry 1
 632         enable_da_f
 633
 634 #ifdef CONFIG_ARM64_PSEUDO_NMI
 635 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
 636         ldr     x20, [sp, #S_PMR_SAVE]
 637 alternative_else_nop_endif
 638         test_irqs_unmasked      res=x0, pmr=x20
 639         cbz     x0, 1f
 640         bl      asm_nmi_enter
 641 1:
 642 #endif
 643
 644 #ifdef CONFIG_TRACE_IRQFLAGS
 645         bl      trace_hardirqs_off
 646 #endif
 647
 648         irq_handler
 649
 650 #ifdef CONFIG_PREEMPT
 651         ldr     x24, [tsk, #TSK_TI_PREEMPT]     // get preempt count
 652 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
 653         /*
 654          * DA_F were cleared at start of handling. If anything is set in DAIF,
 655          * we come back from an NMI, so skip preemption
 656          */
 657         mrs     x0, daif
 658         orr     x24, x24, x0
 659 alternative_else_nop_endif
 660         cbnz    x24, 1f                         // preempt count != 0 || NMI return path
 661         bl      preempt_schedule_irq            // irq en/disable is done inside
 662 1:
 663 #endif
 664
 665 #ifdef CONFIG_ARM64_PSEUDO_NMI
 666         /*
 667          * if IRQs were disabled when we received the interrupt, we have an NMI
 668          * and we are not re-enabling interrupt upon eret. Skip tracing.
 669          */
 670         test_irqs_unmasked      res=x0, pmr=x20
 671         cbz     x0, 1f
 672         bl      asm_nmi_exit
 673 1:
 674 #endif
 675
 676 #ifdef CONFIG_TRACE_IRQFLAGS
 677 #ifdef CONFIG_ARM64_PSEUDO_NMI
 678         test_irqs_unmasked      res=x0, pmr=x20
 679         cbnz    x0, 1f
 680 #endif
 681         bl      trace_hardirqs_on
 682 1:
 683 #endif
 684
 685         kernel_exit 1
 686 ENDPROC(el1_irq)
 687
 688 /*
 689  * EL0 mode handlers.
 690  */
 691         .align  6
 692 el0_sync:
 693         kernel_entry 0
 694         mrs     x25, esr_el1                    // read the syndrome register
 695         lsr     x24, x25, #ESR_ELx_EC_SHIFT     // exception class
 696         cmp     x24, #ESR_ELx_EC_SVC64          // SVC in 64-bit state
 697         b.eq    el0_svc
 698         cmp     x24, #ESR_ELx_EC_DABT_LOW       // data abort in EL0
 699         b.eq    el0_da
 700         cmp     x24, #ESR_ELx_EC_IABT_LOW       // instruction abort in EL0
 701         b.eq    el0_ia
 702         cmp     x24, #ESR_ELx_EC_FP_ASIMD       // FP/ASIMD access
 703         b.eq    el0_fpsimd_acc
 704         cmp     x24, #ESR_ELx_EC_SVE            // SVE access
 705         b.eq    el0_sve_acc
 706         cmp     x24, #ESR_ELx_EC_FP_EXC64       // FP/ASIMD exception
 707         b.eq    el0_fpsimd_exc
 708         cmp     x24, #ESR_ELx_EC_SYS64          // configurable trap
 709         ccmp    x24, #ESR_ELx_EC_WFx, #4, ne
 710         b.eq    el0_sys
 711         cmp     x24, #ESR_ELx_EC_SP_ALIGN       // stack alignment exception
 712         b.eq    el0_sp_pc
 713         cmp     x24, #ESR_ELx_EC_PC_ALIGN       // pc alignment exception
 714         b.eq    el0_sp_pc
 715         cmp     x24, #ESR_ELx_EC_UNKNOWN        // unknown exception in EL0
 716         b.eq    el0_undef
 717         cmp     x24, #ESR_ELx_EC_BREAKPT_LOW    // debug exception in EL0
 718         b.ge    el0_dbg
 719         b       el0_inv
 720
 721 #ifdef CONFIG_COMPAT
 722         .align  6
 723 el0_sync_compat:
 724         kernel_entry 0, 32
 725         mrs     x25, esr_el1                    // read the syndrome register
 726         lsr     x24, x25, #ESR_ELx_EC_SHIFT     // exception class
 727         cmp     x24, #ESR_ELx_EC_SVC32          // SVC in 32-bit state
 728         b.eq    el0_svc_compat
 729         cmp     x24, #ESR_ELx_EC_DABT_LOW       // data abort in EL0
 730         b.eq    el0_da
 731         cmp     x24, #ESR_ELx_EC_IABT_LOW       // instruction abort in EL0
 732         b.eq    el0_ia
 733         cmp     x24, #ESR_ELx_EC_FP_ASIMD       // FP/ASIMD access
 734         b.eq    el0_fpsimd_acc
 735         cmp     x24, #ESR_ELx_EC_FP_EXC32       // FP/ASIMD exception
 736         b.eq    el0_fpsimd_exc
 737         cmp     x24, #ESR_ELx_EC_PC_ALIGN       // pc alignment exception
 738         b.eq    el0_sp_pc
 739         cmp     x24, #ESR_ELx_EC_UNKNOWN        // unknown exception in EL0
 740         b.eq    el0_undef
 741         cmp     x24, #ESR_ELx_EC_CP15_32        // CP15 MRC/MCR trap
 742         b.eq    el0_cp15
 743         cmp     x24, #ESR_ELx_EC_CP15_64        // CP15 MRRC/MCRR trap
 744         b.eq    el0_cp15
 745         cmp     x24, #ESR_ELx_EC_CP14_MR        // CP14 MRC/MCR trap
 746         b.eq    el0_undef
 747         cmp     x24, #ESR_ELx_EC_CP14_LS        // CP14 LDC/STC trap
 748         b.eq    el0_undef
 749         cmp     x24, #ESR_ELx_EC_CP14_64        // CP14 MRRC/MCRR trap
 750         b.eq    el0_undef
 751         cmp     x24, #ESR_ELx_EC_BREAKPT_LOW    // debug exception in EL0
 752         b.ge    el0_dbg
 753         b       el0_inv
 754 el0_svc_compat:
 755         mov     x0, sp
 756         bl      el0_svc_compat_handler
 757         b       ret_to_user
 758
 759         .align  6
 760 el0_irq_compat:
 761         kernel_entry 0, 32
 762         b       el0_irq_naked
 763
 764 el0_error_compat:
 765         kernel_entry 0, 32
 766         b       el0_error_naked
 767
 768 el0_cp15:
 769         /*
 770          * Trapped CP15 (MRC, MCR, MRRC, MCRR) instructions
 771          */
 772         enable_daif
 773         ct_user_exit
 774         mov     x0, x25
 775         mov     x1, sp
 776         bl      do_cp15instr
 777         b       ret_to_user
 778 #endif
 779
 780 el0_da:
 781         /*
 782          * Data abort handling
 783          */
 784         mrs     x26, far_el1
 785         enable_daif
 786         ct_user_exit
 787         clear_address_tag x0, x26
 788         mov     x1, x25
 789         mov     x2, sp
 790         bl      do_mem_abort
 791         b       ret_to_user
 792 el0_ia:
 793         /*
 794          * Instruction abort handling
 795          */
 796         mrs     x26, far_el1
 797         enable_da_f
 798 #ifdef CONFIG_TRACE_IRQFLAGS
 799         bl      trace_hardirqs_off
 800 #endif
 801         ct_user_exit
 802         mov     x0, x26
 803         mov     x1, x25
 804         mov     x2, sp
 805         bl      do_el0_ia_bp_hardening
 806         b       ret_to_user
 807 el0_fpsimd_acc:
 808         /*
 809          * Floating Point or Advanced SIMD access
 810          */
 811         enable_daif
 812         ct_user_exit
 813         mov     x0, x25
 814         mov     x1, sp
 815         bl      do_fpsimd_acc
 816         b       ret_to_user
 817 el0_sve_acc:
 818         /*
 819          * Scalable Vector Extension access
 820          */
 821         enable_daif
 822         ct_user_exit
 823         mov     x0, x25
 824         mov     x1, sp
 825         bl      do_sve_acc
 826         b       ret_to_user
 827 el0_fpsimd_exc:
 828         /*
 829          * Floating Point, Advanced SIMD or SVE exception
 830          */
 831         enable_daif
 832         ct_user_exit
 833         mov     x0, x25
 834         mov     x1, sp
 835         bl      do_fpsimd_exc
 836         b       ret_to_user
 837 el0_sp_pc:
 838         /*
 839          * Stack or PC alignment exception handling
 840          */
 841         mrs     x26, far_el1
 842         enable_da_f
 843 #ifdef CONFIG_TRACE_IRQFLAGS
 844         bl      trace_hardirqs_off
 845 #endif
 846         ct_user_exit
 847         mov     x0, x26
 848         mov     x1, x25
 849         mov     x2, sp
 850         bl      do_sp_pc_abort
 851         b       ret_to_user
 852 el0_undef:
 853         /*
 854          * Undefined instruction
 855          */
 856         enable_daif
 857         ct_user_exit
 858         mov     x0, sp
 859         bl      do_undefinstr
 860         b       ret_to_user
 861 el0_sys:
 862         /*
 863          * System instructions, for trapped cache maintenance instructions
 864          */
 865         enable_daif
 866         ct_user_exit
 867         mov     x0, x25
 868         mov     x1, sp
 869         bl      do_sysinstr
 870         b       ret_to_user
 871 el0_dbg:
 872         /*
 873          * Debug exception handling
 874          */
 875         tbnz    x24, #0, el0_inv                // EL0 only
 876         mrs     x0, far_el1
 877         mov     x1, x25
 878         mov     x2, sp
 879         bl      do_debug_exception
 880         enable_da_f
 881         ct_user_exit
 882         b       ret_to_user
 883 el0_inv:
 884         enable_daif
 885         ct_user_exit
 886         mov     x0, sp
 887         mov     x1, #BAD_SYNC
 888         mov     x2, x25
 889         bl      bad_el0_sync
 890         b       ret_to_user
 891 ENDPROC(el0_sync)
 892
 893         .align  6
 894 el0_irq:
 895         kernel_entry 0
 896 el0_irq_naked:
 897         enable_da_f
 898 #ifdef CONFIG_TRACE_IRQFLAGS
 899         bl      trace_hardirqs_off
 900 #endif
 901
 902         ct_user_exit
 903 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 904         tbz     x22, #55, 1f
 905         bl      do_el0_irq_bp_hardening
 906 1:
 907 #endif
 908         irq_handler
 909
 910 #ifdef CONFIG_TRACE_IRQFLAGS
 911         bl      trace_hardirqs_on
 912 #endif
 913         b       ret_to_user
 914 ENDPROC(el0_irq)
 915
 916 el1_error:
 917         kernel_entry 1
 918         mrs     x1, esr_el1
 919         enable_dbg
 920         mov     x0, sp
 921         bl      do_serror
 922         kernel_exit 1
 923 ENDPROC(el1_error)
 924
 925 el0_error:
 926         kernel_entry 0
 927 el0_error_naked:
 928         mrs     x1, esr_el1
 929         enable_dbg
 930         mov     x0, sp
 931         bl      do_serror
 932         enable_da_f
 933         ct_user_exit
 934         b       ret_to_user
 935 ENDPROC(el0_error)
 936
 937 /*
 938  * Ok, we need to do extra processing, enter the slow path.
 939  */
 940 work_pending:
 941         mov     x0, sp                          // 'regs'
 942         bl      do_notify_resume
 943 #ifdef CONFIG_TRACE_IRQFLAGS
 944         bl      trace_hardirqs_on               // enabled while in userspace
 945 #endif
 946         ldr     x1, [tsk, #TSK_TI_FLAGS]        // re-check for single-step
 947         b       finish_ret_to_user
 948 /*
 949  * "slow" syscall return path.
 950  */
 951 ret_to_user:
 952         disable_daif
 953         ldr     x1, [tsk, #TSK_TI_FLAGS]
 954         and     x2, x1, #_TIF_WORK_MASK
 955         cbnz    x2, work_pending
 956 finish_ret_to_user:
 957         enable_step_tsk x1, x2
 958 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
 959         bl      stackleak_erase
 960 #endif
 961         kernel_exit 0
 962 ENDPROC(ret_to_user)
 963
 964 /*
 965  * SVC handler.
 966  */
 967         .align  6
 968 el0_svc:
 969         mov     x0, sp
 970         bl      el0_svc_handler
 971         b       ret_to_user
 972 ENDPROC(el0_svc)
 973
 974         .popsection                             // .entry.text
 975
 976 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 977 /*
 978  * Exception vectors trampoline.
 979  */
 980         .pushsection ".entry.tramp.text", "ax"
 981
 982         .macro tramp_map_kernel, tmp
 983         mrs     \tmp, ttbr1_el1
 984         add     \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
 985         bic     \tmp, \tmp, #USER_ASID_FLAG
 986         msr     ttbr1_el1, \tmp
 987 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
 988 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
 989         /* ASID already in \tmp[63:48] */
 990         movk    \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
 991         movk    \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
 992         /* 2MB boundary containing the vectors, so we nobble the walk cache */
 993         movk    \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
 994         isb
 995         tlbi    vae1, \tmp
 996         dsb     nsh
 997 alternative_else_nop_endif
 998 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
 999         .endm
1000
1001         .macro tramp_unmap_kernel, tmp
1002         mrs     \tmp, ttbr1_el1
1003         sub     \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
1004         orr     \tmp, \tmp, #USER_ASID_FLAG
1005         msr     ttbr1_el1, \tmp
1006         /*
1007          * We avoid running the post_ttbr_update_workaround here because
1008          * it's only needed by Cavium ThunderX, which requires KPTI to be
1009          * disabled.
1010          */
1011         .endm
1012
1013         .macro tramp_ventry, regsize = 64
1014         .align  7
1015 1:
1016         .if     \regsize == 64
1017         msr     tpidrro_el0, x30        // Restored in kernel_ventry
1018         .endif
1019         /*
1020          * Defend against branch aliasing attacks by pushing a dummy
1021          * entry onto the return stack and using a RET instruction to
1022          * enter the full-fat kernel vectors.
1023          */
1024         bl      2f
1025         b       .
1026 2:
1027         tramp_map_kernel        x30
1028 #ifdef CONFIG_RANDOMIZE_BASE
1029         adr     x30, tramp_vectors + PAGE_SIZE
1030 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
1031         ldr     x30, [x30]
1032 #else
1033         ldr     x30, =vectors
1034 #endif
1035         prfm    plil1strm, [x30, #(1b - tramp_vectors)]
1036         msr     vbar_el1, x30
1037         add     x30, x30, #(1b - tramp_vectors)
1038         isb
1039         ret
1040         .endm
1041
1042         .macro tramp_exit, regsize = 64
1043         adr     x30, tramp_vectors
1044         msr     vbar_el1, x30
1045         tramp_unmap_kernel      x30
1046         .if     \regsize == 64
1047         mrs     x30, far_el1
1048         .endif
1049         eret
1050         sb
1051         .endm
1052
1053         .align  11
1054 ENTRY(tramp_vectors)
1055         .space  0x400
1056
1057         tramp_ventry
1058         tramp_ventry
1059         tramp_ventry
1060         tramp_ventry
1061
1062         tramp_ventry    32
1063         tramp_ventry    32
1064         tramp_ventry    32
1065         tramp_ventry    32
1066 END(tramp_vectors)
1067
1068 ENTRY(tramp_exit_native)
1069         tramp_exit
1070 END(tramp_exit_native)
1071
1072 ENTRY(tramp_exit_compat)
1073         tramp_exit      32
1074 END(tramp_exit_compat)
1075
1076         .ltorg
1077         .popsection                             // .entry.tramp.text
1078 #ifdef CONFIG_RANDOMIZE_BASE
1079         .pushsection ".rodata", "a"
1080         .align PAGE_SHIFT
1081         .globl  __entry_tramp_data_start
1082 __entry_tramp_data_start:
1083         .quad   vectors
1084         .popsection                             // .rodata
1085 #endif /* CONFIG_RANDOMIZE_BASE */
1086 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1087
1088 /*
1089  * Register switch for AArch64. The callee-saved registers need to be saved
1090  * and restored. On entry:
1091  *   x0 = previous task_struct (must be preserved across the switch)
1092  *   x1 = next task_struct
1093  * Previous and next are guaranteed not to be the same.
1094  *
1095  */
1096 ENTRY(cpu_switch_to)
1097         mov     x10, #THREAD_CPU_CONTEXT
1098         add     x8, x0, x10
1099         mov     x9, sp
1100         stp     x19, x20, [x8], #16             // store callee-saved registers
1101         stp     x21, x22, [x8], #16
1102         stp     x23, x24, [x8], #16
1103         stp     x25, x26, [x8], #16
1104         stp     x27, x28, [x8], #16
1105         stp     x29, x9, [x8], #16
1106         str     lr, [x8]
1107         add     x8, x1, x10
1108         ldp     x19, x20, [x8], #16             // restore callee-saved registers
1109         ldp     x21, x22, [x8], #16
1110         ldp     x23, x24, [x8], #16
1111         ldp     x25, x26, [x8], #16
1112         ldp     x27, x28, [x8], #16
1113         ldp     x29, x9, [x8], #16
1114         ldr     lr, [x8]
1115         mov     sp, x9
1116         msr     sp_el0, x1
1117         ret
1118 ENDPROC(cpu_switch_to)
1119 NOKPROBE(cpu_switch_to)
1120
1121 /*
1122  * This is how we return from a fork.
1123  */
1124 ENTRY(ret_from_fork)
1125         bl      schedule_tail
1126         cbz     x19, 1f                         // not a kernel thread
1127         mov     x0, x20
1128         blr     x19
1129 1:      get_current_task tsk
1130         b       ret_to_user
1131 ENDPROC(ret_from_fork)
1132 NOKPROBE(ret_from_fork)
1133
1134 #ifdef CONFIG_ARM_SDE_INTERFACE
1135
1136 #include <asm/sdei.h>
1137 #include <uapi/linux/arm_sdei.h>
1138
1139 .macro sdei_handler_exit exit_mode
1140         /* On success, this call never returns... */
1141         cmp     \exit_mode, #SDEI_EXIT_SMC
1142         b.ne    99f
1143         smc     #0
1144         b       .
1145 99:     hvc     #0
1146         b       .
1147 .endm
1148
1149 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1150 /*
1151  * The regular SDEI entry point may have been unmapped along with the rest of
1152  * the kernel. This trampoline restores the kernel mapping to make the x1 memory
1153  * argument accessible.
1154  *
1155  * This clobbers x4, __sdei_handler() will restore this from firmware's
1156  * copy.
1157  */
1158 .ltorg
1159 .pushsection ".entry.tramp.text", "ax"
1160 ENTRY(__sdei_asm_entry_trampoline)
1161         mrs     x4, ttbr1_el1
1162         tbz     x4, #USER_ASID_BIT, 1f
1163
1164         tramp_map_kernel tmp=x4
1165         isb
1166         mov     x4, xzr
1167
1168         /*
1169          * Use reg->interrupted_regs.addr_limit to remember whether to unmap
1170          * the kernel on exit.
1171          */
1172 1:      str     x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
1173
1174 #ifdef CONFIG_RANDOMIZE_BASE
1175         adr     x4, tramp_vectors + PAGE_SIZE
1176         add     x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
1177         ldr     x4, [x4]
1178 #else
1179         ldr     x4, =__sdei_asm_handler
1180 #endif
1181         br      x4
1182 ENDPROC(__sdei_asm_entry_trampoline)
1183 NOKPROBE(__sdei_asm_entry_trampoline)
1184
1185 /*
1186  * Make the exit call and restore the original ttbr1_el1
1187  *
1188  * x0 & x1: setup for the exit API call
1189  * x2: exit_mode
1190  * x4: struct sdei_registered_event argument from registration time.
1191  */
1192 ENTRY(__sdei_asm_exit_trampoline)
1193         ldr     x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
1194         cbnz    x4, 1f
1195
1196         tramp_unmap_kernel      tmp=x4
1197
1198 1:      sdei_handler_exit exit_mode=x2
1199 ENDPROC(__sdei_asm_exit_trampoline)
1200 NOKPROBE(__sdei_asm_exit_trampoline)
1201         .ltorg
1202 .popsection             // .entry.tramp.text
1203 #ifdef CONFIG_RANDOMIZE_BASE
1204 .pushsection ".rodata", "a"
1205 __sdei_asm_trampoline_next_handler:
1206         .quad   __sdei_asm_handler
1207 .popsection             // .rodata
1208 #endif /* CONFIG_RANDOMIZE_BASE */
1209 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1210
1211 /*
1212  * Software Delegated Exception entry point.
1213  *
1214  * x0: Event number
1215  * x1: struct sdei_registered_event argument from registration time.
1216  * x2: interrupted PC
1217  * x3: interrupted PSTATE
1218  * x4: maybe clobbered by the trampoline
1219  *
1220  * Firmware has preserved x0->x17 for us, we must save/restore the rest to
1221  * follow SMC-CC. We save (or retrieve) all the registers as the handler may
1222  * want them.
1223  */
1224 ENTRY(__sdei_asm_handler)
1225         stp     x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
1226         stp     x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
1227         stp     x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
1228         stp     x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
1229         stp     x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
1230         stp     x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
1231         stp     x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
1232         stp     x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
1233         stp     x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
1234         stp     x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
1235         stp     x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
1236         stp     x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
1237         stp     x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
1238         stp     x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1239         mov     x4, sp
1240         stp     lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
1241
1242         mov     x19, x1
1243
1244 #ifdef CONFIG_VMAP_STACK
1245         /*
1246          * entry.S may have been using sp as a scratch register, find whether
1247          * this is a normal or critical event and switch to the appropriate
1248          * stack for this CPU.
1249          */
1250         ldrb    w4, [x19, #SDEI_EVENT_PRIORITY]
1251         cbnz    w4, 1f
1252         ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
1253         b       2f
1254 1:      ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
1255 2:      mov     x6, #SDEI_STACK_SIZE
1256         add     x5, x5, x6
1257         mov     sp, x5
1258 #endif
1259
1260         /*
1261          * We may have interrupted userspace, or a guest, or exit-from or
1262          * return-to either of these. We can't trust sp_el0, restore it.
1263          */
1264         mrs     x28, sp_el0
1265         ldr_this_cpu    dst=x0, sym=__entry_task, tmp=x1
1266         msr     sp_el0, x0
1267
1268         /* If we interrupted the kernel point to the previous stack/frame. */
1269         and     x0, x3, #0xc
1270         mrs     x1, CurrentEL
1271         cmp     x0, x1
1272         csel    x29, x29, xzr, eq       // fp, or zero
1273         csel    x4, x2, xzr, eq         // elr, or zero
1274
1275         stp     x29, x4, [sp, #-16]!
1276         mov     x29, sp
1277
1278         add     x0, x19, #SDEI_EVENT_INTREGS
1279         mov     x1, x19
1280         bl      __sdei_handler
1281
1282         msr     sp_el0, x28
1283         /* restore regs >x17 that we clobbered */
1284         mov     x4, x19         // keep x4 for __sdei_asm_exit_trampoline
1285         ldp     x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
1286         ldp     x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
1287         ldp     lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
1288         mov     sp, x1
1289
1290         mov     x1, x0                  // address to complete_and_resume
1291         /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
1292         cmp     x0, #1
1293         mov_q   x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1294         mov_q   x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1295         csel    x0, x2, x3, ls
1296
1297         ldr_l   x2, sdei_exit_mode
1298
1299 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
1300         sdei_handler_exit exit_mode=x2
1301 alternative_else_nop_endif
1302
1303 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1304         tramp_alias     dst=x5, sym=__sdei_asm_exit_trampoline
1305         br      x5
1306 #endif
1307 ENDPROC(__sdei_asm_handler)
1308 NOKPROBE(__sdei_asm_handler)
1309 #endif /* CONFIG_ARM_SDE_INTERFACE */