arch/arm64/kernel/head.S

   1 /*
   2  * Low-level CPU initialisation
   3  * Based on arch/arm/kernel/head.S
   4  *
   5  * Copyright (C) 1994-2002 Russell King
   6  * Copyright (C) 2003-2012 ARM Ltd.
   7  * Authors:     Catalin Marinas <catalin.marinas@arm.com>
   8  *              Will Deacon <will.deacon@arm.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/linkage.h>
  24 #include <linux/init.h>
  25 #include <linux/irqchip/arm-gic-v3.h>
  26
  27 #include <asm/assembler.h>
  28 #include <asm/boot.h>
  29 #include <asm/ptrace.h>
  30 #include <asm/asm-offsets.h>
  31 #include <asm/cache.h>
  32 #include <asm/cputype.h>
  33 #include <asm/elf.h>
  34 #include <asm/kernel-pgtable.h>
  35 #include <asm/kvm_arm.h>
  36 #include <asm/memory.h>
  37 #include <asm/pgtable-hwdef.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/page.h>
  40 #include <asm/smp.h>
  41 #include <asm/sysreg.h>
  42 #include <asm/thread_info.h>
  43 #include <asm/virt.h>
  44
  45 #define __PHYS_OFFSET   (KERNEL_START - TEXT_OFFSET)
  46
  47 #if (TEXT_OFFSET & 0xfff) != 0
  48 #error TEXT_OFFSET must be at least 4KB aligned
  49 #elif (PAGE_OFFSET & 0x1fffff) != 0
  50 #error PAGE_OFFSET must be at least 2MB aligned
  51 #elif TEXT_OFFSET > 0x1fffff
  52 #error TEXT_OFFSET must be less than 2MB
  53 #endif
  54
  55 /*
  56  * Kernel startup entry point.
  57  * ---------------------------
  58  *
  59  * The requirements are:
  60  *   MMU = off, D-cache = off, I-cache = on or off,
  61  *   x0 = physical address to the FDT blob.
  62  *
  63  * This code is mostly position independent so you call this at
  64  * __pa(PAGE_OFFSET + TEXT_OFFSET).
  65  *
  66  * Note that the callee-saved registers are used for storing variables
  67  * that are useful before the MMU is enabled. The allocations are described
  68  * in the entry routines.
  69  */
  70         __HEAD
  71 _head:
  72         /*
  73          * DO NOT MODIFY. Image header expected by Linux boot-loaders.
  74          */
  75 #ifdef CONFIG_EFI
  76         /*
  77          * This add instruction has no meaningful effect except that
  78          * its opcode forms the magic "MZ" signature required by UEFI.
  79          */
  80         add     x13, x18, #0x16
  81         b       stext
  82 #else
  83         b       stext                           // branch to kernel start, magic
  84         .long   0                               // reserved
  85 #endif
  86         le64sym _kernel_offset_le               // Image load offset from start of RAM, little-endian
  87         le64sym _kernel_size_le                 // Effective size of kernel image, little-endian
  88         le64sym _kernel_flags_le                // Informative flags, little-endian
  89         .quad   0                               // reserved
  90         .quad   0                               // reserved
  91         .quad   0                               // reserved
  92         .byte   0x41                            // Magic number, "ARM\x64"
  93         .byte   0x52
  94         .byte   0x4d
  95         .byte   0x64
  96 #ifdef CONFIG_EFI
  97         .long   pe_header - _head               // Offset to the PE header.
  98 #else
  99         .word   0                               // reserved
 100 #endif
 101
 102 #ifdef CONFIG_EFI
 103         .align 3
 104 pe_header:
 105         .ascii  "PE"
 106         .short  0
 107 coff_header:
 108         .short  0xaa64                          // AArch64
 109         .short  2                               // nr_sections
 110         .long   0                               // TimeDateStamp
 111         .long   0                               // PointerToSymbolTable
 112         .long   1                               // NumberOfSymbols
 113         .short  section_table - optional_header // SizeOfOptionalHeader
 114         .short  0x206                           // Characteristics.
 115                                                 // IMAGE_FILE_DEBUG_STRIPPED |
 116                                                 // IMAGE_FILE_EXECUTABLE_IMAGE |
 117                                                 // IMAGE_FILE_LINE_NUMS_STRIPPED
 118 optional_header:
 119         .short  0x20b                           // PE32+ format
 120         .byte   0x02                            // MajorLinkerVersion
 121         .byte   0x14                            // MinorLinkerVersion
 122         .long   _end - efi_header_end           // SizeOfCode
 123         .long   0                               // SizeOfInitializedData
 124         .long   0                               // SizeOfUninitializedData
 125         .long   __efistub_entry - _head         // AddressOfEntryPoint
 126         .long   efi_header_end - _head          // BaseOfCode
 127
 128 extra_header_fields:
 129         .quad   0                               // ImageBase
 130         .long   0x1000                          // SectionAlignment
 131         .long   PECOFF_FILE_ALIGNMENT           // FileAlignment
 132         .short  0                               // MajorOperatingSystemVersion
 133         .short  0                               // MinorOperatingSystemVersion
 134         .short  0                               // MajorImageVersion
 135         .short  0                               // MinorImageVersion
 136         .short  0                               // MajorSubsystemVersion
 137         .short  0                               // MinorSubsystemVersion
 138         .long   0                               // Win32VersionValue
 139
 140         .long   _end - _head                    // SizeOfImage
 141
 142         // Everything before the kernel image is considered part of the header
 143         .long   efi_header_end - _head          // SizeOfHeaders
 144         .long   0                               // CheckSum
 145         .short  0xa                             // Subsystem (EFI application)
 146         .short  0                               // DllCharacteristics
 147         .quad   0                               // SizeOfStackReserve
 148         .quad   0                               // SizeOfStackCommit
 149         .quad   0                               // SizeOfHeapReserve
 150         .quad   0                               // SizeOfHeapCommit
 151         .long   0                               // LoaderFlags
 152         .long   0x6                             // NumberOfRvaAndSizes
 153
 154         .quad   0                               // ExportTable
 155         .quad   0                               // ImportTable
 156         .quad   0                               // ResourceTable
 157         .quad   0                               // ExceptionTable
 158         .quad   0                               // CertificationTable
 159         .quad   0                               // BaseRelocationTable
 160
 161         // Section table
 162 section_table:
 163
 164         /*
 165          * The EFI application loader requires a relocation section
 166          * because EFI applications must be relocatable.  This is a
 167          * dummy section as far as we are concerned.
 168          */
 169         .ascii  ".reloc"
 170         .byte   0
 171         .byte   0                       // end of 0 padding of section name
 172         .long   0
 173         .long   0
 174         .long   0                       // SizeOfRawData
 175         .long   0                       // PointerToRawData
 176         .long   0                       // PointerToRelocations
 177         .long   0                       // PointerToLineNumbers
 178         .short  0                       // NumberOfRelocations
 179         .short  0                       // NumberOfLineNumbers
 180         .long   0x42100040              // Characteristics (section flags)
 181
 182
 183         .ascii  ".text"
 184         .byte   0
 185         .byte   0
 186         .byte   0                       // end of 0 padding of section name
 187         .long   _end - efi_header_end   // VirtualSize
 188         .long   efi_header_end - _head  // VirtualAddress
 189         .long   _edata - efi_header_end // SizeOfRawData
 190         .long   efi_header_end - _head  // PointerToRawData
 191
 192         .long   0               // PointerToRelocations (0 for executables)
 193         .long   0               // PointerToLineNumbers (0 for executables)
 194         .short  0               // NumberOfRelocations  (0 for executables)
 195         .short  0               // NumberOfLineNumbers  (0 for executables)
 196         .long   0xe0500020      // Characteristics (section flags)
 197
 198         /*
 199          * EFI will load .text onwards at the 4k section alignment
 200          * described in the PE/COFF header. To ensure that instruction
 201          * sequences using an adrp and a :lo12: immediate will function
 202          * correctly at this alignment, we must ensure that .text is
 203          * placed at a 4k boundary in the Image to begin with.
 204          */
 205         .align 12
 206 efi_header_end:
 207 #endif
 208
 209         __INIT
 210
 211 ENTRY(stext)
 212         bl      preserve_boot_args
 213         bl      el2_setup                       // Drop to EL1, w0=cpu_boot_mode
 214         adrp    x23, __PHYS_OFFSET
 215         and     x23, x23, MIN_KIMG_ALIGN - 1    // KASLR offset, defaults to 0
 216         bl      set_cpu_boot_mode_flag
 217         bl      __create_page_tables
 218         /*
 219          * The following calls CPU setup code, see arch/arm64/mm/proc.S for
 220          * details.
 221          * On return, the CPU will be ready for the MMU to be turned on and
 222          * the TCR will have been set.
 223          */
 224         bl      __cpu_setup                     // initialise processor
 225         b       __primary_switch
 226 ENDPROC(stext)
 227
 228 /*
 229  * Preserve the arguments passed by the bootloader in x0 .. x3
 230  */
 231 preserve_boot_args:
 232         mov     x21, x0                         // x21=FDT
 233
 234         adr_l   x0, boot_args                   // record the contents of
 235         stp     x21, x1, [x0]                   // x0 .. x3 at kernel entry
 236         stp     x2, x3, [x0, #16]
 237
 238         dmb     sy                              // needed before dc ivac with
 239                                                 // MMU off
 240
 241         add     x1, x0, #0x20                   // 4 x 8 bytes
 242         b       __inval_cache_range             // tail call
 243 ENDPROC(preserve_boot_args)
 244
 245 /*
 246  * Macro to create a table entry to the next page.
 247  *
 248  *      tbl:    page table address
 249  *      virt:   virtual address
 250  *      shift:  #imm page table shift
 251  *      ptrs:   #imm pointers per table page
 252  *
 253  * Preserves:   virt
 254  * Corrupts:    tmp1, tmp2
 255  * Returns:     tbl -> next level table page address
 256  */
 257         .macro  create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
 258         lsr     \tmp1, \virt, #\shift
 259         and     \tmp1, \tmp1, #\ptrs - 1        // table index
 260         add     \tmp2, \tbl, #PAGE_SIZE
 261         orr     \tmp2, \tmp2, #PMD_TYPE_TABLE   // address of next table and entry type
 262         str     \tmp2, [\tbl, \tmp1, lsl #3]
 263         add     \tbl, \tbl, #PAGE_SIZE          // next level table page
 264         .endm
 265
 266 /*
 267  * Macro to populate the PGD (and possibily PUD) for the corresponding
 268  * block entry in the next level (tbl) for the given virtual address.
 269  *
 270  * Preserves:   tbl, next, virt
 271  * Corrupts:    tmp1, tmp2
 272  */
 273         .macro  create_pgd_entry, tbl, virt, tmp1, tmp2
 274         create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
 275 #if SWAPPER_PGTABLE_LEVELS > 3
 276         create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2
 277 #endif
 278 #if SWAPPER_PGTABLE_LEVELS > 2
 279         create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
 280 #endif
 281         .endm
 282
 283 /*
 284  * Macro to populate block entries in the page table for the start..end
 285  * virtual range (inclusive).
 286  *
 287  * Preserves:   tbl, flags
 288  * Corrupts:    phys, start, end, pstate
 289  */
 290         .macro  create_block_map, tbl, flags, phys, start, end
 291         lsr     \phys, \phys, #SWAPPER_BLOCK_SHIFT
 292         lsr     \start, \start, #SWAPPER_BLOCK_SHIFT
 293         and     \start, \start, #PTRS_PER_PTE - 1       // table index
 294         orr     \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT  // table entry
 295         lsr     \end, \end, #SWAPPER_BLOCK_SHIFT
 296         and     \end, \end, #PTRS_PER_PTE - 1           // table end index
 297 9999:   str     \phys, [\tbl, \start, lsl #3]           // store the entry
 298         add     \start, \start, #1                      // next entry
 299         add     \phys, \phys, #SWAPPER_BLOCK_SIZE               // next block
 300         cmp     \start, \end
 301         b.ls    9999b
 302         .endm
 303
 304 /*
 305  * Setup the initial page tables. We only setup the barest amount which is
 306  * required to get the kernel running. The following sections are required:
 307  *   - identity mapping to enable the MMU (low address, TTBR0)
 308  *   - first few MB of the kernel linear mapping to jump to once the MMU has
 309  *     been enabled
 310  */
 311 __create_page_tables:
 312         mov     x28, lr
 313
 314         /*
 315          * Invalidate the idmap and swapper page tables to avoid potential
 316          * dirty cache lines being evicted.
 317          */
 318         adrp    x0, idmap_pg_dir
 319         adrp    x1, swapper_pg_dir + SWAPPER_DIR_SIZE
 320         bl      __inval_cache_range
 321
 322         /*
 323          * Clear the idmap and swapper page tables.
 324          */
 325         adrp    x0, idmap_pg_dir
 326         adrp    x6, swapper_pg_dir + SWAPPER_DIR_SIZE
 327 1:      stp     xzr, xzr, [x0], #16
 328         stp     xzr, xzr, [x0], #16
 329         stp     xzr, xzr, [x0], #16
 330         stp     xzr, xzr, [x0], #16
 331         cmp     x0, x6
 332         b.lo    1b
 333
 334         mov     x7, SWAPPER_MM_MMUFLAGS
 335
 336         /*
 337          * Create the identity mapping.
 338          */
 339         adrp    x0, idmap_pg_dir
 340         adrp    x3, __idmap_text_start          // __pa(__idmap_text_start)
 341
 342 #ifndef CONFIG_ARM64_VA_BITS_48
 343 #define EXTRA_SHIFT     (PGDIR_SHIFT + PAGE_SHIFT - 3)
 344 #define EXTRA_PTRS      (1 << (48 - EXTRA_SHIFT))
 345
 346         /*
 347          * If VA_BITS < 48, it may be too small to allow for an ID mapping to be
 348          * created that covers system RAM if that is located sufficiently high
 349          * in the physical address space. So for the ID map, use an extended
 350          * virtual range in that case, by configuring an additional translation
 351          * level.
 352          * First, we have to verify our assumption that the current value of
 353          * VA_BITS was chosen such that all translation levels are fully
 354          * utilised, and that lowering T0SZ will always result in an additional
 355          * translation level to be configured.
 356          */
 357 #if VA_BITS != EXTRA_SHIFT
 358 #error "Mismatch between VA_BITS and page size/number of translation levels"
 359 #endif
 360
 361         /*
 362          * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
 363          * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
 364          * this number conveniently equals the number of leading zeroes in
 365          * the physical address of __idmap_text_end.
 366          */
 367         adrp    x5, __idmap_text_end
 368         clz     x5, x5
 369         cmp     x5, TCR_T0SZ(VA_BITS)   // default T0SZ small enough?
 370         b.ge    1f                      // .. then skip additional level
 371
 372         adr_l   x6, idmap_t0sz
 373         str     x5, [x6]
 374         dmb     sy
 375         dc      ivac, x6                // Invalidate potentially stale cache line
 376
 377         create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6
 378 1:
 379 #endif
 380
 381         create_pgd_entry x0, x3, x5, x6
 382         mov     x5, x3                          // __pa(__idmap_text_start)
 383         adr_l   x6, __idmap_text_end            // __pa(__idmap_text_end)
 384         create_block_map x0, x7, x3, x5, x6
 385
 386         /*
 387          * Map the kernel image (starting with PHYS_OFFSET).
 388          */
 389         adrp    x0, swapper_pg_dir
 390         mov_q   x5, KIMAGE_VADDR + TEXT_OFFSET  // compile time __va(_text)
 391         add     x5, x5, x23                     // add KASLR displacement
 392         create_pgd_entry x0, x5, x3, x6
 393         adrp    x6, _end                        // runtime __pa(_end)
 394         adrp    x3, _text                       // runtime __pa(_text)
 395         sub     x6, x6, x3                      // _end - _text
 396         add     x6, x6, x5                      // runtime __va(_end)
 397         create_block_map x0, x7, x3, x5, x6
 398
 399         /*
 400          * Since the page tables have been populated with non-cacheable
 401          * accesses (MMU disabled), invalidate the idmap and swapper page
 402          * tables again to remove any speculatively loaded cache lines.
 403          */
 404         adrp    x0, idmap_pg_dir
 405         adrp    x1, swapper_pg_dir + SWAPPER_DIR_SIZE
 406         dmb     sy
 407         bl      __inval_cache_range
 408
 409         ret     x28
 410 ENDPROC(__create_page_tables)
 411         .ltorg
 412
 413 /*
 414  * The following fragment of code is executed with the MMU enabled.
 415  *
 416  *   x0 = __PHYS_OFFSET
 417  */
 418         .set    initial_sp, init_thread_union + THREAD_START_SP
 419 __primary_switched:
 420         mov     x28, lr                         // preserve LR
 421         adr_l   x8, vectors                     // load VBAR_EL1 with virtual
 422         msr     vbar_el1, x8                    // vector table address
 423         isb
 424
 425         str_l   x21, __fdt_pointer, x5          // Save FDT pointer
 426
 427         ldr_l   x4, kimage_vaddr                // Save the offset between
 428         sub     x4, x4, x0                      // the kernel virtual and
 429         str_l   x4, kimage_voffset, x5          // physical mappings
 430
 431         // Clear BSS
 432         adr_l   x0, __bss_start
 433         mov     x1, xzr
 434         adr_l   x2, __bss_stop
 435         sub     x2, x2, x0
 436         bl      __pi_memset
 437         dsb     ishst                           // Make zero page visible to PTW
 438
 439         adr_l   sp, initial_sp, x4
 440         mov     x4, sp
 441         and     x4, x4, #~(THREAD_SIZE - 1)
 442         msr     sp_el0, x4                      // Save thread_info
 443         mov     x29, #0
 444 #ifdef CONFIG_KASAN
 445         bl      kasan_early_init
 446 #endif
 447 #ifdef CONFIG_RANDOMIZE_BASE
 448         tst     x23, ~(MIN_KIMG_ALIGN - 1)      // already running randomized?
 449         b.ne    0f
 450         mov     x0, x21                         // pass FDT address in x0
 451         mov     x1, x23                         // pass modulo offset in x1
 452         bl      kaslr_early_init                // parse FDT for KASLR options
 453         cbz     x0, 0f                          // KASLR disabled? just proceed
 454         orr     x23, x23, x0                    // record KASLR offset
 455         ret     x28                             // we must enable KASLR, return
 456                                                 // to __primary_switch()
 457 0:
 458 #endif
 459         b       start_kernel
 460 ENDPROC(__primary_switched)
 461
 462 /*
 463  * end early head section, begin head code that is also used for
 464  * hotplug and needs to have the same protections as the text region
 465  */
 466         .section ".idmap.text","ax"
 467
 468 ENTRY(kimage_vaddr)
 469         .quad           _text - TEXT_OFFSET
 470
 471 /*
 472  * If we're fortunate enough to boot at EL2, ensure that the world is
 473  * sane before dropping to EL1.
 474  *
 475  * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
 476  * booted in EL1 or EL2 respectively.
 477  */
 478 ENTRY(el2_setup)
 479         mrs     x0, CurrentEL
 480         cmp     x0, #CurrentEL_EL2
 481         b.ne    1f
 482         mrs     x0, sctlr_el2
 483 CPU_BE( orr     x0, x0, #(1 << 25)      )       // Set the EE bit for EL2
 484 CPU_LE( bic     x0, x0, #(1 << 25)      )       // Clear the EE bit for EL2
 485         msr     sctlr_el2, x0
 486         b       2f
 487 1:      mrs     x0, sctlr_el1
 488 CPU_BE( orr     x0, x0, #(3 << 24)      )       // Set the EE and E0E bits for EL1
 489 CPU_LE( bic     x0, x0, #(3 << 24)      )       // Clear the EE and E0E bits for EL1
 490         msr     sctlr_el1, x0
 491         mov     w0, #BOOT_CPU_MODE_EL1          // This cpu booted in EL1
 492         isb
 493         ret
 494
 495 2:
 496 #ifdef CONFIG_ARM64_VHE
 497         /*
 498          * Check for VHE being present. For the rest of the EL2 setup,
 499          * x2 being non-zero indicates that we do have VHE, and that the
 500          * kernel is intended to run at EL2.
 501          */
 502         mrs     x2, id_aa64mmfr1_el1
 503         ubfx    x2, x2, #8, #4
 504 #else
 505         mov     x2, xzr
 506 #endif
 507
 508         /* Hyp configuration. */
 509         mov     x0, #HCR_RW                     // 64-bit EL1
 510         cbz     x2, set_hcr
 511         orr     x0, x0, #HCR_TGE                // Enable Host Extensions
 512         orr     x0, x0, #HCR_E2H
 513 set_hcr:
 514         msr     hcr_el2, x0
 515         isb
 516
 517         /* Generic timers. */
 518         mrs     x0, cnthctl_el2
 519         orr     x0, x0, #3                      // Enable EL1 physical timers
 520         msr     cnthctl_el2, x0
 521         msr     cntvoff_el2, xzr                // Clear virtual offset
 522
 523 #ifdef CONFIG_ARM_GIC_V3
 524         /* GICv3 system register access */
 525         mrs     x0, id_aa64pfr0_el1
 526         ubfx    x0, x0, #24, #4
 527         cmp     x0, #1
 528         b.ne    3f
 529
 530         mrs_s   x0, ICC_SRE_EL2
 531         orr     x0, x0, #ICC_SRE_EL2_SRE        // Set ICC_SRE_EL2.SRE==1
 532         orr     x0, x0, #ICC_SRE_EL2_ENABLE     // Set ICC_SRE_EL2.Enable==1
 533         msr_s   ICC_SRE_EL2, x0
 534         isb                                     // Make sure SRE is now set
 535         mrs_s   x0, ICC_SRE_EL2                 // Read SRE back,
 536         tbz     x0, #0, 3f                      // and check that it sticks
 537         msr_s   ICH_HCR_EL2, xzr                // Reset ICC_HCR_EL2 to defaults
 538
 539 3:
 540 #endif
 541
 542         /* Populate ID registers. */
 543         mrs     x0, midr_el1
 544         mrs     x1, mpidr_el1
 545         msr     vpidr_el2, x0
 546         msr     vmpidr_el2, x1
 547
 548         /*
 549          * When VHE is not in use, early init of EL2 and EL1 needs to be
 550          * done here.
 551          * When VHE _is_ in use, EL1 will not be used in the host and
 552          * requires no configuration, and all non-hyp-specific EL2 setup
 553          * will be done via the _EL1 system register aliases in __cpu_setup.
 554          */
 555         cbnz    x2, 1f
 556
 557         /* sctlr_el1 */
 558         mov     x0, #0x0800                     // Set/clear RES{1,0} bits
 559 CPU_BE( movk    x0, #0x33d0, lsl #16    )       // Set EE and E0E on BE systems
 560 CPU_LE( movk    x0, #0x30d0, lsl #16    )       // Clear EE and E0E on LE systems
 561         msr     sctlr_el1, x0
 562
 563         /* Coprocessor traps. */
 564         mov     x0, #0x33ff
 565         msr     cptr_el2, x0                    // Disable copro. traps to EL2
 566 1:
 567
 568 #ifdef CONFIG_COMPAT
 569         msr     hstr_el2, xzr                   // Disable CP15 traps to EL2
 570 #endif
 571
 572         /* EL2 debug */
 573         mrs     x0, id_aa64dfr0_el1             // Check ID_AA64DFR0_EL1 PMUVer
 574         sbfx    x0, x0, #8, #4
 575         cmp     x0, #1
 576         b.lt    4f                              // Skip if no PMU present
 577         mrs     x0, pmcr_el0                    // Disable debug access traps
 578         ubfx    x0, x0, #11, #5                 // to EL2 and allow access to
 579         msr     mdcr_el2, x0                    // all PMU counters from EL1
 580 4:
 581
 582         /* Stage-2 translation */
 583         msr     vttbr_el2, xzr
 584
 585         cbz     x2, install_el2_stub
 586
 587         mov     w0, #BOOT_CPU_MODE_EL2          // This CPU booted in EL2
 588         isb
 589         ret
 590
 591 install_el2_stub:
 592         /* Hypervisor stub */
 593         adrp    x0, __hyp_stub_vectors
 594         add     x0, x0, #:lo12:__hyp_stub_vectors
 595         msr     vbar_el2, x0
 596
 597         /* spsr */
 598         mov     x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
 599                       PSR_MODE_EL1h)
 600         msr     spsr_el2, x0
 601         msr     elr_el2, lr
 602         mov     w0, #BOOT_CPU_MODE_EL2          // This CPU booted in EL2
 603         eret
 604 ENDPROC(el2_setup)
 605
 606 /*
 607  * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
 608  * in x20. See arch/arm64/include/asm/virt.h for more info.
 609  */
 610 set_cpu_boot_mode_flag:
 611         adr_l   x1, __boot_cpu_mode
 612         cmp     w0, #BOOT_CPU_MODE_EL2
 613         b.ne    1f
 614         add     x1, x1, #4
 615 1:      str     w0, [x1]                        // This CPU has booted in EL1
 616         dmb     sy
 617         dc      ivac, x1                        // Invalidate potentially stale cache line
 618         ret
 619 ENDPROC(set_cpu_boot_mode_flag)
 620
 621 /*
 622  * These values are written with the MMU off, but read with the MMU on.
 623  * Writers will invalidate the corresponding address, discarding up to a
 624  * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures
 625  * sufficient alignment that the CWG doesn't overlap another section.
 626  */
 627         .pushsection ".mmuoff.data.write", "aw"
 628 /*
 629  * We need to find out the CPU boot mode long after boot, so we need to
 630  * store it in a writable variable.
 631  *
 632  * This is not in .bss, because we set it sufficiently early that the boot-time
 633  * zeroing of .bss would clobber it.
 634  */
 635 ENTRY(__boot_cpu_mode)
 636         .long   BOOT_CPU_MODE_EL2
 637         .long   BOOT_CPU_MODE_EL1
 638 /*
 639  * The booting CPU updates the failed status @__early_cpu_boot_status,
 640  * with MMU turned off.
 641  */
 642 ENTRY(__early_cpu_boot_status)
 643         .long   0
 644
 645         .popsection
 646
 647         /*
 648          * This provides a "holding pen" for platforms to hold all secondary
 649          * cores are held until we're ready for them to initialise.
 650          */
 651 ENTRY(secondary_holding_pen)
 652         bl      el2_setup                       // Drop to EL1, w0=cpu_boot_mode
 653         bl      set_cpu_boot_mode_flag
 654         mrs     x0, mpidr_el1
 655         mov_q   x1, MPIDR_HWID_BITMASK
 656         and     x0, x0, x1
 657         adr_l   x3, secondary_holding_pen_release
 658 pen:    ldr     x4, [x3]
 659         cmp     x4, x0
 660         b.eq    secondary_startup
 661         wfe
 662         b       pen
 663 ENDPROC(secondary_holding_pen)
 664
 665         /*
 666          * Secondary entry point that jumps straight into the kernel. Only to
 667          * be used where CPUs are brought online dynamically by the kernel.
 668          */
 669 ENTRY(secondary_entry)
 670         bl      el2_setup                       // Drop to EL1
 671         bl      set_cpu_boot_mode_flag
 672         b       secondary_startup
 673 ENDPROC(secondary_entry)
 674
 675 secondary_startup:
 676         /*
 677          * Common entry point for secondary CPUs.
 678          */
 679         bl      __cpu_setup                     // initialise processor
 680         bl      __enable_mmu
 681         ldr     x8, =__secondary_switched
 682         br      x8
 683 ENDPROC(secondary_startup)
 684
 685 __secondary_switched:
 686         adr_l   x5, vectors
 687         msr     vbar_el1, x5
 688         isb
 689
 690         adr_l   x0, secondary_data
 691         ldr     x0, [x0, #CPU_BOOT_STACK]       // get secondary_data.stack
 692         mov     sp, x0
 693         and     x0, x0, #~(THREAD_SIZE - 1)
 694         msr     sp_el0, x0                      // save thread_info
 695         mov     x29, #0
 696         b       secondary_start_kernel
 697 ENDPROC(__secondary_switched)
 698
 699 /*
 700  * The booting CPU updates the failed status @__early_cpu_boot_status,
 701  * with MMU turned off.
 702  *
 703  * update_early_cpu_boot_status tmp, status
 704  *  - Corrupts tmp1, tmp2
 705  *  - Writes 'status' to __early_cpu_boot_status and makes sure
 706  *    it is committed to memory.
 707  */
 708
 709         .macro  update_early_cpu_boot_status status, tmp1, tmp2
 710         mov     \tmp2, #\status
 711         adr_l   \tmp1, __early_cpu_boot_status
 712         str     \tmp2, [\tmp1]
 713         dmb     sy
 714         dc      ivac, \tmp1                     // Invalidate potentially stale cache line
 715         .endm
 716
 717 /*
 718  * Enable the MMU.
 719  *
 720  *  x0  = SCTLR_EL1 value for turning on the MMU.
 721  *
 722  * Returns to the caller via x30/lr. This requires the caller to be covered
 723  * by the .idmap.text section.
 724  *
 725  * Checks if the selected granule size is supported by the CPU.
 726  * If it isn't, park the CPU
 727  */
 728 ENTRY(__enable_mmu)
 729         mrs     x1, ID_AA64MMFR0_EL1
 730         ubfx    x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4
 731         cmp     x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
 732         b.ne    __no_granule_support
 733         update_early_cpu_boot_status 0, x1, x2
 734         adrp    x1, idmap_pg_dir
 735         adrp    x2, swapper_pg_dir
 736         msr     ttbr0_el1, x1                   // load TTBR0
 737         msr     ttbr1_el1, x2                   // load TTBR1
 738         isb
 739         msr     sctlr_el1, x0
 740         isb
 741         /*
 742          * Invalidate the local I-cache so that any instructions fetched
 743          * speculatively from the PoC are discarded, since they may have
 744          * been dynamically patched at the PoU.
 745          */
 746         ic      iallu
 747         dsb     nsh
 748         isb
 749         ret
 750 ENDPROC(__enable_mmu)
 751
 752 __no_granule_support:
 753         /* Indicate that this CPU can't boot and is stuck in the kernel */
 754         update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2
 755 1:
 756         wfe
 757         wfi
 758         b       1b
 759 ENDPROC(__no_granule_support)
 760
 761 #ifdef CONFIG_RELOCATABLE
 762 __relocate_kernel:
 763         /*
 764          * Iterate over each entry in the relocation table, and apply the
 765          * relocations in place.
 766          */
 767         ldr     w9, =__rela_offset              // offset to reloc table
 768         ldr     w10, =__rela_size               // size of reloc table
 769
 770         mov_q   x11, KIMAGE_VADDR               // default virtual offset
 771         add     x11, x11, x23                   // actual virtual offset
 772         add     x9, x9, x11                     // __va(.rela)
 773         add     x10, x9, x10                    // __va(.rela) + sizeof(.rela)
 774
 775 0:      cmp     x9, x10
 776         b.hs    1f
 777         ldp     x11, x12, [x9], #24
 778         ldr     x13, [x9, #-8]
 779         cmp     w12, #R_AARCH64_RELATIVE
 780         b.ne    0b
 781         add     x13, x13, x23                   // relocate
 782         str     x13, [x11, x23]
 783         b       0b
 784 1:      ret
 785 ENDPROC(__relocate_kernel)
 786 #endif
 787
 788 __primary_switch:
 789 #ifdef CONFIG_RANDOMIZE_BASE
 790         mov     x19, x0                         // preserve new SCTLR_EL1 value
 791         mrs     x20, sctlr_el1                  // preserve old SCTLR_EL1 value
 792 #endif
 793
 794         bl      __enable_mmu
 795 #ifdef CONFIG_RELOCATABLE
 796         bl      __relocate_kernel
 797 #ifdef CONFIG_RANDOMIZE_BASE
 798         ldr     x8, =__primary_switched
 799         adrp    x0, __PHYS_OFFSET
 800         blr     x8
 801
 802         /*
 803          * If we return here, we have a KASLR displacement in x23 which we need
 804          * to take into account by discarding the current kernel mapping and
 805          * creating a new one.
 806          */
 807         msr     sctlr_el1, x20                  // disable the MMU
 808         isb
 809         bl      __create_page_tables            // recreate kernel mapping
 810
 811         tlbi    vmalle1                         // Remove any stale TLB entries
 812         dsb     nsh
 813
 814         msr     sctlr_el1, x19                  // re-enable the MMU
 815         isb
 816         ic      iallu                           // flush instructions fetched
 817         dsb     nsh                             // via old mapping
 818         isb
 819
 820         bl      __relocate_kernel
 821 #endif
 822 #endif
 823         ldr     x8, =__primary_switched
 824         adrp    x0, __PHYS_OFFSET
 825         br      x8
 826 ENDPROC(__primary_switch)