arch/arm64/kernel/setup.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Based on arch/arm/kernel/setup.c
   4  *
   5  * Copyright (C) 1995-2001 Russell King
   6  * Copyright (C) 2012 ARM Ltd.
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/export.h>
  11 #include <linux/kernel.h>
  12 #include <linux/stddef.h>
  13 #include <linux/ioport.h>
  14 #include <linux/delay.h>
  15 #include <linux/initrd.h>
  16 #include <linux/console.h>
  17 #include <linux/cache.h>
  18 #include <linux/screen_info.h>
  19 #include <linux/init.h>
  20 #include <linux/kexec.h>
  21 #include <linux/root_dev.h>
  22 #include <linux/cpu.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/smp.h>
  25 #include <linux/fs.h>
  26 #include <linux/proc_fs.h>
  27 #include <linux/memblock.h>
  28 #include <linux/of_fdt.h>
  29 #include <linux/efi.h>
  30 #include <linux/psci.h>
  31 #include <linux/sched/task.h>
  32 #include <linux/mm.h>
  33
  34 #include <asm/acpi.h>
  35 #include <asm/fixmap.h>
  36 #include <asm/cpu.h>
  37 #include <asm/cputype.h>
  38 #include <asm/daifflags.h>
  39 #include <asm/elf.h>
  40 #include <asm/cpufeature.h>
  41 #include <asm/cpu_ops.h>
  42 #include <asm/kasan.h>
  43 #include <asm/numa.h>
  44 #include <asm/sections.h>
  45 #include <asm/setup.h>
  46 #include <asm/smp_plat.h>
  47 #include <asm/cacheflush.h>
  48 #include <asm/tlbflush.h>
  49 #include <asm/traps.h>
  50 #include <asm/efi.h>
  51 #include <asm/xen/hypervisor.h>
  52 #include <asm/mmu_context.h>
  53
  54 static int num_standard_resources;
  55 static struct resource *standard_resources;
  56
  57 phys_addr_t __fdt_pointer __initdata;
  58
  59 /*
  60  * Standard memory resources
  61  */
  62 static struct resource mem_res[] = {
  63         {
  64                 .name = "Kernel code",
  65                 .start = 0,
  66                 .end = 0,
  67                 .flags = IORESOURCE_SYSTEM_RAM
  68         },
  69         {
  70                 .name = "Kernel data",
  71                 .start = 0,
  72                 .end = 0,
  73                 .flags = IORESOURCE_SYSTEM_RAM
  74         }
  75 };
  76
  77 #define kernel_code mem_res[0]
  78 #define kernel_data mem_res[1]
  79
  80 /*
  81  * The recorded values of x0 .. x3 upon kernel entry.
  82  */
  83 u64 __cacheline_aligned boot_args[4];
  84
  85 void __init smp_setup_processor_id(void)
  86 {
  87         u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
  88         cpu_logical_map(0) = mpidr;
  89
  90         /*
  91          * clear __my_cpu_offset on boot CPU to avoid hang caused by
  92          * using percpu variable early, for example, lockdep will
  93          * access percpu variable inside lock_release
  94          */
  95         set_my_cpu_offset(0);
  96         pr_info("Booting Linux on physical CPU 0x%010lx [0x%08x]\n",
  97                 (unsigned long)mpidr, read_cpuid_id());
  98 }
  99
 100 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
 101 {
 102         return phys_id == cpu_logical_map(cpu);
 103 }
 104
 105 struct mpidr_hash mpidr_hash;
 106 /**
 107  * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
 108  *                        level in order to build a linear index from an
 109  *                        MPIDR value. Resulting algorithm is a collision
 110  *                        free hash carried out through shifting and ORing
 111  */
 112 static void __init smp_build_mpidr_hash(void)
 113 {
 114         u32 i, affinity, fs[4], bits[4], ls;
 115         u64 mask = 0;
 116         /*
 117          * Pre-scan the list of MPIDRS and filter out bits that do
 118          * not contribute to affinity levels, ie they never toggle.
 119          */
 120         for_each_possible_cpu(i)
 121                 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
 122         pr_debug("mask of set bits %#llx\n", mask);
 123         /*
 124          * Find and stash the last and first bit set at all affinity levels to
 125          * check how many bits are required to represent them.
 126          */
 127         for (i = 0; i < 4; i++) {
 128                 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
 129                 /*
 130                  * Find the MSB bit and LSB bits position
 131                  * to determine how many bits are required
 132                  * to express the affinity level.
 133                  */
 134                 ls = fls(affinity);
 135                 fs[i] = affinity ? ffs(affinity) - 1 : 0;
 136                 bits[i] = ls - fs[i];
 137         }
 138         /*
 139          * An index can be created from the MPIDR_EL1 by isolating the
 140          * significant bits at each affinity level and by shifting
 141          * them in order to compress the 32 bits values space to a
 142          * compressed set of values. This is equivalent to hashing
 143          * the MPIDR_EL1 through shifting and ORing. It is a collision free
 144          * hash though not minimal since some levels might contain a number
 145          * of CPUs that is not an exact power of 2 and their bit
 146          * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
 147          */
 148         mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
 149         mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
 150         mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
 151                                                 (bits[1] + bits[0]);
 152         mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
 153                                   fs[3] - (bits[2] + bits[1] + bits[0]);
 154         mpidr_hash.mask = mask;
 155         mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
 156         pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
 157                 mpidr_hash.shift_aff[0],
 158                 mpidr_hash.shift_aff[1],
 159                 mpidr_hash.shift_aff[2],
 160                 mpidr_hash.shift_aff[3],
 161                 mpidr_hash.mask,
 162                 mpidr_hash.bits);
 163         /*
 164          * 4x is an arbitrary value used to warn on a hash table much bigger
 165          * than expected on most systems.
 166          */
 167         if (mpidr_hash_size() > 4 * num_possible_cpus())
 168                 pr_warn("Large number of MPIDR hash buckets detected\n");
 169 }
 170
 171 static void __init setup_machine_fdt(phys_addr_t dt_phys)
 172 {
 173         void *dt_virt = fixmap_remap_fdt(dt_phys);
 174         const char *name;
 175
 176         if (!dt_virt || !early_init_dt_scan(dt_virt)) {
 177                 pr_crit("\n"
 178                         "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n"
 179                         "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"
 180                         "\nPlease check your bootloader.",
 181                         &dt_phys, dt_virt);
 182
 183                 while (true)
 184                         cpu_relax();
 185         }
 186
 187         name = of_flat_dt_get_machine_name();
 188         if (!name)
 189                 return;
 190
 191         pr_info("Machine model: %s\n", name);
 192         dump_stack_set_arch_desc("%s (DT)", name);
 193 }
 194
 195 static void __init request_standard_resources(void)
 196 {
 197         struct memblock_region *region;
 198         struct resource *res;
 199         unsigned long i = 0;
 200         size_t res_size;
 201
 202         kernel_code.start   = __pa_symbol(_text);
 203         kernel_code.end     = __pa_symbol(__init_begin - 1);
 204         kernel_data.start   = __pa_symbol(_sdata);
 205         kernel_data.end     = __pa_symbol(_end - 1);
 206
 207         num_standard_resources = memblock.memory.cnt;
 208         res_size = num_standard_resources * sizeof(*standard_resources);
 209         standard_resources = memblock_alloc(res_size, SMP_CACHE_BYTES);
 210         if (!standard_resources)
 211                 panic("%s: Failed to allocate %zu bytes\n", __func__, res_size);
 212
 213         for_each_memblock(memory, region) {
 214                 res = &standard_resources[i++];
 215                 if (memblock_is_nomap(region)) {
 216                         res->name  = "reserved";
 217                         res->flags = IORESOURCE_MEM;
 218                 } else {
 219                         res->name  = "System RAM";
 220                         res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
 221                 }
 222                 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
 223                 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
 224
 225                 request_resource(&iomem_resource, res);
 226
 227                 if (kernel_code.start >= res->start &&
 228                     kernel_code.end <= res->end)
 229                         request_resource(res, &kernel_code);
 230                 if (kernel_data.start >= res->start &&
 231                     kernel_data.end <= res->end)
 232                         request_resource(res, &kernel_data);
 233 #ifdef CONFIG_KEXEC_CORE
 234                 /* Userspace will find "Crash kernel" region in /proc/iomem. */
 235                 if (crashk_res.end && crashk_res.start >= res->start &&
 236                     crashk_res.end <= res->end)
 237                         request_resource(res, &crashk_res);
 238 #endif
 239         }
 240 }
 241
 242 static int __init reserve_memblock_reserved_regions(void)
 243 {
 244         u64 i, j;
 245
 246         for (i = 0; i < num_standard_resources; ++i) {
 247                 struct resource *mem = &standard_resources[i];
 248                 phys_addr_t r_start, r_end, mem_size = resource_size(mem);
 249
 250                 if (!memblock_is_region_reserved(mem->start, mem_size))
 251                         continue;
 252
 253                 for_each_reserved_mem_region(j, &r_start, &r_end) {
 254                         resource_size_t start, end;
 255
 256                         start = max(PFN_PHYS(PFN_DOWN(r_start)), mem->start);
 257                         end = min(PFN_PHYS(PFN_UP(r_end)) - 1, mem->end);
 258
 259                         if (start > mem->end || end < mem->start)
 260                                 continue;
 261
 262                         reserve_region_with_split(mem, start, end, "reserved");
 263                 }
 264         }
 265
 266         return 0;
 267 }
 268 arch_initcall(reserve_memblock_reserved_regions);
 269
 270 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
 271
 272 void __init setup_arch(char **cmdline_p)
 273 {
 274         init_mm.start_code = (unsigned long) _text;
 275         init_mm.end_code   = (unsigned long) _etext;
 276         init_mm.end_data   = (unsigned long) _edata;
 277         init_mm.brk        = (unsigned long) _end;
 278
 279         *cmdline_p = boot_command_line;
 280
 281         early_fixmap_init();
 282         early_ioremap_init();
 283
 284         setup_machine_fdt(__fdt_pointer);
 285
 286         parse_early_param();
 287
 288         /*
 289          * Unmask asynchronous aborts and fiq after bringing up possible
 290          * earlycon. (Report possible System Errors once we can report this
 291          * occurred).
 292          */
 293         local_daif_restore(DAIF_PROCCTX_NOIRQ);
 294
 295         /*
 296          * TTBR0 is only used for the identity mapping at this stage. Make it
 297          * point to zero page to avoid speculatively fetching new entries.
 298          */
 299         cpu_uninstall_idmap();
 300
 301         xen_early_init();
 302         efi_init();
 303         arm64_memblock_init();
 304
 305         paging_init();
 306
 307         acpi_table_upgrade();
 308
 309         /* Parse the ACPI tables for possible boot-time configuration */
 310         acpi_boot_table_init();
 311
 312         if (acpi_disabled)
 313                 unflatten_device_tree();
 314
 315         bootmem_init();
 316
 317         kasan_init();
 318
 319         request_standard_resources();
 320
 321         early_ioremap_reset();
 322
 323         if (acpi_disabled)
 324                 psci_dt_init();
 325         else
 326                 psci_acpi_init();
 327
 328         cpu_read_bootcpu_ops();
 329         smp_init_cpus();
 330         smp_build_mpidr_hash();
 331
 332         /* Init percpu seeds for random tags after cpus are set up. */
 333         kasan_init_tags();
 334
 335 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
 336         /*
 337          * Make sure init_thread_info.ttbr0 always generates translation
 338          * faults in case uaccess_enable() is inadvertently called by the init
 339          * thread.
 340          */
 341         init_task.thread_info.ttbr0 = __pa_symbol(empty_zero_page);
 342 #endif
 343
 344 #ifdef CONFIG_VT
 345         conswitchp = &dummy_con;
 346 #endif
 347         if (boot_args[1] || boot_args[2] || boot_args[3]) {
 348                 pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"
 349                         "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n"
 350                         "This indicates a broken bootloader or old kernel\n",
 351                         boot_args[1], boot_args[2], boot_args[3]);
 352         }
 353 }
 354
 355 static int __init topology_init(void)
 356 {
 357         int i;
 358
 359         for_each_online_node(i)
 360                 register_one_node(i);
 361
 362         for_each_possible_cpu(i) {
 363                 struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
 364                 cpu->hotpluggable = 1;
 365                 register_cpu(cpu, i);
 366         }
 367
 368         return 0;
 369 }
 370 subsys_initcall(topology_init);
 371
 372 /*
 373  * Dump out kernel offset information on panic.
 374  */
 375 static int dump_kernel_offset(struct notifier_block *self, unsigned long v,
 376                               void *p)
 377 {
 378         const unsigned long offset = kaslr_offset();
 379
 380         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && offset > 0) {
 381                 pr_emerg("Kernel Offset: 0x%lx from 0x%lx\n",
 382                          offset, KIMAGE_VADDR);
 383                 pr_emerg("PHYS_OFFSET: 0x%llx\n", PHYS_OFFSET);
 384         } else {
 385                 pr_emerg("Kernel Offset: disabled\n");
 386         }
 387         return 0;
 388 }
 389
 390 static struct notifier_block kernel_offset_notifier = {
 391         .notifier_call = dump_kernel_offset
 392 };
 393
 394 static int __init register_kernel_offset_dumper(void)
 395 {
 396         atomic_notifier_chain_register(&panic_notifier_list,
 397                                        &kernel_offset_notifier);
 398         return 0;
 399 }
 400 __initcall(register_kernel_offset_dumper);