arch/arm64/kvm/hyp/entry.S

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2015 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #include <linux/linkage.h>
   8
   9 #include <asm/alternative.h>
  10 #include <asm/asm-offsets.h>
  11 #include <asm/assembler.h>
  12 #include <asm/fpsimdmacros.h>
  13 #include <asm/kvm.h>
  14 #include <asm/kvm_arm.h>
  15 #include <asm/kvm_asm.h>
  16 #include <asm/kvm_mmu.h>
  17 #include <asm/kvm_ptrauth.h>
  18
  19 #define CPU_GP_REG_OFFSET(x)    (CPU_GP_REGS + x)
  20 #define CPU_XREG_OFFSET(x)      CPU_GP_REG_OFFSET(CPU_USER_PT_REGS + 8*x)
  21
  22         .text
  23         .pushsection    .hyp.text, "ax"
  24
  25 /*
  26  * We treat x18 as callee-saved as the host may use it as a platform
  27  * register (e.g. for shadow call stack).
  28  */
  29 .macro save_callee_saved_regs ctxt
  30         str     x18,      [\ctxt, #CPU_XREG_OFFSET(18)]
  31         stp     x19, x20, [\ctxt, #CPU_XREG_OFFSET(19)]
  32         stp     x21, x22, [\ctxt, #CPU_XREG_OFFSET(21)]
  33         stp     x23, x24, [\ctxt, #CPU_XREG_OFFSET(23)]
  34         stp     x25, x26, [\ctxt, #CPU_XREG_OFFSET(25)]
  35         stp     x27, x28, [\ctxt, #CPU_XREG_OFFSET(27)]
  36         stp     x29, lr,  [\ctxt, #CPU_XREG_OFFSET(29)]
  37 .endm
  38
  39 .macro restore_callee_saved_regs ctxt
  40         // We require \ctxt is not x18-x28
  41         ldr     x18,      [\ctxt, #CPU_XREG_OFFSET(18)]
  42         ldp     x19, x20, [\ctxt, #CPU_XREG_OFFSET(19)]
  43         ldp     x21, x22, [\ctxt, #CPU_XREG_OFFSET(21)]
  44         ldp     x23, x24, [\ctxt, #CPU_XREG_OFFSET(23)]
  45         ldp     x25, x26, [\ctxt, #CPU_XREG_OFFSET(25)]
  46         ldp     x27, x28, [\ctxt, #CPU_XREG_OFFSET(27)]
  47         ldp     x29, lr,  [\ctxt, #CPU_XREG_OFFSET(29)]
  48 .endm
  49
  50 /*
  51  * u64 __guest_enter(struct kvm_vcpu *vcpu,
  52  *                   struct kvm_cpu_context *host_ctxt);
  53  */
  54 SYM_FUNC_START(__guest_enter)
  55         // x0: vcpu
  56         // x1: host context
  57         // x2-x17: clobbered by macros
  58         // x29: guest context
  59
  60         // Store the host regs
  61         save_callee_saved_regs x1
  62
  63         // Now the host state is stored if we have a pending RAS SError it must
  64         // affect the host. If any asynchronous exception is pending we defer
  65         // the guest entry. The DSB isn't necessary before v8.2 as any SError
  66         // would be fatal.
  67 alternative_if ARM64_HAS_RAS_EXTN
  68         dsb     nshst
  69         isb
  70 alternative_else_nop_endif
  71         mrs     x1, isr_el1
  72         cbz     x1,  1f
  73         mov     x0, #ARM_EXCEPTION_IRQ
  74         ret
  75
  76 1:
  77         add     x29, x0, #VCPU_CONTEXT
  78
  79         // Macro ptrauth_switch_to_guest format:
  80         //      ptrauth_switch_to_guest(guest cxt, tmp1, tmp2, tmp3)
  81         // The below macro to restore guest keys is not implemented in C code
  82         // as it may cause Pointer Authentication key signing mismatch errors
  83         // when this feature is enabled for kernel code.
  84         ptrauth_switch_to_guest x29, x0, x1, x2
  85
  86         // Restore guest regs x0-x17
  87         ldp     x0, x1,   [x29, #CPU_XREG_OFFSET(0)]
  88         ldp     x2, x3,   [x29, #CPU_XREG_OFFSET(2)]
  89         ldp     x4, x5,   [x29, #CPU_XREG_OFFSET(4)]
  90         ldp     x6, x7,   [x29, #CPU_XREG_OFFSET(6)]
  91         ldp     x8, x9,   [x29, #CPU_XREG_OFFSET(8)]
  92         ldp     x10, x11, [x29, #CPU_XREG_OFFSET(10)]
  93         ldp     x12, x13, [x29, #CPU_XREG_OFFSET(12)]
  94         ldp     x14, x15, [x29, #CPU_XREG_OFFSET(14)]
  95         ldp     x16, x17, [x29, #CPU_XREG_OFFSET(16)]
  96
  97         // Restore guest regs x18-x29, lr
  98         restore_callee_saved_regs x29
  99
 100         // Do not touch any register after this!
 101         eret
 102         sb
 103
 104 SYM_INNER_LABEL(__guest_exit, SYM_L_GLOBAL)
 105         // x0: return code
 106         // x1: vcpu
 107         // x2-x29,lr: vcpu regs
 108         // vcpu x0-x1 on the stack
 109
 110         add     x1, x1, #VCPU_CONTEXT
 111
 112         ALTERNATIVE(nop, SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN)
 113
 114         // Store the guest regs x2 and x3
 115         stp     x2, x3,   [x1, #CPU_XREG_OFFSET(2)]
 116
 117         // Retrieve the guest regs x0-x1 from the stack
 118         ldp     x2, x3, [sp], #16       // x0, x1
 119
 120         // Store the guest regs x0-x1 and x4-x17
 121         stp     x2, x3,   [x1, #CPU_XREG_OFFSET(0)]
 122         stp     x4, x5,   [x1, #CPU_XREG_OFFSET(4)]
 123         stp     x6, x7,   [x1, #CPU_XREG_OFFSET(6)]
 124         stp     x8, x9,   [x1, #CPU_XREG_OFFSET(8)]
 125         stp     x10, x11, [x1, #CPU_XREG_OFFSET(10)]
 126         stp     x12, x13, [x1, #CPU_XREG_OFFSET(12)]
 127         stp     x14, x15, [x1, #CPU_XREG_OFFSET(14)]
 128         stp     x16, x17, [x1, #CPU_XREG_OFFSET(16)]
 129
 130         // Store the guest regs x18-x29, lr
 131         save_callee_saved_regs x1
 132
 133         get_host_ctxt   x2, x3
 134
 135         // Macro ptrauth_switch_to_guest format:
 136         //      ptrauth_switch_to_host(guest cxt, host cxt, tmp1, tmp2, tmp3)
 137         // The below macro to save/restore keys is not implemented in C code
 138         // as it may cause Pointer Authentication key signing mismatch errors
 139         // when this feature is enabled for kernel code.
 140         ptrauth_switch_to_host x1, x2, x3, x4, x5
 141
 142         // Now restore the host regs
 143         restore_callee_saved_regs x2
 144
 145 alternative_if ARM64_HAS_RAS_EXTN
 146         // If we have the RAS extensions we can consume a pending error
 147         // without an unmask-SError and isb. The ESB-instruction consumed any
 148         // pending guest error when we took the exception from the guest.
 149         mrs_s   x2, SYS_DISR_EL1
 150         str     x2, [x1, #(VCPU_FAULT_DISR - VCPU_CONTEXT)]
 151         cbz     x2, 1f
 152         msr_s   SYS_DISR_EL1, xzr
 153         orr     x0, x0, #(1<<ARM_EXIT_WITH_SERROR_BIT)
 154 1:      ret
 155 alternative_else
 156         dsb     sy              // Synchronize against in-flight ld/st
 157         isb                     // Prevent an early read of side-effect free ISR
 158         mrs     x2, isr_el1
 159         tbnz    x2, #8, 2f      // ISR_EL1.A
 160         ret
 161         nop
 162 2:
 163 alternative_endif
 164         // We know we have a pending asynchronous abort, now is the
 165         // time to flush it out. From your VAXorcist book, page 666:
 166         // "Threaten me not, oh Evil one!  For I speak with
 167         // the power of DEC, and I command thee to show thyself!"
 168         mrs     x2, elr_el2
 169         mrs     x3, esr_el2
 170         mrs     x4, spsr_el2
 171         mov     x5, x0
 172
 173         msr     daifclr, #4     // Unmask aborts
 174
 175         // This is our single instruction exception window. A pending
 176         // SError is guaranteed to occur at the earliest when we unmask
 177         // it, and at the latest just after the ISB.
 178         .global abort_guest_exit_start
 179 abort_guest_exit_start:
 180
 181         isb
 182
 183         .global abort_guest_exit_end
 184 abort_guest_exit_end:
 185
 186         msr     daifset, #4     // Mask aborts
 187
 188         // If the exception took place, restore the EL1 exception
 189         // context so that we can report some information.
 190         // Merge the exception code with the SError pending bit.
 191         tbz     x0, #ARM_EXIT_WITH_SERROR_BIT, 1f
 192         msr     elr_el2, x2
 193         msr     esr_el2, x3
 194         msr     spsr_el2, x4
 195         orr     x0, x0, x5
 196 1:      ret
 197 SYM_FUNC_END(__guest_enter)