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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64...
[people/ms/linux.git] / arch / arm64 / kvm / sys_regs.c
1 /*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Derived from arch/arm/kvm/coproc.c:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Authors: Rusty Russell <rusty@rustcorp.com.au>
8 * Christoffer Dall <c.dall@virtualopensystems.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License, version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include <linux/kvm_host.h>
24 #include <linux/mm.h>
25 #include <linux/uaccess.h>
26
27 #include <asm/cacheflush.h>
28 #include <asm/cputype.h>
29 #include <asm/debug-monitors.h>
30 #include <asm/esr.h>
31 #include <asm/kvm_arm.h>
32 #include <asm/kvm_coproc.h>
33 #include <asm/kvm_emulate.h>
34 #include <asm/kvm_host.h>
35 #include <asm/kvm_mmu.h>
36
37 #include <trace/events/kvm.h>
38
39 #include "sys_regs.h"
40
41 /*
42 * All of this file is extremly similar to the ARM coproc.c, but the
43 * types are different. My gut feeling is that it should be pretty
44 * easy to merge, but that would be an ABI breakage -- again. VFP
45 * would also need to be abstracted.
46 *
47 * For AArch32, we only take care of what is being trapped. Anything
48 * that has to do with init and userspace access has to go via the
49 * 64bit interface.
50 */
51
52 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
53 static u32 cache_levels;
54
55 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
56 #define CSSELR_MAX 12
57
58 /* Which cache CCSIDR represents depends on CSSELR value. */
59 static u32 get_ccsidr(u32 csselr)
60 {
61 u32 ccsidr;
62
63 /* Make sure noone else changes CSSELR during this! */
64 local_irq_disable();
65 /* Put value into CSSELR */
66 asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
67 isb();
68 /* Read result out of CCSIDR */
69 asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr));
70 local_irq_enable();
71
72 return ccsidr;
73 }
74
75 /*
76 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
77 */
78 static bool access_dcsw(struct kvm_vcpu *vcpu,
79 const struct sys_reg_params *p,
80 const struct sys_reg_desc *r)
81 {
82 if (!p->is_write)
83 return read_from_write_only(vcpu, p);
84
85 kvm_set_way_flush(vcpu);
86 return true;
87 }
88
89 /*
90 * Generic accessor for VM registers. Only called as long as HCR_TVM
91 * is set. If the guest enables the MMU, we stop trapping the VM
92 * sys_regs and leave it in complete control of the caches.
93 */
94 static bool access_vm_reg(struct kvm_vcpu *vcpu,
95 const struct sys_reg_params *p,
96 const struct sys_reg_desc *r)
97 {
98 unsigned long val;
99 bool was_enabled = vcpu_has_cache_enabled(vcpu);
100
101 BUG_ON(!p->is_write);
102
103 val = *vcpu_reg(vcpu, p->Rt);
104 if (!p->is_aarch32) {
105 vcpu_sys_reg(vcpu, r->reg) = val;
106 } else {
107 if (!p->is_32bit)
108 vcpu_cp15_64_high(vcpu, r->reg) = val >> 32;
109 vcpu_cp15_64_low(vcpu, r->reg) = val & 0xffffffffUL;
110 }
111
112 kvm_toggle_cache(vcpu, was_enabled);
113 return true;
114 }
115
116 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
117 const struct sys_reg_params *p,
118 const struct sys_reg_desc *r)
119 {
120 if (p->is_write)
121 return ignore_write(vcpu, p);
122 else
123 return read_zero(vcpu, p);
124 }
125
126 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
127 const struct sys_reg_params *p,
128 const struct sys_reg_desc *r)
129 {
130 if (p->is_write) {
131 return ignore_write(vcpu, p);
132 } else {
133 *vcpu_reg(vcpu, p->Rt) = (1 << 3);
134 return true;
135 }
136 }
137
138 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
139 const struct sys_reg_params *p,
140 const struct sys_reg_desc *r)
141 {
142 if (p->is_write) {
143 return ignore_write(vcpu, p);
144 } else {
145 u32 val;
146 asm volatile("mrs %0, dbgauthstatus_el1" : "=r" (val));
147 *vcpu_reg(vcpu, p->Rt) = val;
148 return true;
149 }
150 }
151
152 /*
153 * We want to avoid world-switching all the DBG registers all the
154 * time:
155 *
156 * - If we've touched any debug register, it is likely that we're
157 * going to touch more of them. It then makes sense to disable the
158 * traps and start doing the save/restore dance
159 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
160 * then mandatory to save/restore the registers, as the guest
161 * depends on them.
162 *
163 * For this, we use a DIRTY bit, indicating the guest has modified the
164 * debug registers, used as follow:
165 *
166 * On guest entry:
167 * - If the dirty bit is set (because we're coming back from trapping),
168 * disable the traps, save host registers, restore guest registers.
169 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
170 * set the dirty bit, disable the traps, save host registers,
171 * restore guest registers.
172 * - Otherwise, enable the traps
173 *
174 * On guest exit:
175 * - If the dirty bit is set, save guest registers, restore host
176 * registers and clear the dirty bit. This ensure that the host can
177 * now use the debug registers.
178 */
179 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
180 const struct sys_reg_params *p,
181 const struct sys_reg_desc *r)
182 {
183 if (p->is_write) {
184 vcpu_sys_reg(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
185 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
186 } else {
187 *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg);
188 }
189
190 return true;
191 }
192
193 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
194 {
195 u64 amair;
196
197 asm volatile("mrs %0, amair_el1\n" : "=r" (amair));
198 vcpu_sys_reg(vcpu, AMAIR_EL1) = amair;
199 }
200
201 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
202 {
203 /*
204 * Simply map the vcpu_id into the Aff0 field of the MPIDR.
205 */
206 vcpu_sys_reg(vcpu, MPIDR_EL1) = (1UL << 31) | (vcpu->vcpu_id & 0xff);
207 }
208
209 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
210 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
211 /* DBGBVRn_EL1 */ \
212 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \
213 trap_debug_regs, reset_val, (DBGBVR0_EL1 + (n)), 0 }, \
214 /* DBGBCRn_EL1 */ \
215 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \
216 trap_debug_regs, reset_val, (DBGBCR0_EL1 + (n)), 0 }, \
217 /* DBGWVRn_EL1 */ \
218 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110), \
219 trap_debug_regs, reset_val, (DBGWVR0_EL1 + (n)), 0 }, \
220 /* DBGWCRn_EL1 */ \
221 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \
222 trap_debug_regs, reset_val, (DBGWCR0_EL1 + (n)), 0 }
223
224 /*
225 * Architected system registers.
226 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
227 *
228 * We could trap ID_DFR0 and tell the guest we don't support performance
229 * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
230 * NAKed, so it will read the PMCR anyway.
231 *
232 * Therefore we tell the guest we have 0 counters. Unfortunately, we
233 * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
234 * all PM registers, which doesn't crash the guest kernel at least.
235 *
236 * Debug handling: We do trap most, if not all debug related system
237 * registers. The implementation is good enough to ensure that a guest
238 * can use these with minimal performance degradation. The drawback is
239 * that we don't implement any of the external debug, none of the
240 * OSlock protocol. This should be revisited if we ever encounter a
241 * more demanding guest...
242 */
243 static const struct sys_reg_desc sys_reg_descs[] = {
244 /* DC ISW */
245 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
246 access_dcsw },
247 /* DC CSW */
248 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
249 access_dcsw },
250 /* DC CISW */
251 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
252 access_dcsw },
253
254 DBG_BCR_BVR_WCR_WVR_EL1(0),
255 DBG_BCR_BVR_WCR_WVR_EL1(1),
256 /* MDCCINT_EL1 */
257 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
258 trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
259 /* MDSCR_EL1 */
260 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
261 trap_debug_regs, reset_val, MDSCR_EL1, 0 },
262 DBG_BCR_BVR_WCR_WVR_EL1(2),
263 DBG_BCR_BVR_WCR_WVR_EL1(3),
264 DBG_BCR_BVR_WCR_WVR_EL1(4),
265 DBG_BCR_BVR_WCR_WVR_EL1(5),
266 DBG_BCR_BVR_WCR_WVR_EL1(6),
267 DBG_BCR_BVR_WCR_WVR_EL1(7),
268 DBG_BCR_BVR_WCR_WVR_EL1(8),
269 DBG_BCR_BVR_WCR_WVR_EL1(9),
270 DBG_BCR_BVR_WCR_WVR_EL1(10),
271 DBG_BCR_BVR_WCR_WVR_EL1(11),
272 DBG_BCR_BVR_WCR_WVR_EL1(12),
273 DBG_BCR_BVR_WCR_WVR_EL1(13),
274 DBG_BCR_BVR_WCR_WVR_EL1(14),
275 DBG_BCR_BVR_WCR_WVR_EL1(15),
276
277 /* MDRAR_EL1 */
278 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
279 trap_raz_wi },
280 /* OSLAR_EL1 */
281 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
282 trap_raz_wi },
283 /* OSLSR_EL1 */
284 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
285 trap_oslsr_el1 },
286 /* OSDLR_EL1 */
287 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
288 trap_raz_wi },
289 /* DBGPRCR_EL1 */
290 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
291 trap_raz_wi },
292 /* DBGCLAIMSET_EL1 */
293 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
294 trap_raz_wi },
295 /* DBGCLAIMCLR_EL1 */
296 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
297 trap_raz_wi },
298 /* DBGAUTHSTATUS_EL1 */
299 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
300 trap_dbgauthstatus_el1 },
301
302 /* TEECR32_EL1 */
303 { Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
304 NULL, reset_val, TEECR32_EL1, 0 },
305 /* TEEHBR32_EL1 */
306 { Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000),
307 NULL, reset_val, TEEHBR32_EL1, 0 },
308
309 /* MDCCSR_EL1 */
310 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
311 trap_raz_wi },
312 /* DBGDTR_EL0 */
313 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
314 trap_raz_wi },
315 /* DBGDTR[TR]X_EL0 */
316 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
317 trap_raz_wi },
318
319 /* DBGVCR32_EL2 */
320 { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
321 NULL, reset_val, DBGVCR32_EL2, 0 },
322
323 /* MPIDR_EL1 */
324 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
325 NULL, reset_mpidr, MPIDR_EL1 },
326 /* SCTLR_EL1 */
327 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
328 access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
329 /* CPACR_EL1 */
330 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
331 NULL, reset_val, CPACR_EL1, 0 },
332 /* TTBR0_EL1 */
333 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
334 access_vm_reg, reset_unknown, TTBR0_EL1 },
335 /* TTBR1_EL1 */
336 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
337 access_vm_reg, reset_unknown, TTBR1_EL1 },
338 /* TCR_EL1 */
339 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
340 access_vm_reg, reset_val, TCR_EL1, 0 },
341
342 /* AFSR0_EL1 */
343 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
344 access_vm_reg, reset_unknown, AFSR0_EL1 },
345 /* AFSR1_EL1 */
346 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
347 access_vm_reg, reset_unknown, AFSR1_EL1 },
348 /* ESR_EL1 */
349 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
350 access_vm_reg, reset_unknown, ESR_EL1 },
351 /* FAR_EL1 */
352 { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
353 access_vm_reg, reset_unknown, FAR_EL1 },
354 /* PAR_EL1 */
355 { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
356 NULL, reset_unknown, PAR_EL1 },
357
358 /* PMINTENSET_EL1 */
359 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
360 trap_raz_wi },
361 /* PMINTENCLR_EL1 */
362 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
363 trap_raz_wi },
364
365 /* MAIR_EL1 */
366 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
367 access_vm_reg, reset_unknown, MAIR_EL1 },
368 /* AMAIR_EL1 */
369 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
370 access_vm_reg, reset_amair_el1, AMAIR_EL1 },
371
372 /* VBAR_EL1 */
373 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
374 NULL, reset_val, VBAR_EL1, 0 },
375
376 /* ICC_SRE_EL1 */
377 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
378 trap_raz_wi },
379
380 /* CONTEXTIDR_EL1 */
381 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
382 access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
383 /* TPIDR_EL1 */
384 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
385 NULL, reset_unknown, TPIDR_EL1 },
386
387 /* CNTKCTL_EL1 */
388 { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
389 NULL, reset_val, CNTKCTL_EL1, 0},
390
391 /* CSSELR_EL1 */
392 { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
393 NULL, reset_unknown, CSSELR_EL1 },
394
395 /* PMCR_EL0 */
396 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
397 trap_raz_wi },
398 /* PMCNTENSET_EL0 */
399 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
400 trap_raz_wi },
401 /* PMCNTENCLR_EL0 */
402 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
403 trap_raz_wi },
404 /* PMOVSCLR_EL0 */
405 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
406 trap_raz_wi },
407 /* PMSWINC_EL0 */
408 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
409 trap_raz_wi },
410 /* PMSELR_EL0 */
411 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
412 trap_raz_wi },
413 /* PMCEID0_EL0 */
414 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
415 trap_raz_wi },
416 /* PMCEID1_EL0 */
417 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
418 trap_raz_wi },
419 /* PMCCNTR_EL0 */
420 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
421 trap_raz_wi },
422 /* PMXEVTYPER_EL0 */
423 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
424 trap_raz_wi },
425 /* PMXEVCNTR_EL0 */
426 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
427 trap_raz_wi },
428 /* PMUSERENR_EL0 */
429 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
430 trap_raz_wi },
431 /* PMOVSSET_EL0 */
432 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
433 trap_raz_wi },
434
435 /* TPIDR_EL0 */
436 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
437 NULL, reset_unknown, TPIDR_EL0 },
438 /* TPIDRRO_EL0 */
439 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
440 NULL, reset_unknown, TPIDRRO_EL0 },
441
442 /* DACR32_EL2 */
443 { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
444 NULL, reset_unknown, DACR32_EL2 },
445 /* IFSR32_EL2 */
446 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
447 NULL, reset_unknown, IFSR32_EL2 },
448 /* FPEXC32_EL2 */
449 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
450 NULL, reset_val, FPEXC32_EL2, 0x70 },
451 };
452
453 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
454 const struct sys_reg_params *p,
455 const struct sys_reg_desc *r)
456 {
457 if (p->is_write) {
458 return ignore_write(vcpu, p);
459 } else {
460 u64 dfr = read_cpuid(ID_AA64DFR0_EL1);
461 u64 pfr = read_cpuid(ID_AA64PFR0_EL1);
462 u32 el3 = !!((pfr >> 12) & 0xf);
463
464 *vcpu_reg(vcpu, p->Rt) = ((((dfr >> 20) & 0xf) << 28) |
465 (((dfr >> 12) & 0xf) << 24) |
466 (((dfr >> 28) & 0xf) << 20) |
467 (6 << 16) | (el3 << 14) | (el3 << 12));
468 return true;
469 }
470 }
471
472 static bool trap_debug32(struct kvm_vcpu *vcpu,
473 const struct sys_reg_params *p,
474 const struct sys_reg_desc *r)
475 {
476 if (p->is_write) {
477 vcpu_cp14(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
478 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
479 } else {
480 *vcpu_reg(vcpu, p->Rt) = vcpu_cp14(vcpu, r->reg);
481 }
482
483 return true;
484 }
485
486 #define DBG_BCR_BVR_WCR_WVR(n) \
487 /* DBGBVRn */ \
488 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_debug32, \
489 NULL, (cp14_DBGBVR0 + (n) * 2) }, \
490 /* DBGBCRn */ \
491 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_debug32, \
492 NULL, (cp14_DBGBCR0 + (n) * 2) }, \
493 /* DBGWVRn */ \
494 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_debug32, \
495 NULL, (cp14_DBGWVR0 + (n) * 2) }, \
496 /* DBGWCRn */ \
497 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_debug32, \
498 NULL, (cp14_DBGWCR0 + (n) * 2) }
499
500 #define DBGBXVR(n) \
501 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_debug32, \
502 NULL, cp14_DBGBXVR0 + n * 2 }
503
504 /*
505 * Trapped cp14 registers. We generally ignore most of the external
506 * debug, on the principle that they don't really make sense to a
507 * guest. Revisit this one day, whould this principle change.
508 */
509 static const struct sys_reg_desc cp14_regs[] = {
510 /* DBGIDR */
511 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
512 /* DBGDTRRXext */
513 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
514
515 DBG_BCR_BVR_WCR_WVR(0),
516 /* DBGDSCRint */
517 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
518 DBG_BCR_BVR_WCR_WVR(1),
519 /* DBGDCCINT */
520 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
521 /* DBGDSCRext */
522 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
523 DBG_BCR_BVR_WCR_WVR(2),
524 /* DBGDTR[RT]Xint */
525 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
526 /* DBGDTR[RT]Xext */
527 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
528 DBG_BCR_BVR_WCR_WVR(3),
529 DBG_BCR_BVR_WCR_WVR(4),
530 DBG_BCR_BVR_WCR_WVR(5),
531 /* DBGWFAR */
532 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
533 /* DBGOSECCR */
534 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
535 DBG_BCR_BVR_WCR_WVR(6),
536 /* DBGVCR */
537 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
538 DBG_BCR_BVR_WCR_WVR(7),
539 DBG_BCR_BVR_WCR_WVR(8),
540 DBG_BCR_BVR_WCR_WVR(9),
541 DBG_BCR_BVR_WCR_WVR(10),
542 DBG_BCR_BVR_WCR_WVR(11),
543 DBG_BCR_BVR_WCR_WVR(12),
544 DBG_BCR_BVR_WCR_WVR(13),
545 DBG_BCR_BVR_WCR_WVR(14),
546 DBG_BCR_BVR_WCR_WVR(15),
547
548 /* DBGDRAR (32bit) */
549 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
550
551 DBGBXVR(0),
552 /* DBGOSLAR */
553 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
554 DBGBXVR(1),
555 /* DBGOSLSR */
556 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
557 DBGBXVR(2),
558 DBGBXVR(3),
559 /* DBGOSDLR */
560 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
561 DBGBXVR(4),
562 /* DBGPRCR */
563 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
564 DBGBXVR(5),
565 DBGBXVR(6),
566 DBGBXVR(7),
567 DBGBXVR(8),
568 DBGBXVR(9),
569 DBGBXVR(10),
570 DBGBXVR(11),
571 DBGBXVR(12),
572 DBGBXVR(13),
573 DBGBXVR(14),
574 DBGBXVR(15),
575
576 /* DBGDSAR (32bit) */
577 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
578
579 /* DBGDEVID2 */
580 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
581 /* DBGDEVID1 */
582 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
583 /* DBGDEVID */
584 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
585 /* DBGCLAIMSET */
586 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
587 /* DBGCLAIMCLR */
588 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
589 /* DBGAUTHSTATUS */
590 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
591 };
592
593 /* Trapped cp14 64bit registers */
594 static const struct sys_reg_desc cp14_64_regs[] = {
595 /* DBGDRAR (64bit) */
596 { Op1( 0), CRm( 1), .access = trap_raz_wi },
597
598 /* DBGDSAR (64bit) */
599 { Op1( 0), CRm( 2), .access = trap_raz_wi },
600 };
601
602 /*
603 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
604 * depending on the way they are accessed (as a 32bit or a 64bit
605 * register).
606 */
607 static const struct sys_reg_desc cp15_regs[] = {
608 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
609 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
610 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
611 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
612 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
613 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
614 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
615 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
616 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
617 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
618 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
619
620 /*
621 * DC{C,I,CI}SW operations:
622 */
623 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
624 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
625 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
626
627 /* PMU */
628 { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi },
629 { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
630 { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
631 { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
632 { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
633 { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
634 { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
635 { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
636 { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
637 { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
638 { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
639 { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
640 { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
641
642 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
643 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
644 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
645 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
646
647 /* ICC_SRE */
648 { Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
649
650 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
651 };
652
653 static const struct sys_reg_desc cp15_64_regs[] = {
654 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
655 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
656 };
657
658 /* Target specific emulation tables */
659 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
660
661 void kvm_register_target_sys_reg_table(unsigned int target,
662 struct kvm_sys_reg_target_table *table)
663 {
664 target_tables[target] = table;
665 }
666
667 /* Get specific register table for this target. */
668 static const struct sys_reg_desc *get_target_table(unsigned target,
669 bool mode_is_64,
670 size_t *num)
671 {
672 struct kvm_sys_reg_target_table *table;
673
674 table = target_tables[target];
675 if (mode_is_64) {
676 *num = table->table64.num;
677 return table->table64.table;
678 } else {
679 *num = table->table32.num;
680 return table->table32.table;
681 }
682 }
683
684 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
685 const struct sys_reg_desc table[],
686 unsigned int num)
687 {
688 unsigned int i;
689
690 for (i = 0; i < num; i++) {
691 const struct sys_reg_desc *r = &table[i];
692
693 if (params->Op0 != r->Op0)
694 continue;
695 if (params->Op1 != r->Op1)
696 continue;
697 if (params->CRn != r->CRn)
698 continue;
699 if (params->CRm != r->CRm)
700 continue;
701 if (params->Op2 != r->Op2)
702 continue;
703
704 return r;
705 }
706 return NULL;
707 }
708
709 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
710 {
711 kvm_inject_undefined(vcpu);
712 return 1;
713 }
714
715 /*
716 * emulate_cp -- tries to match a sys_reg access in a handling table, and
717 * call the corresponding trap handler.
718 *
719 * @params: pointer to the descriptor of the access
720 * @table: array of trap descriptors
721 * @num: size of the trap descriptor array
722 *
723 * Return 0 if the access has been handled, and -1 if not.
724 */
725 static int emulate_cp(struct kvm_vcpu *vcpu,
726 const struct sys_reg_params *params,
727 const struct sys_reg_desc *table,
728 size_t num)
729 {
730 const struct sys_reg_desc *r;
731
732 if (!table)
733 return -1; /* Not handled */
734
735 r = find_reg(params, table, num);
736
737 if (r) {
738 /*
739 * Not having an accessor means that we have
740 * configured a trap that we don't know how to
741 * handle. This certainly qualifies as a gross bug
742 * that should be fixed right away.
743 */
744 BUG_ON(!r->access);
745
746 if (likely(r->access(vcpu, params, r))) {
747 /* Skip instruction, since it was emulated */
748 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
749 }
750
751 /* Handled */
752 return 0;
753 }
754
755 /* Not handled */
756 return -1;
757 }
758
759 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
760 struct sys_reg_params *params)
761 {
762 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
763 int cp;
764
765 switch(hsr_ec) {
766 case ESR_ELx_EC_CP15_32:
767 case ESR_ELx_EC_CP15_64:
768 cp = 15;
769 break;
770 case ESR_ELx_EC_CP14_MR:
771 case ESR_ELx_EC_CP14_64:
772 cp = 14;
773 break;
774 default:
775 WARN_ON((cp = -1));
776 }
777
778 kvm_err("Unsupported guest CP%d access at: %08lx\n",
779 cp, *vcpu_pc(vcpu));
780 print_sys_reg_instr(params);
781 kvm_inject_undefined(vcpu);
782 }
783
784 /**
785 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP15 access
786 * @vcpu: The VCPU pointer
787 * @run: The kvm_run struct
788 */
789 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
790 const struct sys_reg_desc *global,
791 size_t nr_global,
792 const struct sys_reg_desc *target_specific,
793 size_t nr_specific)
794 {
795 struct sys_reg_params params;
796 u32 hsr = kvm_vcpu_get_hsr(vcpu);
797 int Rt2 = (hsr >> 10) & 0xf;
798
799 params.is_aarch32 = true;
800 params.is_32bit = false;
801 params.CRm = (hsr >> 1) & 0xf;
802 params.Rt = (hsr >> 5) & 0xf;
803 params.is_write = ((hsr & 1) == 0);
804
805 params.Op0 = 0;
806 params.Op1 = (hsr >> 16) & 0xf;
807 params.Op2 = 0;
808 params.CRn = 0;
809
810 /*
811 * Massive hack here. Store Rt2 in the top 32bits so we only
812 * have one register to deal with. As we use the same trap
813 * backends between AArch32 and AArch64, we get away with it.
814 */
815 if (params.is_write) {
816 u64 val = *vcpu_reg(vcpu, params.Rt);
817 val &= 0xffffffff;
818 val |= *vcpu_reg(vcpu, Rt2) << 32;
819 *vcpu_reg(vcpu, params.Rt) = val;
820 }
821
822 if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
823 goto out;
824 if (!emulate_cp(vcpu, &params, global, nr_global))
825 goto out;
826
827 unhandled_cp_access(vcpu, &params);
828
829 out:
830 /* Do the opposite hack for the read side */
831 if (!params.is_write) {
832 u64 val = *vcpu_reg(vcpu, params.Rt);
833 val >>= 32;
834 *vcpu_reg(vcpu, Rt2) = val;
835 }
836
837 return 1;
838 }
839
840 /**
841 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
842 * @vcpu: The VCPU pointer
843 * @run: The kvm_run struct
844 */
845 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
846 const struct sys_reg_desc *global,
847 size_t nr_global,
848 const struct sys_reg_desc *target_specific,
849 size_t nr_specific)
850 {
851 struct sys_reg_params params;
852 u32 hsr = kvm_vcpu_get_hsr(vcpu);
853
854 params.is_aarch32 = true;
855 params.is_32bit = true;
856 params.CRm = (hsr >> 1) & 0xf;
857 params.Rt = (hsr >> 5) & 0xf;
858 params.is_write = ((hsr & 1) == 0);
859 params.CRn = (hsr >> 10) & 0xf;
860 params.Op0 = 0;
861 params.Op1 = (hsr >> 14) & 0x7;
862 params.Op2 = (hsr >> 17) & 0x7;
863
864 if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
865 return 1;
866 if (!emulate_cp(vcpu, &params, global, nr_global))
867 return 1;
868
869 unhandled_cp_access(vcpu, &params);
870 return 1;
871 }
872
873 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
874 {
875 const struct sys_reg_desc *target_specific;
876 size_t num;
877
878 target_specific = get_target_table(vcpu->arch.target, false, &num);
879 return kvm_handle_cp_64(vcpu,
880 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
881 target_specific, num);
882 }
883
884 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
885 {
886 const struct sys_reg_desc *target_specific;
887 size_t num;
888
889 target_specific = get_target_table(vcpu->arch.target, false, &num);
890 return kvm_handle_cp_32(vcpu,
891 cp15_regs, ARRAY_SIZE(cp15_regs),
892 target_specific, num);
893 }
894
895 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
896 {
897 return kvm_handle_cp_64(vcpu,
898 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
899 NULL, 0);
900 }
901
902 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
903 {
904 return kvm_handle_cp_32(vcpu,
905 cp14_regs, ARRAY_SIZE(cp14_regs),
906 NULL, 0);
907 }
908
909 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
910 const struct sys_reg_params *params)
911 {
912 size_t num;
913 const struct sys_reg_desc *table, *r;
914
915 table = get_target_table(vcpu->arch.target, true, &num);
916
917 /* Search target-specific then generic table. */
918 r = find_reg(params, table, num);
919 if (!r)
920 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
921
922 if (likely(r)) {
923 /*
924 * Not having an accessor means that we have
925 * configured a trap that we don't know how to
926 * handle. This certainly qualifies as a gross bug
927 * that should be fixed right away.
928 */
929 BUG_ON(!r->access);
930
931 if (likely(r->access(vcpu, params, r))) {
932 /* Skip instruction, since it was emulated */
933 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
934 return 1;
935 }
936 /* If access function fails, it should complain. */
937 } else {
938 kvm_err("Unsupported guest sys_reg access at: %lx\n",
939 *vcpu_pc(vcpu));
940 print_sys_reg_instr(params);
941 }
942 kvm_inject_undefined(vcpu);
943 return 1;
944 }
945
946 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
947 const struct sys_reg_desc *table, size_t num)
948 {
949 unsigned long i;
950
951 for (i = 0; i < num; i++)
952 if (table[i].reset)
953 table[i].reset(vcpu, &table[i]);
954 }
955
956 /**
957 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
958 * @vcpu: The VCPU pointer
959 * @run: The kvm_run struct
960 */
961 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
962 {
963 struct sys_reg_params params;
964 unsigned long esr = kvm_vcpu_get_hsr(vcpu);
965
966 params.is_aarch32 = false;
967 params.is_32bit = false;
968 params.Op0 = (esr >> 20) & 3;
969 params.Op1 = (esr >> 14) & 0x7;
970 params.CRn = (esr >> 10) & 0xf;
971 params.CRm = (esr >> 1) & 0xf;
972 params.Op2 = (esr >> 17) & 0x7;
973 params.Rt = (esr >> 5) & 0x1f;
974 params.is_write = !(esr & 1);
975
976 return emulate_sys_reg(vcpu, &params);
977 }
978
979 /******************************************************************************
980 * Userspace API
981 *****************************************************************************/
982
983 static bool index_to_params(u64 id, struct sys_reg_params *params)
984 {
985 switch (id & KVM_REG_SIZE_MASK) {
986 case KVM_REG_SIZE_U64:
987 /* Any unused index bits means it's not valid. */
988 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
989 | KVM_REG_ARM_COPROC_MASK
990 | KVM_REG_ARM64_SYSREG_OP0_MASK
991 | KVM_REG_ARM64_SYSREG_OP1_MASK
992 | KVM_REG_ARM64_SYSREG_CRN_MASK
993 | KVM_REG_ARM64_SYSREG_CRM_MASK
994 | KVM_REG_ARM64_SYSREG_OP2_MASK))
995 return false;
996 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
997 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
998 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
999 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1000 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1001 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1002 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1003 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1004 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1005 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1006 return true;
1007 default:
1008 return false;
1009 }
1010 }
1011
1012 /* Decode an index value, and find the sys_reg_desc entry. */
1013 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1014 u64 id)
1015 {
1016 size_t num;
1017 const struct sys_reg_desc *table, *r;
1018 struct sys_reg_params params;
1019
1020 /* We only do sys_reg for now. */
1021 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1022 return NULL;
1023
1024 if (!index_to_params(id, &params))
1025 return NULL;
1026
1027 table = get_target_table(vcpu->arch.target, true, &num);
1028 r = find_reg(&params, table, num);
1029 if (!r)
1030 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1031
1032 /* Not saved in the sys_reg array? */
1033 if (r && !r->reg)
1034 r = NULL;
1035
1036 return r;
1037 }
1038
1039 /*
1040 * These are the invariant sys_reg registers: we let the guest see the
1041 * host versions of these, so they're part of the guest state.
1042 *
1043 * A future CPU may provide a mechanism to present different values to
1044 * the guest, or a future kvm may trap them.
1045 */
1046
1047 #define FUNCTION_INVARIANT(reg) \
1048 static void get_##reg(struct kvm_vcpu *v, \
1049 const struct sys_reg_desc *r) \
1050 { \
1051 u64 val; \
1052 \
1053 asm volatile("mrs %0, " __stringify(reg) "\n" \
1054 : "=r" (val)); \
1055 ((struct sys_reg_desc *)r)->val = val; \
1056 }
1057
1058 FUNCTION_INVARIANT(midr_el1)
1059 FUNCTION_INVARIANT(ctr_el0)
1060 FUNCTION_INVARIANT(revidr_el1)
1061 FUNCTION_INVARIANT(id_pfr0_el1)
1062 FUNCTION_INVARIANT(id_pfr1_el1)
1063 FUNCTION_INVARIANT(id_dfr0_el1)
1064 FUNCTION_INVARIANT(id_afr0_el1)
1065 FUNCTION_INVARIANT(id_mmfr0_el1)
1066 FUNCTION_INVARIANT(id_mmfr1_el1)
1067 FUNCTION_INVARIANT(id_mmfr2_el1)
1068 FUNCTION_INVARIANT(id_mmfr3_el1)
1069 FUNCTION_INVARIANT(id_isar0_el1)
1070 FUNCTION_INVARIANT(id_isar1_el1)
1071 FUNCTION_INVARIANT(id_isar2_el1)
1072 FUNCTION_INVARIANT(id_isar3_el1)
1073 FUNCTION_INVARIANT(id_isar4_el1)
1074 FUNCTION_INVARIANT(id_isar5_el1)
1075 FUNCTION_INVARIANT(clidr_el1)
1076 FUNCTION_INVARIANT(aidr_el1)
1077
1078 /* ->val is filled in by kvm_sys_reg_table_init() */
1079 static struct sys_reg_desc invariant_sys_regs[] = {
1080 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1081 NULL, get_midr_el1 },
1082 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1083 NULL, get_revidr_el1 },
1084 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1085 NULL, get_id_pfr0_el1 },
1086 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1087 NULL, get_id_pfr1_el1 },
1088 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1089 NULL, get_id_dfr0_el1 },
1090 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1091 NULL, get_id_afr0_el1 },
1092 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1093 NULL, get_id_mmfr0_el1 },
1094 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1095 NULL, get_id_mmfr1_el1 },
1096 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1097 NULL, get_id_mmfr2_el1 },
1098 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1099 NULL, get_id_mmfr3_el1 },
1100 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1101 NULL, get_id_isar0_el1 },
1102 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1103 NULL, get_id_isar1_el1 },
1104 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1105 NULL, get_id_isar2_el1 },
1106 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1107 NULL, get_id_isar3_el1 },
1108 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1109 NULL, get_id_isar4_el1 },
1110 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1111 NULL, get_id_isar5_el1 },
1112 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1113 NULL, get_clidr_el1 },
1114 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1115 NULL, get_aidr_el1 },
1116 { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1117 NULL, get_ctr_el0 },
1118 };
1119
1120 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
1121 {
1122 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1123 return -EFAULT;
1124 return 0;
1125 }
1126
1127 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
1128 {
1129 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1130 return -EFAULT;
1131 return 0;
1132 }
1133
1134 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1135 {
1136 struct sys_reg_params params;
1137 const struct sys_reg_desc *r;
1138
1139 if (!index_to_params(id, &params))
1140 return -ENOENT;
1141
1142 r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1143 if (!r)
1144 return -ENOENT;
1145
1146 return reg_to_user(uaddr, &r->val, id);
1147 }
1148
1149 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1150 {
1151 struct sys_reg_params params;
1152 const struct sys_reg_desc *r;
1153 int err;
1154 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1155
1156 if (!index_to_params(id, &params))
1157 return -ENOENT;
1158 r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1159 if (!r)
1160 return -ENOENT;
1161
1162 err = reg_from_user(&val, uaddr, id);
1163 if (err)
1164 return err;
1165
1166 /* This is what we mean by invariant: you can't change it. */
1167 if (r->val != val)
1168 return -EINVAL;
1169
1170 return 0;
1171 }
1172
1173 static bool is_valid_cache(u32 val)
1174 {
1175 u32 level, ctype;
1176
1177 if (val >= CSSELR_MAX)
1178 return false;
1179
1180 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
1181 level = (val >> 1);
1182 ctype = (cache_levels >> (level * 3)) & 7;
1183
1184 switch (ctype) {
1185 case 0: /* No cache */
1186 return false;
1187 case 1: /* Instruction cache only */
1188 return (val & 1);
1189 case 2: /* Data cache only */
1190 case 4: /* Unified cache */
1191 return !(val & 1);
1192 case 3: /* Separate instruction and data caches */
1193 return true;
1194 default: /* Reserved: we can't know instruction or data. */
1195 return false;
1196 }
1197 }
1198
1199 static int demux_c15_get(u64 id, void __user *uaddr)
1200 {
1201 u32 val;
1202 u32 __user *uval = uaddr;
1203
1204 /* Fail if we have unknown bits set. */
1205 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1206 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1207 return -ENOENT;
1208
1209 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1210 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1211 if (KVM_REG_SIZE(id) != 4)
1212 return -ENOENT;
1213 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1214 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1215 if (!is_valid_cache(val))
1216 return -ENOENT;
1217
1218 return put_user(get_ccsidr(val), uval);
1219 default:
1220 return -ENOENT;
1221 }
1222 }
1223
1224 static int demux_c15_set(u64 id, void __user *uaddr)
1225 {
1226 u32 val, newval;
1227 u32 __user *uval = uaddr;
1228
1229 /* Fail if we have unknown bits set. */
1230 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1231 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1232 return -ENOENT;
1233
1234 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1235 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1236 if (KVM_REG_SIZE(id) != 4)
1237 return -ENOENT;
1238 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1239 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1240 if (!is_valid_cache(val))
1241 return -ENOENT;
1242
1243 if (get_user(newval, uval))
1244 return -EFAULT;
1245
1246 /* This is also invariant: you can't change it. */
1247 if (newval != get_ccsidr(val))
1248 return -EINVAL;
1249 return 0;
1250 default:
1251 return -ENOENT;
1252 }
1253 }
1254
1255 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1256 {
1257 const struct sys_reg_desc *r;
1258 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1259
1260 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1261 return demux_c15_get(reg->id, uaddr);
1262
1263 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1264 return -ENOENT;
1265
1266 r = index_to_sys_reg_desc(vcpu, reg->id);
1267 if (!r)
1268 return get_invariant_sys_reg(reg->id, uaddr);
1269
1270 return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
1271 }
1272
1273 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1274 {
1275 const struct sys_reg_desc *r;
1276 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1277
1278 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1279 return demux_c15_set(reg->id, uaddr);
1280
1281 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1282 return -ENOENT;
1283
1284 r = index_to_sys_reg_desc(vcpu, reg->id);
1285 if (!r)
1286 return set_invariant_sys_reg(reg->id, uaddr);
1287
1288 return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
1289 }
1290
1291 static unsigned int num_demux_regs(void)
1292 {
1293 unsigned int i, count = 0;
1294
1295 for (i = 0; i < CSSELR_MAX; i++)
1296 if (is_valid_cache(i))
1297 count++;
1298
1299 return count;
1300 }
1301
1302 static int write_demux_regids(u64 __user *uindices)
1303 {
1304 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
1305 unsigned int i;
1306
1307 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
1308 for (i = 0; i < CSSELR_MAX; i++) {
1309 if (!is_valid_cache(i))
1310 continue;
1311 if (put_user(val | i, uindices))
1312 return -EFAULT;
1313 uindices++;
1314 }
1315 return 0;
1316 }
1317
1318 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
1319 {
1320 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
1321 KVM_REG_ARM64_SYSREG |
1322 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
1323 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
1324 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
1325 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
1326 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
1327 }
1328
1329 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
1330 {
1331 if (!*uind)
1332 return true;
1333
1334 if (put_user(sys_reg_to_index(reg), *uind))
1335 return false;
1336
1337 (*uind)++;
1338 return true;
1339 }
1340
1341 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
1342 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
1343 {
1344 const struct sys_reg_desc *i1, *i2, *end1, *end2;
1345 unsigned int total = 0;
1346 size_t num;
1347
1348 /* We check for duplicates here, to allow arch-specific overrides. */
1349 i1 = get_target_table(vcpu->arch.target, true, &num);
1350 end1 = i1 + num;
1351 i2 = sys_reg_descs;
1352 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
1353
1354 BUG_ON(i1 == end1 || i2 == end2);
1355
1356 /* Walk carefully, as both tables may refer to the same register. */
1357 while (i1 || i2) {
1358 int cmp = cmp_sys_reg(i1, i2);
1359 /* target-specific overrides generic entry. */
1360 if (cmp <= 0) {
1361 /* Ignore registers we trap but don't save. */
1362 if (i1->reg) {
1363 if (!copy_reg_to_user(i1, &uind))
1364 return -EFAULT;
1365 total++;
1366 }
1367 } else {
1368 /* Ignore registers we trap but don't save. */
1369 if (i2->reg) {
1370 if (!copy_reg_to_user(i2, &uind))
1371 return -EFAULT;
1372 total++;
1373 }
1374 }
1375
1376 if (cmp <= 0 && ++i1 == end1)
1377 i1 = NULL;
1378 if (cmp >= 0 && ++i2 == end2)
1379 i2 = NULL;
1380 }
1381 return total;
1382 }
1383
1384 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
1385 {
1386 return ARRAY_SIZE(invariant_sys_regs)
1387 + num_demux_regs()
1388 + walk_sys_regs(vcpu, (u64 __user *)NULL);
1389 }
1390
1391 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1392 {
1393 unsigned int i;
1394 int err;
1395
1396 /* Then give them all the invariant registers' indices. */
1397 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
1398 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
1399 return -EFAULT;
1400 uindices++;
1401 }
1402
1403 err = walk_sys_regs(vcpu, uindices);
1404 if (err < 0)
1405 return err;
1406 uindices += err;
1407
1408 return write_demux_regids(uindices);
1409 }
1410
1411 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
1412 {
1413 unsigned int i;
1414
1415 for (i = 1; i < n; i++) {
1416 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
1417 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
1418 return 1;
1419 }
1420 }
1421
1422 return 0;
1423 }
1424
1425 void kvm_sys_reg_table_init(void)
1426 {
1427 unsigned int i;
1428 struct sys_reg_desc clidr;
1429
1430 /* Make sure tables are unique and in order. */
1431 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
1432 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
1433 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
1434 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
1435 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
1436 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
1437
1438 /* We abuse the reset function to overwrite the table itself. */
1439 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
1440 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
1441
1442 /*
1443 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
1444 *
1445 * If software reads the Cache Type fields from Ctype1
1446 * upwards, once it has seen a value of 0b000, no caches
1447 * exist at further-out levels of the hierarchy. So, for
1448 * example, if Ctype3 is the first Cache Type field with a
1449 * value of 0b000, the values of Ctype4 to Ctype7 must be
1450 * ignored.
1451 */
1452 get_clidr_el1(NULL, &clidr); /* Ugly... */
1453 cache_levels = clidr.val;
1454 for (i = 0; i < 7; i++)
1455 if (((cache_levels >> (i*3)) & 7) == 0)
1456 break;
1457 /* Clear all higher bits. */
1458 cache_levels &= (1 << (i*3))-1;
1459 }
1460
1461 /**
1462 * kvm_reset_sys_regs - sets system registers to reset value
1463 * @vcpu: The VCPU pointer
1464 *
1465 * This function finds the right table above and sets the registers on the
1466 * virtual CPU struct to their architecturally defined reset values.
1467 */
1468 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
1469 {
1470 size_t num;
1471 const struct sys_reg_desc *table;
1472
1473 /* Catch someone adding a register without putting in reset entry. */
1474 memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
1475
1476 /* Generic chip reset first (so target could override). */
1477 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1478
1479 table = get_target_table(vcpu->arch.target, true, &num);
1480 reset_sys_reg_descs(vcpu, table, num);
1481
1482 for (num = 1; num < NR_SYS_REGS; num++)
1483 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
1484 panic("Didn't reset vcpu_sys_reg(%zi)", num);
1485 }
Michael's Linux tree.