arch/blackfin/cpu/u-boot.lds

   1 /*
   2  * U-Boot - u-boot.lds.S
   3  *
   4  * Copyright (c) 2005-2010 Analog Device Inc.
   5  *
   6  * (C) Copyright 2000-2004
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13 #include <asm/blackfin.h>
  14 #undef ALIGN
  15 #undef ENTRY
  16
  17 #ifndef LDS_BOARD_TEXT
  18 # define LDS_BOARD_TEXT
  19 #endif
  20
  21 /* If we don't actually load anything into L1 data, this will avoid
  22  * a syntax error.  If we do actually load something into L1 data,
  23  * we'll get a linker memory load error (which is what we'd want).
  24  * This is here in the first place so we can quickly test building
  25  * for different CPU's which may lack non-cache L1 data.
  26  */
  27 #ifndef L1_DATA_A_SRAM
  28 # define L1_DATA_A_SRAM      0
  29 # define L1_DATA_A_SRAM_SIZE 0
  30 #endif
  31 #ifndef L1_DATA_B_SRAM
  32 # define L1_DATA_B_SRAM      L1_DATA_A_SRAM
  33 # define L1_DATA_B_SRAM_SIZE L1_DATA_A_SRAM_SIZE
  34 #endif
  35
  36 /* The 0xC offset is so we don't clobber the tiny LDR jump block. */
  37 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
  38 # define L1_CODE_ORIGIN L1_INST_SRAM
  39 #else
  40 # define L1_CODE_ORIGIN L1_INST_SRAM + 0xC
  41 #endif
  42
  43 OUTPUT_ARCH(bfin)
  44
  45 MEMORY
  46 {
  47 #if CONFIG_MEM_SIZE
  48         ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
  49 # define ram_code ram
  50 # define ram_data ram
  51 #else
  52 # define ram_code l1_code
  53 # define ram_data l1_data
  54 #endif
  55         l1_code : ORIGIN = L1_CODE_ORIGIN,          LENGTH = L1_INST_SRAM_SIZE
  56         l1_data : ORIGIN = L1_DATA_B_SRAM,          LENGTH = L1_DATA_B_SRAM_SIZE
  57 }
  58
  59 ENTRY(_start)
  60 SECTIONS
  61 {
  62         .text.pre :
  63         {
  64                 arch/blackfin/cpu/start.o (.text .text.*)
  65
  66                 LDS_BOARD_TEXT
  67         } >ram_code
  68
  69         .text.init :
  70         {
  71                 arch/blackfin/cpu/initcode.o (.text .text.*)
  72         } >ram_code
  73         __initcode_lma = LOADADDR(.text.init);
  74         __initcode_len = SIZEOF(.text.init);
  75
  76         .text :
  77         {
  78                 *(.text .text.*)
  79         } >ram_code
  80
  81         .rodata :
  82         {
  83                 . = ALIGN(4);
  84                 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
  85                 . = ALIGN(4);
  86         } >ram_data
  87
  88         .data :
  89         {
  90                 . = ALIGN(4);
  91                 *(.data .data.*)
  92                 *(.data1)
  93                 *(.sdata)
  94                 *(.sdata2)
  95                 *(.dynamic)
  96                 CONSTRUCTORS
  97         } >ram_data
  98
  99
 100         .u_boot_list : {
 101                 KEEP(*(SORT(.u_boot_list*)));
 102         } >ram_data
 103
 104         .text_l1 :
 105         {
 106                 . = ALIGN(4);
 107                 __stext_l1 = .;
 108                 *(.l1.text)
 109                 . = ALIGN(4);
 110                 __etext_l1 = .;
 111         } >l1_code AT>ram_code
 112         __text_l1_lma = LOADADDR(.text_l1);
 113         __text_l1_len = SIZEOF(.text_l1);
 114         ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!")
 115
 116         .data_l1 :
 117         {
 118                 . = ALIGN(4);
 119                 __sdata_l1 = .;
 120                 *(.l1.data)
 121                 *(.l1.bss)
 122                 . = ALIGN(4);
 123                 __edata_l1 = .;
 124         } >l1_data AT>ram_data
 125         __data_l1_lma = LOADADDR(.data_l1);
 126         __data_l1_len = SIZEOF(.data_l1);
 127         ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data overflow!")
 128
 129         .bss :
 130         {
 131                 . = ALIGN(4);
 132                 *(.sbss) *(.scommon)
 133                 *(.dynbss)
 134                 *(.bss .bss.*)
 135                 *(COMMON)
 136                 . = ALIGN(4);
 137         } >ram_data
 138         __bss_end = .;
 139         __bss_start = ADDR(.bss);
 140         __bss_len = SIZEOF(.bss);
 141         __init_end = .;
 142 }