arch/cris/arch-v10/kernel/time.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  linux/arch/cris/arch-v10/kernel/time.c
   4  *
   5  *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
   6  *  Copyright (C) 1999-2002 Axis Communications AB
   7  *
   8  */
   9
  10 #include <linux/timex.h>
  11 #include <linux/time.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/swap.h>
  15 #include <linux/sched.h>
  16 #include <linux/init.h>
  17 #include <linux/mm.h>
  18 #include <asm/types.h>
  19 #include <asm/signal.h>
  20 #include <asm/io.h>
  21 #include <asm/delay.h>
  22 #include <asm/irq_regs.h>
  23
  24 /* define this if you need to use print_timestamp */
  25 /* it will make jiffies at 96 hz instead of 100 hz though */
  26 #undef USE_CASCADE_TIMERS
  27
  28 unsigned long get_ns_in_jiffie(void)
  29 {
  30         unsigned char timer_count, t1;
  31         unsigned short presc_count;
  32         unsigned long ns;
  33         unsigned long flags;
  34
  35         local_irq_save(flags);
  36         timer_count = *R_TIMER0_DATA;
  37         presc_count = *R_TIM_PRESC_STATUS;
  38         /* presc_count might be wrapped */
  39         t1 = *R_TIMER0_DATA;
  40
  41         if (timer_count != t1){
  42                 /* it wrapped, read prescaler again...  */
  43                 presc_count = *R_TIM_PRESC_STATUS;
  44                 timer_count = t1;
  45         }
  46         local_irq_restore(flags);
  47         if (presc_count >= PRESCALE_VALUE/2 ){
  48                 presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
  49         } else {
  50                 presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
  51         }
  52
  53         ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
  54              ( (presc_count) * (1000000000/PRESCALE_FREQ));
  55         return ns;
  56 }
  57
  58 static u32 cris_v10_gettimeoffset(void)
  59 {
  60         u32 count;
  61
  62         /* The timer interrupt comes from Etrax timer 0. In order to get
  63          * better precision, we check the current value. It might have
  64          * underflowed already though.
  65          */
  66         count = *R_TIMER0_DATA;
  67
  68         /* Convert timer value to nsec */
  69         return (TIMER0_DIV - count) * (NSEC_PER_SEC/HZ)/TIMER0_DIV;
  70 }
  71
  72 /* Excerpt from the Etrax100 HSDD about the built-in watchdog:
  73  *
  74  * 3.10.4 Watchdog timer
  75
  76  * When the watchdog timer is started, it generates an NMI if the watchdog
  77  * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
  78  * stopped after an additional 3.3 ms, the watchdog resets the chip.
  79  * The watchdog timer is stopped after reset. The watchdog timer is controlled
  80  * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
  81  * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
  82  * described in the table below:
  83  *
  84  *   Watchdog    Value written:
  85  *   state:      To enable:  To key:      Operation:
  86  *   --------    ----------  -------      ----------
  87  *   stopped         0         X          No effect.
  88  *   stopped         1       key_val      Start watchdog with key = key_val.
  89  *   started         0       ~key         Stop watchdog
  90  *   started         1       ~key         Restart watchdog with key = ~key.
  91  *   started         X       new_key_val  Change key to new_key_val.
  92  *
  93  * Note: '~' is the bitwise NOT operator.
  94  *
  95  */
  96
  97 /* right now, starting the watchdog is the same as resetting it */
  98 #define start_watchdog reset_watchdog
  99
 100 #ifdef CONFIG_ETRAX_WATCHDOG
 101 static int watchdog_key = 0;  /* arbitrary number */
 102 #endif
 103
 104 /* number of pages to consider "out of memory". it is normal that the memory
 105  * is used though, so put this really low.
 106  */
 107
 108 #define WATCHDOG_MIN_FREE_PAGES 8
 109
 110 void reset_watchdog(void)
 111 {
 112 #if defined(CONFIG_ETRAX_WATCHDOG)
 113         /* only keep watchdog happy as long as we have memory left! */
 114         if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
 115                 /* reset the watchdog with the inverse of the old key */
 116                 watchdog_key ^= 0x7; /* invert key, which is 3 bits */
 117                 *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
 118                         IO_STATE(R_WATCHDOG, enable, start);
 119         }
 120 #endif
 121 }
 122
 123 /* stop the watchdog - we still need the correct key */
 124
 125 void stop_watchdog(void)
 126 {
 127 #ifdef CONFIG_ETRAX_WATCHDOG
 128         watchdog_key ^= 0x7; /* invert key, which is 3 bits */
 129         *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
 130                 IO_STATE(R_WATCHDOG, enable, stop);
 131 #endif
 132 }
 133
 134
 135 extern void cris_do_profile(struct pt_regs *regs);
 136
 137 /*
 138  * timer_interrupt() needs to keep up the real-time clock,
 139  * as well as call the "xtime_update()" routine every clocktick
 140  */
 141 static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
 142 {
 143         struct pt_regs *regs = get_irq_regs();
 144         /* acknowledge the timer irq */
 145
 146 #ifdef USE_CASCADE_TIMERS
 147         *R_TIMER_CTRL =
 148                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 149                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 150                 IO_STATE( R_TIMER_CTRL, i1, clr) |
 151                 IO_STATE( R_TIMER_CTRL, tm1, run) |
 152                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 153                 IO_STATE( R_TIMER_CTRL, i0, clr) |
 154                 IO_STATE( R_TIMER_CTRL, tm0, run) |
 155                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 156 #else
 157         *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i0, clr);
 158 #endif
 159
 160         /* reset watchdog otherwise it resets us! */
 161         reset_watchdog();
 162
 163         /* Update statistics. */
 164         update_process_times(user_mode(regs));
 165
 166         /* call the real timer interrupt handler */
 167         xtime_update(1);
 168
 169         cris_do_profile(regs); /* Save profiling information */
 170         return IRQ_HANDLED;
 171 }
 172
 173 /* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain */
 174
 175 static struct irqaction irq2  = {
 176         .handler = timer_interrupt,
 177         .flags = IRQF_SHARED,
 178         .name = "timer",
 179 };
 180
 181 void __init time_init(void)
 182 {
 183         arch_gettimeoffset = cris_v10_gettimeoffset;
 184
 185         /* probe for the RTC and read it if it exists
 186          * Before the RTC can be probed the loops_per_usec variable needs
 187          * to be initialized to make usleep work. A better value for
 188          * loops_per_usec is calculated by the kernel later once the
 189          * clock has started.
 190          */
 191         loops_per_usec = 50;
 192
 193         /* Setup the etrax timers
 194          * Base frequency is 25000 hz, divider 250 -> 100 HZ
 195          * In normal mode, we use timer0, so timer1 is free. In cascade
 196          * mode (which we sometimes use for debugging) both timers are used.
 197          * Remember that linux/timex.h contains #defines that rely on the
 198          * timer settings below (hz and divide factor) !!!
 199          */
 200
 201 #ifdef USE_CASCADE_TIMERS
 202         *R_TIMER_CTRL =
 203                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 204                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 205                 IO_STATE( R_TIMER_CTRL, i1, nop) |
 206                 IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
 207                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 208                 IO_STATE( R_TIMER_CTRL, i0, nop) |
 209                 IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
 210                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 211
 212         *R_TIMER_CTRL = r_timer_ctrl_shadow =
 213                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 214                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 215                 IO_STATE( R_TIMER_CTRL, i1, nop) |
 216                 IO_STATE( R_TIMER_CTRL, tm1, run) |
 217                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 218                 IO_STATE( R_TIMER_CTRL, i0, nop) |
 219                 IO_STATE( R_TIMER_CTRL, tm0, run) |
 220                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 221 #else
 222         *R_TIMER_CTRL =
 223                 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
 224                 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 225                 IO_STATE(R_TIMER_CTRL, i1,        nop)      |
 226                 IO_STATE(R_TIMER_CTRL, tm1,       stop_ld)  |
 227                 IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 228                 IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 229                 IO_STATE(R_TIMER_CTRL, tm0,       stop_ld)  |
 230                 IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
 231
 232         *R_TIMER_CTRL = r_timer_ctrl_shadow =
 233                 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
 234                 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 235                 IO_STATE(R_TIMER_CTRL, i1,        nop)      |
 236                 IO_STATE(R_TIMER_CTRL, tm1,       run)      |
 237                 IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 238                 IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 239                 IO_STATE(R_TIMER_CTRL, tm0,       run)      |
 240                 IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
 241
 242         *R_TIMER_PRESCALE = PRESCALE_VALUE;
 243 #endif
 244
 245         /* unmask the timer irq */
 246         *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer0, set);
 247
 248         /* now actually register the irq handler that calls timer_interrupt() */
 249         setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
 250
 251         /* enable watchdog if we should use one */
 252 #if defined(CONFIG_ETRAX_WATCHDOG)
 253         printk("Enabling watchdog...\n");
 254         start_watchdog();
 255
 256         /* If we use the hardware watchdog, we want to trap it as an NMI
 257            and dump registers before it resets us.  For this to happen, we
 258            must set the "m" NMI enable flag (which once set, is unset only
 259            when an NMI is taken).
 260
 261            The same goes for the external NMI, but that doesn't have any
 262            driver or infrastructure support yet.  */
 263         asm ("setf m");
 264
 265         *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
 266         *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, nmi, set);
 267 #endif
 268 }